for CMS experiment- Data CompressionDecompression System and Pattern Comparator ASIC
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for CMS experiment -Data Compression/Decompression System and Pattern Comparator ASICMaciej Gorski a), Zbigniew Jaworski b), Ignacy M. Kudla c), Wieslaw Kuzmicz b),Mariusz Niewczas b), Krzysztof T. Pozniak b)a) Soltan Institute of Nuclear Studies, b) Warsaw University of Technology, c) Warsaw UniversityAbstractCMS detector will have a dedicated subdetector (RPC chambers) to identify muons, measure their transverse momenta pt, and determine the bunch crossings from which they originate. Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers grouped in the four muon stations in the CMS magnet yoke. A huge interconnection network is needed to fulfill this task. It can be built in the control room only, approximately 120 m away from the detector.The data compression/decompression system is proposed to reduce the number of links needed to transfer the data from detector to control room. The idea of such a system and results of first tests will be presented.Trigger algorithm is based on muon track search and classification in raw data from the RPC chambers grouped in the four muon stations in the CMS magnet yoke. PAttern Comparator (PAC) ASIC will search for tracks of muons and measure their momenta. Idea of PAC and its first prototype implementation are shown---------------------------------------------------------------------------------------------------------------------------------------------------------------1. IntroductionPattern Comparator Trigger (PACT) system for CMS experiment deal with row data from 4 planes of RPC muon chambers located in the magnet iron return yoke of CMS detector [1]. Due to the bending of muon tracks in magnetic field the same data are used in different elements of PACT scheme. Searching algorithm of PACT need data (properly aligned in time) from many planes of RPC distributed over big area of CMS detector. To avoid huge interconections network on detector PACT electronics will be located in counting room, about 100 m from CMS detector.1.1 Data Compression/Decompression SystemTransfer of all uncompressed RPC data to the counting room need big number of expensive optical links. The rate of hits for a single bunch crossing in RPC chamber is relatively low (see Fig 1. )MB 4MB 3Fig 1. Expected hit rate for the CMS detector PACT trigger algorithm is faster then other elements of trigger system of CMS.It allow to use certain fixed amount of bunch crossing periods to compress data at detector level, send them over the optical link, and to decompress them after arriving to the PACT trigger boards.The distribution of the hit rate in the detector is not homogeneous (see Fig 1.). This implies that for the areas of higher hits rate a bigger numbers of links are required.The important constraint of this type of selective readout is level of allowed data loss. The assumed data loss threshold of the order of 10-6 results in trigger efficiency loss not greater than 1% [4]. If this value is taken as a project definition – total number of links will be reduced by a factor of at least six in comparison with the non-compressed data transmition. Fig 3. shows the functional blocks of electronics and their locations when comression/decompression devices are used and compression factor is maximal.1.2 PAttern Comparator ASICRPC muon trigger for CMS experiment is based on dataHigh Pt Muonpattern: (0,0,0)defined on 4 layersFig 2. General idea of PACT triggerfrom 4 RPC planes. RPC planes are located [5] in each muon station placed inside of iron return magnet yoke. RPC cover the η-range up to |η| = 2.1 [6]. RPC are read out by strips covering ∆η = .1 and ∆φ = 5/16° each. For low pt muons, when the resolution is limited by multiple scattering, the strips are grouped by 2 or 4 depending of the momentum. The region of detector covering ∆η = .1 and ∆φ = 2.5° (defined at level of muon station 2 – reference) is called segment and is providing information on one, the highest momentum muon passing by covered region. This information is: polarity of muon, quality bitproportional to the momentum of muon. Fig 2. shows the algorithm of Pattern Comparator Trigger (PACT). It is based on comparison of patterns of hits from 4 RPC planes with predefined valid patterns. Two differently shaded areas show two overlapping sets of strips connected to two neighboaring PAC processors [9,10,11].The valid patterns are first obtained from simulation and will be corrected later using real reconstructed muon tracks.Maximum number of patterns needed per hit from the reference plane is 160. Trigger information must be provided without dead time. Pattern Comparator (PAC) ASIC is the device which fulfills the requirements of PACT algorithm.2.1 The algorithm of compression and decompression Many different data compression styles are possible [2].Here a simple one – easy to implement - is shown. Data are divided into equal length data partitions. Each non-empty partition is sent together with its partion number and delay value. The latter defines the delay (in bunch crossings) of the partition just being sent relative to the bunch crossing associated with a given data word. The non-empty partitions of every data word are sent in descending order starting from the partition of the highest number.Fig 3. Functional blocks of electronics of RPC based muon trigger system for CMS experimentAn example of compression/decompression system is presented in Fig 4. Instead of 24 bits - only 9 bits are send every bunch crossing. In above example, the first data word (bx=0) has two non-empty partitions. The P5 partition is sent immediately,and the value of its delay is zero. During the next bunch crossing the P3 partition is sent with a delay w.r.t the data word of oneFig 4. Example of commpressed/ decompressed data bunch crossing. From now on, a stream of transmitted partitions belonging to the same data word and the same bunch crossingempty partitions. The P2 partition is delayed by one bunchcrossing, and for next partitions (P1 and P0) this delay increases by every time. The packet decompression is bases on data retrieval from transmitted partitions in one packet. Maintaining a constant delay between the compression and decompression processes requires a given value of the maximum delay value.Precisely after this number of bunch crossings, a decompressed data word will be generated.The partitions with a delay greater than this defined maximum value will be lost. When the compression circuit does not have a non-empty partition to send, an empty partition is sent to keep synchronization. In above example, data words are constant value equal to the sum of maximum delay value (4) and delayed at level of the output of decompressing device by the transmission latency (16).2.2 The data compression circuit – LMUXLMUX realizes the data compression algorithm. Its structure is presented in Fig. 4. New data are introduced for each bunchFig 5. Data compression circuitcrossing. A block of input latches synchronizes the data with an internal clock. The data possessing at least one non-empty partition are stored in a FIFO memory. The maximal length of FIFO memory is equal to maximal delay value. The data from FIFO memory are shifted to PACKET CONSTRUCTOR. The PACKET CONSTRUCTOR selects non-empty partitions and supplies them with partiton numbers and delay values. Sending of current data word is aborted when the maximal delay value is reached. In such a case the last partition has the overload flag set. This flag denotes that the data word beeing sent is not complete.When the PACKET CONSTRUCTOR does not have a non-empty partition to send, an empty partition is sent. This partition has a non existing partition number.Additionally LMUX is equipped with a PACKET MULTIPLEXER. This is intended to merge data from several neighbouring RPCs (maximum two) and to send their data by a single optical link. Each packet contains, therefore, the RPC chamber number in addition. The PACKET MULTIPLEXER is preceded by a block of latches. These latches equalize relative delays between streams of packets from different RPCs.2.3. The data decompression circuit – LDEMUXLDEMUX realizes data decompression algorithm. Its structure is presented on Fig 6. A single LDEMUX circuit works for one chamber only. Only partitions from this, selected chamber are accepted (the chamber number is compared to the BASE NUMBER). The accepted partitions are fed in to the SHIFT REGISTERS. A shift register consists of D+1 positions, where D is the maximum delay value. Each position of the SHIFT REGISTER has DELAY INDEX assigned to it, with values from 0 to D. If the partition’s delay value is equal to DELAY INDEX then the partition data are shifted, via the demultiplexer,number.Fig 6. Data decompression circuitThe partition, which was sent immediately by LMUX, i.e. one with zero delay value, is fed into LDEMUX when it reaches the end of the SHIFT REGISTERS (DELAY INDEX=0). On the contrary, the partition with the maximum delay value will be fed into LDEMUX immediately. The method provides compensation of delays between LMUX and LDEMUX circuits.When LDEMUX receives a broken data packet (with set overload flag), the output data are modified according to a special algorithm (for example, all bits of data word are zeroed).2.4 LMUX and DEMUX testsLMUX and DEMUX tests were realized in Altera CPLD devices. Because of the size of selected Altera circuits (EPF8820), the test project assumed the following parameters of compression/decompression set - 20-bit length data word, 4-bit partition word , maximum delay equal 4.The test circuit was built as the VME board. Test data were generated by a FDPM card (CERN, RD12). Results have been checked with a HP LSA 1662C. The total latency of compression and decompression circuits is 9 clock periods.Maximum frequency of LMUX/DEMUX test circuit (with Flex 8820AGC-4) was 24Mhz.3.1 General Description of PAC architectureIn general PAC can be considered as a kind of Content Addressable Memory (CAM) - for every input value (54 signals from 4 layers of muon chambers) a 7 bit code (the highest momentum muon code) - is presented. Up to 160 patterns can be programmed into PAC for each hit from060606 06Fig 7. General view of PAC ASICcrosses on Fig 7. Upper part of a drawing shows programmable track definition (see Fig 8), the lower part – code programming and selection. Only the highest code is presented on the output.Output code equal “0” mean, that no pattern match was found.PAC is a synchronous, pipelined and dead time free device - output signal is produced each clock cycle and corresponds to the value of the input signals from two clock cycles before.Programming of internal memory (patterns and codes) is done by use of Boundary Scan Test (BST) circuit.3.2 Track recognition circuitFig 8. shows how one track coressponding to a particular pattern (1,15,2) is recognized in PAC. Patterns are written via JTAG interface to the registers which control multiplexers. Only one signal goes from each multiplexer to the 3_ or 4_point track definition circuit. This circuit provides track,MS4MS3MS1MS2pattern Fig 8. Track recognition circuitdefined as a 4_point track (coincidence of signals from 4MS planes) in presence of qbit_in signal. If qbit_in signal is absent, a 3_point track signal (one of four possible 3-fold coincidences of signals from 4 planes) is allowed to go out of circuit. Qbit_in signal is the logical OR of all 4_point_track signals from PAC.For every strip in so called reference station (MS2 on Fig 7.)signal there are 160 such blocks.3.3 Track code programming and selection circuitEach track which can be defined in track recognition circuit of PAC can have its own code. All 160 tracks corresponding toFig 9. Track code programming and selection circuitgroups of positive and negative tracks, each has 80 tracks. Fig 9. shows track code programming and selection circuit. In this example tracks 1 and 160 are programmed to code 1, tracks 80 and 81 – to code 15. Programming of track code is done by writing (via boundary scan circuit) a control register of the demultiplexer (DMX). Only one output line of DMX is selected. The outputs of the negative and positive groups of DMX's are wired OR-ed together and placed separately to the input of the highest code selection circuit. Every clock cycle the highest code selection circuit choose the highest of the present code lines.3.4 Mask and Cascade circuitsEvery input signal can be masked to deal with the faulty strip signals as well as output mask register can mask faulty PAC output. Cascade circuit allows to cascade PAC’s to build segment processor from 3-4 PAC’s if needed.3.5. Boundary Scan Test CircuitPAC is equiped with (BST )Boundary Scan Test (JTAG) circuit defined by IEEE 1149.1 standard. Three mandatory (EXTEST, BYPASS, SAMPLE/PRELOAD) and two optional (INTEST, IDCODE) boundary scan functions are implemented.BST circuit is used to test the pins of PAC and to program PAC functions. Four BST user_data_registers are used to program patterns and codes coresponding to four reference strips and one to program input, output mask registers and cascade control circuit.4. Conclusions1. The algorithm of synchronous compression and decompression was investigated. The simulational results for the Altera were confronted with the measurements on a test device. The agreement between the simulation and measurments was fair. This is encouraging for further work on compression and decompression circuits - for LMUX, LDEMUX ASIC’s construction.CMS ASIC version of LMUX, DEMUX needs 96-bit data word, 12-bit partitions (or 8-bit partition), maximum delay 7 and multiplexing of input data (up to 3 data streams).VHDL description of full LMUX and LDEMUX ASIC is under simulation.different ALTERA CPLD’s. They encouraged us to propose ASIC design. The three different small prototype devices has been produced before launching the PAC demonstrator ASIC production. Main building blocks has been successfully tested using these prototype devices. PAC demonstrator has been produced and delivered at the end of February 1998. It contains full logic for 4 strips from the reference plane, cascade logic and boundary scan circuits. It has been produced using ATMEL ES2 0.8 technology. Total die surface is 8.8 * 7.5 mm2. The die was packed into a 144 pin PGA package. Test board, and programs has been developed for testing PAC demonstrator.References1.Jaworski Z. et. al., Resistive Plate Chamber (RPC) basedMuon Trigger System for CMS experiment - PAttern Comparator ASIC, this precedings;2.Bondestam,N. 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Wrochna, Simulationstudy of the single muon, RPC based trigger for CMS,CMS Technical Note, CMS TN/92-39;11.M.Andlinger et al., Pattern Comparator Trigger (PACT) forthe Muon System of the CMS experiment,NIM.A370(1996)389;12.Z.Jaworski et al., VLSI implementation of the RPC PatternComparator (PAC) ASIC for CMS experiment - Feasibility Study CMS Technical Note, CMS TN/96-003This work was partially financed by Polish Committee for Scientific Research under group KBN 115/E-343/SPUB/P03/119/96 and KBN 115/E-343/SPUB/P03/004/97。