$sdf_annotate用法

★ ISE详细步骤、作用及其理解：这里把仿真单独编号1）新建工程2）生成原文件手段CORE Generator ModuleLanguage Templates3） check syntax①Behavioral simulate我觉得从Synthesis and Simulation Design Guide文件看，应该先RTL Simulation (that is, Behavioral simulate )。

其实没有关系，综合和RTL仿真的顺序无所谓，这两个不一定要谁在前己见：注意跑行为仿真前是不需要综合的，仅是RTL代码仿真参考：[In-Depth Tutorial] Chapter 4 P914） Synthesis步骤：Entering Constraints (xcf格式) -> Entering Synthesis Options -> Synthsizing参考：[In-Depth Tutorial]P43-P50我觉得这里的constraints是 synthesis constraints：《cgd》p18已见：参《Xilinx ISE 9.X FPGA/CPLD设计指南（人民邮电）》P31综合是把HDL描述转化为使用基本门电路以及厂家库提供的基本单元进行描述的网表(Netlist)的过程。

综合时需要附加一定的约束，指导综合过程的进行，最常用的约束有管脚位置约束和附加时序约束② Post- Synthesis Simulation这里以《夏宇闻》第17章的设计为例，前面行为仿真时可以直接仿真cputop模块（专为仿真写的，不可综合），但在synthesize时，必须把cpu模块Set as Top Module,因为cputop模块是不可综合的，然后点击Generate Post-Synthesis Simulation Model,可以注意到原文件夹下会生成netgen文件夹，打开会发现有synthsis文件夹，里面有cpu_synthesis.v 文件，这个文件是专门用来仿真的。

Verilog 中常用的系统函数(2011-12-06 14:54:39)转载▼标签：分类：FPGA的研究杂谈Verilog HDL常用的系统任务1.$display(<输出格式控制列表>,<输出列表>)；//显示变量的值或变量的范围，自动加换行如：$display(“dout=%d dout”,dout);2.$write();//和上面的用法相同，但是不会自动加换行3.$monitor(<格式控制>，<输出列表>);//在多模块调试的情况下，许多模块中都调用了$monitor,因为任何时刻只能有一个$monitor起作用，因此需配合$monitoron与$monitoroff使用，把需要监视的模块用$monitoron打开，在监视完毕后及时用$monitoroff关闭，以便把$monitor 让给其他模块使用。

$monitor与$display的不同处还在于$monitor 往往在initial块中调用，只要不调用$monitoroff,$monitor便不间断地对所设定的信号进行监视。

4.$time系统函数：返回64位的整数来表示当前的仿真时刻； $realtime系统函数：返回一个实型数表示当前仿真时刻。

都以模块的仿真时间尺度为基准。

5.$monitor($realtime,,"set=%b",set);//其中一个用法5.系统任务$finish:退出仿真器，返回操作系统6.系统任务$stop：暂停仿真器7.系统任务$random:$random%b或者{$random}%b8.系统任务$readmemb和$readmemh:用于从文件中读取数据到寄存器中，任何时候都可以被执行（数据方向：文件>>寄存器）；有以下用法：1) $readmemb("<数据文件名>",<存贮器名>);2) $readmemb("<数据文件名>",<存贮器名>,<起始地址>);3) $readmemb("<数据文件名>",<存贮器名>,<起始地址>,<结束地址>);4) $readmemh("<数据文件名>",<存贮器名>);5) $readmemh("<数据文件名>",<存贮器名>,<起始地址>);6) $readmemh("<数据文件名>",<存贮器名>,<起始地址>,<结束地址>);其中文件中的地址表示方式@hhhh--hh,但是寄存器中的地址可直接用数表示。

1.常见错误：Failed to find INSTANCE ...，问题出在下面所示的第2步或第4步。

正确处理步骤：（1）Quartus中编译测试码欲调用的顶层模块（设模块名：xxx），设置EDA tool 的simulation 工具，如verilog ,以产生xxx.vo文件及xxx_v.sdo延时文件；（2）打开modelsim，新建工程，添加xxx.vo文件、测试用激励波形文件testbench.v、所用器件的网表文件(以cyclone为例：$Quartus\eda\sim_lib\cyclone_atoms.v)。

全部编译。

！！：确认testbench.v中不包含顶层模块xxx代码。

（3）xxx_v.sdo复制到modelsim工程目录。

（4）最后，建立仿真配置文件：在workspace的project页中右键单击，选simulation configuration，如下图于是,workspace中得到simulation 1。

按下图设置：注意，上面的框中添加xxx_v.sdo，下面的文本框中设置作用域，格式为：\testbench模块名\xxx的实例名。

（5）`timescale 影响仿真结果显示效果。

=================例===================[1]//文件count4.vmodule count4(out,reset,clk);output[3:0] out;input reset, clk;reg[3:0] out;always @(posedge clk)beginif (reset)out <= 0;elseout <= out + 1;endendmodule[2]//测试文件count_tp.v`timescale 1ns/1nsmodule count_tp;reg clk,reset;wire[3:0] out;parameter DELY = 100;count4 mycount(out,reset,clk);always #(DELY/2) clk = ~clk;initialbeginclk = 0; reset = 0;#DELY reset = 1;#DELY reset = 0;#(DELY*20) $finish;endinitial $monitor($time,,,"clk=%d reset=%d out=%d",clk,reset,out); endmodule[3]所用器件：cyclone[4]结果：明显产生了时延p.s.-----------------------网上有朋友指出勾选SDF中的两个选项，将原来的警告禁止，将原来的错误变为警告, 可以成功地进行反标注并运行仿真，但这样做并没有解决实际问题,只能产生功能仿真，没有得到带时延的时序仿真2.** Error: D:/ModelSim_6.5/ModelSimnear "'t": Illegal base specifier in numeric constant.syntax error, unexpected "BASE", expecting "class"错误原因：不是’timescale 而是`timescale，那个是键盘左上角的点，不是一撇。

VCS仿真指南VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式;使用的步骤和modelsim类似,都要先做编译,再调用仿真.Vcs包括两种调试界面:Text-based:Command Line Interface(CLI) 和GUI-based(VirSim);仿真主要的两个步骤是编译,运行:>vcs design.v//编译verilog的源文件并且生成一个可执行文件simv>simv//运行simv一般情况下都存在vcs 做编译的时候的compile_time_options和运行时候的run_time_options,这些我们在下面再具体介绍.一.VCS的三种调试模式使用vcs存在三种调试模式:CLI调试模式,VirSim交互调试模式和VirSim后处理调试模式.下面举例说明: 1. CLI调试模式CLI调试模式存在两种调用方法,一种是编译后马上执行,一种是把编译执行分开处理>vcs source.v +cli+3 –R –s或者>vcs source.v +cli+3>simv source.v –s其中+cli+[1 2 3 4]是指调试时候交互调试的能力.+cli+[<module_name>=]1|2|3|4Enable CLI debugging.1 enables you to see the values of nets and registers and deposit values to registers.2 also enables breakpoints on value changes of nets and registers.3 also enables you to force a value on nets.4 also enables you to force a value on a register.You can specify a module to enable CLI debugging only for instances of the module.-line 能够支持单步调试但是这些都是会增加运行时间的.这里不详细介绍CLI 命令具体可以参考usrerguide.注意我们也可以把CLI的命令写成一个script的文件在vcs编译时调用.>vcs source.v –R –s –include script_file或者在cli下调用cli>source script_file2. VirSim交互调试模式启动VirSim交互调试模式和调用CLI一样也是有两中方法.>vcs source.v –RI –line +vcsd +cfgfile+filename或者>vcs source.v –I –line +vcsd>vcs source.v -RIG +cfgfile+filename其中-RI 作用有两个:编译生成可以在VirSim中可执行的文件并且编译后马上启动Virsim;要编译成可以在VirSim中可执行的文件必须在编译阶段加-I,在要生成vcd或vpd时这个参数一定要添加;-RIG通过一个已编译完成的默认的simv文件启动Virsim,在启动之前一定要通过vcs –RI或者-I对源文件做过编译.使用vcs编译源文件之后会发现目录下多了simv和/csrc等文件,其中simv是默认的可执行文件,可以在vcs 做编译的时候–o filename改变输出的名字,/csrc是存的增量编译的结果,/simv.daidir如果设置中使用到了PLI就会创建.具体如何使用VirSim做交互调试这里也不具体介绍,可以参考VirSim的userguide和vcs安装下面的doc 的tutorial.3. VirSim的后处理调试模式注意什么时候用后处理调试模式,什么时候使用交换模式那?在初步仿真的过程使用交互模式,若是调试一个成熟的设计或者很多人一起做调试这样子可以使用post-processing mode.其主要的方法是通过仿真运行dump数据在vcd或者vpd文件中,运行结束后通过vcd或者vpd观察运行过程的情况,交互调试能力相对较差,但是通过记录的数据可以观察出其中异常的地方;也就是包括两个步骤Write VCD+ file,View result.>vcs source.v –line –R -PP +vcsd其中-R自动运行并且生成vcd+文件-PP编译的时候是faster VirSim post_processing>vcs –RPP source.v +vpdfile+vcdplus.vpd注意:VirSim只能处理VCD+ file.VCD文件可以被转换成VCD+格式的文件.VCD+和VCD有什么不一样那?更快,更小.VCD+系统任务可以在testbench中使用也可以在仿真的时候添加.(注意使用到这些系统函数时,在vcs编译的时候一定要添加-I或者-RI.)$vcdpluson(level_number,module_instance,….|net_or reg,….)level_numbers指定记录的层次0- 记录整个指定module_instance的所有信号1- 记录指定module_instance顶层信号n- 记录从顶层开始到下面的n层例化模块的信号module_instance 指定例化名net_ or reg 指定特定的wire或者reg作为记录的对象,默认是所有信号.$vcdplusoff(module_instance,….|net_ or reg,…)其他系统函数可以参见VCS quick reference.二. 其他情况注意区别的两个方面:1. –R –I 不同于-RI-R –I是编译成VirSim的可执行文件而且马上运行仿真, -RI是编译成VirSim的可执行文件并且调用VirSim.2. –R –PP 不同于-RPP-R –PP是编译成VirSim的可执行文件并且在运行的时候加快输出VCD+文件-RPP是在存在VCD+的条件下调用VirSim进行post processing的调试.门级仿真需要反标SDF文件,可以在testbench中添加$sdf_annotate系统函数.并且在编译的时候注意要使用standcell的仿真库.Compile-Time Options********************-f <filename>Specifies a file that contains a list of pathnames to source filesand compile-time options.-F <filename>Same as the -f option but allows you to specify a path to the fileand the source files listed in the file do not have to be absolutepathnames.-hDisplays a succinct description of the most commonly used compile-timeand runtime options.-l <filename>(lower case L) Specifies a log file where VCS records compilationmessages and runtime messages if you include the -R, -RI, or-RIG options.-lineEnables stepping through the code and source line breakpoints in VirSim.-MEnables incremental compilation, but do not overwrite the makefile.-MupdateEnable incremental compilation and overwrite the make file.-noticeEnables verbose diagnostic messages.-o <name>Specifies the name of the executable file that is the product ofcompilation. The default name is simv (simv.exe on Windows).-ova_covEnables functional coverage.-P <pli.tab>Specifies a PLI table file.-RRun the executable file immediately after VCS links together the executable file. You can add any runtime option to the vcs command line.-sStop simulation just as it begins. Use this option with the -R and+cli options.-timescale=<time_unit>/<time_precision>If only some source files contain the `timescale compiler directive and the ones that don't appear first on the vcs command line, use this option to specify the time scale for these source files.-VEnables the verbose mode.-v <filename>Specifies a Verilog library file to search for module definitions.-veraSpecifies the standard VERA PLI table file and object library.-y <directory_pathname>Specifies a Verilog library directory to search for module definitions.+2stateEnables 2 state simulation.+cli+[<module_name>=]1|2|3|4Enable CLI debugging.1 enables you to see the values of nets and registers and deposit values to registers.2 also enables breakpoints on value changes of nets and registers.3 also enables you to force a value on nets.4 also enables you to force a value on a register.You can specify a module to enable CLI debugging only for instances of the module.+define+<macro_name>=<value>Defines a text macro. Test for this definition in your Verilogsource code using the `ifdef compiler directive.+incdir+<directory>Specifies the directories that contain the files you specified withthe `include compiler directive. You can specify more that one directory, separating each path name with the + character.+libext+<extension>Specifies that VCS only search the source files in a Verilog library directory with the specified extension. You can specify more than one extension, separating each extension with the + character.For example, +libext++.v specifies searches library files with no extension and library files with the .v extension.Enter this option when you enter the -y option.+maxdelaysUse maximum value when min:typ:max values are encountered in delay specifications SDF files.+mindelaysUse minimum value when min:typ:max values are encountered in delay specifications and SDF files.+notimingcheckSuppresses timing checks in specify blocks.+plusarg_ignoreAlso enter this option in the file that you specify with the -f optionso that VCS does not pass to the simv executable or to VirSim the options that follow in the file. Use this option with the+plusarg_save option to specify that other options shouldnot be passed.+raceSpecifies that VCS generate a report, during simulation, of all therace conditions in the design and write this report in the race.outfile.+race=allAnalyzes the source code during compilation to look for codingstyles that cause race conditions.+rad or +rad+2Performs aggressive optimizations on your design.+rad+1 or +radlite or +radlightPerforms less aggressive optimizations on your design.+v2kEnables the use of new Verilog constricts in the 1364-2001 standard.Runtime Options***************-i <filename>Specifies a file containing CLI commands that VCS executes whensimulation starts.-l <filename>Specifies writing all messages from simulation to the specifiedfile as well as displaying these messages in the standard output.This option begins with the letter "l" (lowercase "L") for log file.-ova_covEnables functional coverage reporting.-sStops simulation just as it beings, and enters interactive mode.Use with the +cli+<number> option.-VVerbose mode. Print VCS version and extended summary information. Prints VCS compile and run-time version numbers, and copyright information, at start of simulation.-vcd <filename>Sets the output VCD file name to the specified file.The default filename is verilog.dump.A $dumpfile system task in the Verilog source code will overridethis option.+maxdelaysSpecies using the compiled SDF file for maximum delays generatedby the +allmtm compile-time option.Also specifies using maximum delays for SWIFT VMC or SmartModelsor Synopsys hardware models if you also enter the+override_model_delays runtime option.+mindelaysSpecifies using the compiled SDF file for minimum delays generatedby the +allmtm compile-time option.Also specifies using minimum delays for SWIFT VMC or SmartModelsor Synopsys hardware models if you also enter the+override_model_delays runtime option.+notimingcheckSuppress timing checks.+override_model_delaysEnables you to use the +mindelays, +typdelays, or +maxdelays runtime options to specify timing for SWIFT SmartModels or Synopsys hardware models.+sdfverboseEnables the display of more than ten warning and ten error messages about SDF back annotation.+vcs+dumpoff+<t>+<ht>Turn off value change dumping ($dumpvars system task) at time <t>.<ht> is the high 32 bits of a time value greater than 32 bits.+vcs+dumpon+<t>+<ht>Suppress $dumpvars system task until time <t>.<ht> is the high 32 bits of a time value greater than 32 bits.+vcs+dumpvarsoffSuppress $dumpvars system tasks.+vcs+finish+<t>+<ht>Finish simulation at time <t>.<ht> is the high 32 bits of a time value greater than 32 bits.Options for Using VirSim Interactively or in Post-Processing************************************************************+cfgfile+<filename>Specifies using a configuration file that you recorded in aprevious session with VirSim.+vslogfile[+<filename>]Enables logging of VirSim commands in a VirSim log file. If you do not specify a filename, the log is automatically saved to the workingdirectory as VirSim.log.Options For Using VirSim************************the following are options for using VirSim. You enter them on thevcs command line and also specify the source files.Options for Using VirSim interactively with VCS+++++++++++++++++++++++++++++++++++++++++++++++ -RIRun Interactive. Starts VirSim immediately after compilation.-RIGRun Interactive Debug. Start VirSim using an existing executablefile (such as the simv or simv.exe file). VCS does no compilation.+sim+<simv_name>Use with the -RIG option. You need this option to specify the nameof the simv executable file that isn't named simv but has a differentname that you specified with the -o compile-time option.+vslogfilesim[+<filename>]Enables the logging of VCS communication messages in the VirSim logfile. If you use both +vslogfile and +vslogfilesim, VirSim commandsand VCS messages are saved to the same file.If you do not specify a filename, the log is automatically savedto the working directory as VirSim.log.+vpdfile+<filename>At runtime, defines an alternative name of the VCD+ file that VCSwrites instead of the default name vcdplus.vpd.Options for Using VirSim in Post-Processing+++++++++++++++++++++++++++++++++++++++++++-RPPRun Post-Processing mode. Starts VirSim for post-processing a VCD+file.+vcdfile+<filename>Specifies the VCD file you want to use for post-processing.+vpdfile+<filename>[+start+<start_time>+end+<end_time>]In post-processing, specifies the VCD+ file you wish to view inVirSim. The optional +start+<start_time> and +end+<end_time>arguments specify you only want VirSim to display the resultsfrom between these simulation times.Options for Specifying How VCS Writes the VCD+ File+++++++++++++++++++++++++++++++++++++++++++++++++++ -PPEnables system tasks and options for VCD+ files and optimizationsfor faster post-processing.-IEnables system tasks and options for VCD+ files.+vpdbufsize+<MB>VCS uses an internal buffer to store value changes before it writesthem to the VCD+ file on disk. VCS makes this buffer size either 5MB or large enough to record 15 value changes for all nets andregisters in your design, which ever is larger.You can use this option to override the buffer size that VCScalculates for the buffer size. You specify a buffer size inmegabytes.+vpddriversTells VCS to record the values of all the drivers of all the nets.+vpdfilesize+<MB>Specifies the maximum size of the VCD+ file. When VCS reaches this limit, VCS overwrites the oldest simulation history data in the file with the newest.+vpdignoreTells VCS to ignore $vcdplus system tasks so VCS does not write a VCD+ file.+vpdportsTells VCS to record, in the VCD+ file, the port direction of signals that are ports.+vpdnocompressDisables the automatic compressing of the data in VCD+ files.+vpdupdateIf VCS is writing a VCD+ file during simulation, this option enables you to have VCS halt writing to the VCD+ file while the simulationis running and so that you can view the recorded results in VirSim. This option enables you to use the update feature in VirSim.+vpdnostrengthsDisables recording strength information in the VCD+ file.Options For CAlling The vcd2vpd and vpd2vcd Utilities*****************************************************-vcd2vpd <vcd_filename> <vcdplus_filename>Tells VCS to find and run the vcd2vpd utility that converts a VCDfile to a VCD+ file. VCS inputs to the utility the specified VCDfile and the utility outputs the specified VCD+ file.-vpd2vcd <vcdplus_filename> <vcd_filename>Tells VCS to find and run the vpd2vcd utility that converts a VCD+ file to a VCD file. VCS inputs to the utility the specified VCD+file and the utility outputs the specified VCD file.The Virsim debugger and the vpd2vcd and vcd2vpd translator utilities are best invoked via the vcs command line.Summary of vcs options for the $vcdpluson tasks:-------------------------------------------------I enable interactive/postprocessing debugging capabilities-PP enable optimizer postprocessing capabilities for vcd++vcsd enable the VCS DKI (Direct Kernel Interface); +vpdports,+vpddrivers, output and interactivesimulation currently are not available in +vcsd mode.Summary of vcs options for the Virsim GUI:-------------------------------------------RI after compilation, run simulation under Virsim (implies -I)-RIG run simulation under Virsim without compiling (executable has to exist)-RPP run Virsim in postprocessing mode (requires file created by $vcdpluson)Additional Virsim Verilog and $vcdpluson flags:-----------------------------------------------VirSim 4.3.R11 Virtual Simulator EnvironmentCopyright (C) 1993-2003 by Synopsys, Inc.Licensed Software. All Rights Reserved.Usage: vcs [-RI|-RIG|-RPP] [[+vpdfile+<vpdname>]...] [[+vcdfile+<vcdname>]...] [[+cfgfile+<cfgname>]...][sim-opts] [vpd-opts-to-pli] [other-opts] files+vpdfile+<vpdname> Multiple VPD files can be opened using several+vpdfile+ commands+vcdfile+<vcdname> Multiple VCD files can be opened using several+vcdfile+ commands+cfgfile+<cfgname> Multiple (incremental) configuration files can be loadedsim-opts:+sim+<simulator-path> Sets simulator path name+simtype+<simulator> Sets simulator type exactly as listed in SimulatorInvocation Dialog+simargs+<parameters> Sets additional simulator arguments. Double quotes around multiple arguments.+simargs+"+vpdfile+<vpdname>" Sets name of VPD file to be created by VCD+ PLI vpd-opts-to-pli: Options for VCD+ generation by an interactivesimulation run started by virsim+vpdports Stores port type information for hierarchy+vpddrivers Stores data for changes on drivers of resolved nets+vpdbufsize+<#MB> Changes the default size of the internal VCD+ buffer+vpdfilesize+<#MB> Sets file size when storing data in wraparound mode+vpdupdate Enables VPD file locking+vpdignore Tells simulator to ignore all calls to generate VPD+vslogfile Enables message logging. Does not log simulation communication messages +vslogfile+<filename> Enables message logging. Logs messages in filename+vslogfilesim Enables logging of simulation communication messagesother-opts: Sets regular options to compile verilog code+v2k Enables supported verilog 2000 additionsfiles: Verilog source code file(s) listSummary of vcd2vpd options:---------------------------Usage: vcs -vcd2vpd <options> <evcd_options> <vcd_file> <vpd_file><options>-b# Buffer size in KB used to store Value Change Data beforewriting it to disk.-f# Maximum output file size in KB. Wrap around occurs ifthe specified file size is reached.-h Translate hierarchy information only.-m Give tranlsation metrics during translation.-q Suppress printing of copyright and other informational messages.+deltacycle Add delta cycle information to each signal value change.+glitchon Add glitch event detection data.+nocompress Turn data compression off.+nocurrentvalue Do not include object's current value at the beginning of each VCB. <evcd_options>+dut+<dut_prefix> Modifies the string identifier for the Device-Under-Testhalf of the split signal. Default is "DUT".+tf+<tf_prefix> Modifies the string identifier for the Test-Fixturehalf of the split signal. Default is "TF".+indexlast Appends the bit index of a vector bit as the lastelement of the name.Summary of vpd2vcd options:---------------------------Usage: vcs -vpd2vcd <vpd_file> [<vcd_file>]Summary of vpd2vcd command line options-h Translate hierarchy information only.-q Suppress printing of copyright and other informational messages.-s Allow sign extension for vectors. Reduces size of <vcd_file>.-x Expand vector variables to full length when displaying$dumpoff value blocks.+zerodelayglitchfilter Zero delay glitch filtering for multiple value changes within the same time unit.+morevhdl Translates the vhdl types that are not directly mappable to verilog types in addition to the ones that are mappable.+start+<value> Translate value changes starting after start time <value> +end+<value> Translate value changes ending before end time <value> (Note) If both start and end values are input, value changesoccuring between start and end time are translated.。

VCS使⽤SDF⽂件进⾏后仿反标概述从概念上来说，数字验证包含两⽅⾯的内容，⼀个是验证功能，另⼀个是验证时序。

对应的仿真模型（不论是model，standard cell等）也不外乎这两个部分，功能部分由逻辑，udp元件或gate构成，时序部分则包括了时序反标和时序检查两⼩块。

平时我们所说的功能验证，也就是前仿真，实现了对功能进⾏验证的⽬的，时序被默认为理想情况，不包含延迟信息。

门级仿真，也称为后仿真，除了功能验证外，最主要就是⽤来检查时序是否满⾜，有没有时序违例的情形。

门级仿真根据⽹表不同，⼜可以分为综合后仿真，以及pnr后仿真。

前者是⽤综合后的⽹表进⾏仿真，这时由于hold没有修，所以会出现不少时序违例的情况，真正timing clean的⽹表是后端做完布局布线，修修补补完timing的⽹表，我们称为pnr⽹表。

进⾏pnr⽹表的后仿真时，我们需要告知仿真⼯具cell与cell之间的延迟，D端到Q端的延迟，这⾥，我们就要请出主⾓SDF⽂件，闪亮登场！什么是SDF⽂件？SDF(Standard delay file)⽂件是把布局布线过程中器件延时和线延时的信息保留下来，据此就可以在路径时序分析时将整条路径的时序计算出来，再判断时序约束条件就能知道是否满⾜时序要求了。

如何反标SDF⽂件？反标SDF⽂件有两种⽅法，⼀种作为elaboration的选项指定，另⼀种是在bench中调⽤系统函数$sdf_annotate来完成。

作为elaboration的选项-sdfmin|typ|max:instance_name:file.sdf如vcs-sdf min:top.i_test.:test.sdf使⽤系统函数$sdf_annotate$sdf_annotate (“sdf_file”[, module_instance] [,“sdf_configfile”][,“sdf_logfile”][,“mtm_spec”] [,“scale_factors”][,“scale_type”]);这⾥除了sdf_file必须给出外，其他参数可以使⽤默认值，如：$sdf_annotate(“test.sdf”);要说明下参数scale_type，sdf⽂件中时序信息都会由3个数字组成，分别对应是minimum，typical，maximum三种情形下的延迟（当然，有时候会只有minimum和maximum的情况，那么typical的延迟没有就省略）scale_type的可取值为：FROM_MINIMUX选择SDF⽂件中mininum timingFROM_TYPICAL选择SDF⽂件中typical timingFROM_MAXIMUM选择SDF⽂件中maximum timingFROM_MTM系统默认如何确认成功反标呢？反标完成后，可以从log中看到这样⼀句话：例⼦这样我们就反标完成了，接下来让我们通过后仿波形，验证下设计中延迟和sdf⽂件中延迟是否⼀致。