GS88237BD-200I中文资料

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GS88237BB/D-333/300/250/200256K x 369Mb SCD/DCD Sync Burst SRAM333 MHz–200 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O119- & 165-Bump BGA Commercial Temp Industrial Temp Features• Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-bump and 165-bump BGA packages • Pb-Free 119-bump and 165-bump BGA packages availableFunctional DescriptionApplicationsThe GS88237BB/D is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may beconfigured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.SCD and DCD Pipelined ReadsThe GS88237BB/D is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS88237BB/D operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.Parameter Synopsis-333-300-250-200Unit Pipeline 3-1-1-1t KQ tCycle 2.03.0 2.23.3 2.34.0 2.75.0ns ns (x36)(x36)GS88237BB/D-333/300/250/200 GS88237B Pad Out—119-Bump BGA—Top View (Package B)1234567A V DDQ A6A7ADSP A8A9V DDQB NC NC A4ADSC A15A17NCC NC A5A3V DD A14A16NCD DQ C4DQ C9V SS ZQ V SS DQ B9DQ B4E DQ C3DQ C8V SS E1V SS DQ B8DQ B3F V DDQ DQ C7V SSG V SS DQ B7V DDQG DQ C2D Q C6B C ADV B B DQ B6DQ B2H DQ C1DQ C5V SS GW V SS DQ B5DQ B1J V DDQ V DD NC V DD NC V DD V DDQK DQ D1DQ D5V SS CK V SS DQ A5DQ A1L DQ D2DQ D6B D SCD B A DQ A6DQ A2M V DDQ DQ D7V SS BW V SS DQ A7V DDQN DQ D3DQ D8V SS A1V SS DQ A8DQ A3P DQ D4DQ D9V SS A0V SS DQ A9DQ A4R NC A2LBO V DD V DDQ/A13PEDNUT NC NC A10A11A12 NC ZZU V DDQ TMS TDI TCK TDO NC V DDQGS88237BB/D-333/300/250/200 165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3BW ADSC ADV A NC AB NC A E2BD BA CK GW G ADSP A NC BC DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GMCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HH V DDQ/NCJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQD SCD V DDQ V SS NC NC NC V SS V DDQ NC DQA NP NC NC A A TDI A1TDO A A A A17PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump PitchGS88237BB/D-333/300/250/200GS882V37 BGA Pin DescriptionSymbol Type DescriptionA0, A1I Address field LSBs and Address Counter Preset InputsA I Address InputsDQ ADQ BDQ CDQ DI/O Data Input and Output pinsB A, B B, B C, B D I Byte Write Enable for DQ A, DQ B, DQ C, DQ D I/Os; active lowNC—No ConnectNC—No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active lowGW I Global Write Enable—Writes all bytes; active lowE1I Chip Enable; active lowE3I Chip Enable; active lowE2I Chip Enable; active highG I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active highLBO I Linear Burst Order mode; active lowPE I9th Bit Enable; active low (only on 119-bump BGA)ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode SelectTDI I Scan Test Data InTDO O Scan Test Data OutTCK I Scan Test ClockMCL—Must Connect Low SCD—Single Cycle Deselect/Dual Cyle Deselect Mode Control V DD I Core power supplyV SS I I/O and Core GroundV DDQ I Output driver power supplyGS88237BB/D-333/300/250/200GS88237B Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.B AB BB CB DGS88237BB/D-333/300/250/200Note:There are pull-up devices onthe ZQ, SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQ L High Drive (Low Impedance)H or NC Low Drive (High Impedance)9th Bit EnablePEL Activate DQPx I/Os (x18/x36 mode)H or NCDeactivate DQPx I/Os (x16/x32 mode)Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS88237BB/D-333/300/250/2001.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X XGS88237BB/D-333/300/250/200Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS88237BB/D-333/300/250/200Simplified State Diagram with GFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS88237BB/D-333/300/250/200Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6V V CK Voltage on Clock Input Pin –0.5 to 6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCPower Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.52.7VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88237BB/D-333/300/250/200V DDQ3 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH 2.0—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.8V1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.8V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameter Symbol Min.Typ.Max.Unit Notes V DD Input High Voltage V IH0.6*V DD—V DD + 0.3V1V DD Input Low Voltage V IL–0.3—0.3*V DD V1V DDQ I/O Input High Voltage V IHQ0.6*V DD—V DDQ + 0.3V1,3V DDQ I/O Input Low Voltage V ILQ–0.3—0.3*V DD V1,3 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameter Symbol Min.Typ.Max.Unit Notes Ambient Temperature (Commercial Range Versions)T A02570°C2 Ambient Temperature (Industrial Range Versions)T A–402585°C2 Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS88237BB/D-333/300/250/200Note:These parameters are sample tested.Capacitance(T A = 25o C, f = 1 MH Z , V DD = 2.5 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFAC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. 20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceGS88237BB/D-333/300/250/2001.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.2.All parameters listed are worst case scenario.DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH–1 uA –1 uA 1 uA 100 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VOperating CurrentsParameterTest ConditionsModeSymbol-333-300-250-200Unit0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40 to 85°C0to 70°C–40to 85°COperating Current 3.3 V Device Selected; All other inputs ≥V IH o r ≤ V IL Output open (x36)PipelineI DD I DDQ3805539055345503555029040300402403025030mAOperating Current 2.5 V Device Selected; All other inputs ≥V IH o r ≤ V IL Output open (x36)PipelineI DD I DDQ 3805539055345053555029040300402403025030mAStandby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB 4050405040504050mADeselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD8590808585907580mAGS88237BB/D-333/300/250/200Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameter Symbol -333-300-250-200Unit Min Max Min Max Min Max Min Max PipelineClock Cycle Time tKC 3.0— 3.3— 4.0— 5.0—ns Clock to Output Valid tKQ — 2.0— 2.2— 2.3— 2.7ns Clock to Output Invalid tKQX 1.0— 1.0— 1.0— 1.0—ns Clock to Output in Low-ZtLZ 1 1.0— 1.0— 1.0— 1.0—ns Setup time tS 1.0— 1.1— 1.2— 1.4—ns Hold time tH 0—0.1—0.2—0.4—ns G to Output Valid tOE — 2.0— 2.2— 2.3— 2.5ns G to output in High-Z tOHZ 1— 2.0— 2.2— 2.3— 2.5ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.5— 1.5— 1.5—1.5—ns Clock to Output inHigh-Z tHZ 1 1.0 2.0 1.0 2.2 1.5 2.3 1.5 3.0ns G to output in Low-Z tOLZ 10—0—0—0—ns ZZ setup time tZZS 25—5—5—5—ns ZZ hold time tZZH 21—1—1—1—ns ZZ recoverytZZR20—20—20—20—nsGS88237BB/D-333/300/250/200Pipeline Mode Timing (+1)Begin Read A Cont Cont Deselect Write BRead C Read C+1Read C+2Read C+3Cont DeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKLtKH Q(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88237BB/D-333/300/250/200Sleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.tZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZGS88237BB/D-333/300/250/200JTAG Port Registers OverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS88237BB/D-333/300/250/200JTAG TAP Block DiagramIdentification (ID) RegisterThe ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put inCapture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.Instruction RegisterID Code RegisterBoundary Scan Register120····313029120Bypass RegisterTDITDOTMS TCKTest Access Port (TAP) Controller108·1·········Control Signals·GS88237BB/D-333/300/250/200Tap Controller Instruction SetOverviewThere are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must beimplemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.ID Register ContentsDie Revision CodeNot UsedI/O ConfigurationGSI Technology JEDEC Vendor ID CodeP r e s e n c e R e g i s t e r Bit #313029282726252423222120191817161514131211109876543210x36XXXXX11100110110011GS88237BB/D-333/300/250/200JTAG Tap Controller State DiagramInstruction DescriptionsBYPASSWhen the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-tate testing of other devices in the scan path.SAMPLE/PRELOADSAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTESTEXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.Select DRCapture DRShift DRExit1 DRPause DRExit2 DRUpdate DRSelect IRCapture IRShift IRExit1 IRPause IRExit2 IRUpdate IRTest Logic ResetRun Test Idle 01111111111111111。

GS200用户指南说明书

GS200 USER GUIDEThis manual may differ from the phonedepending on the phone software versionand service provider used.P/N: MMBB0361705 (1.0)Menu tree1 Browser1 Home2 Yahoo!3 Bookmarks4 Enter address5 History6 Settings2 Call history1 All calls2 Missed calls3 Dialled calls4 Received calls5 Call duration6 Call costs7 Data information 3 T ools1 Alarm clock2 Calendar3 Calculator4 Memo5 To do6 Unit converter7 World clock8 S ervice ProviderName4 Multimedia1 MP3 player2 Camera3 Video camera4 FM radio5 Schedule FM record6 Voice recorder7 Melody composer8 Ringtone creator5 Messaging1 New message2 Inbox3 Drafts4 Outbox5 Sent6 Listen to voicemail7 Info message8 Templates9 Settings6 My stuff1 Images2 Sounds3 Videos4 Others5 External memory6 Games & Apps7 Profiles1 Normal2 Silent3 Outdoor4 Flight mode8 Contacts1 Search2 New contact3 Speed dials4 Groups5 Copy all6 Delete all7 Settings8 Information9 Settings1 Date & Time2 Languages3 Display4 Shortcut5 Call6 Security7 Connectivity8 Power save9 Reset0 Memory statusInstalling the SIM card and the handset batteryInstalling the SIM CardWhen you subscribe to a cellular network, you are provided with a plug-in SIM card loaded with your subscription details, such as your PIN, any optional services available and many others.Important! ›T he plug-in SIM card and its contacts can be easily damaged by scratches or bending, so be careful when handling, inserting or removing the card. Keep all SIM cards out of the reach of small children.›U SIM is not supported in this phone.IllustrationsAlways switch the device off and disconnect the charger before removing the battery.1 P ress the release button and remove the back cover.2 Lift battery away.3 Insert the SIM card.4 Insert the battery pack.5 Attach the back cover.6 Charge the battery. Note: Fully charge the battery before using it for the first time.1 2 34 5 6Phone ComponentsSoft keys(Left soft key / Right soft key)These keys perform the functionIndicated in the bottom of the display.End key- S witch on/off (hold down)- End or reject a call.Display screenSend key- Dial a phone number and answera call.- In standby mode: Shows a historyof calls.Navigation keysUse for quick access to phone functions.Number keyIn most of the time, the numeric keysare used to input number of characters.# key* keyEarpieceSide volume keyMicro USB Port / Earphone jack /Charger portSD card slotCamera keyTurning Your Phone On and Off1.Press and hold the End key until the power comes on.2. Press and hold the End key until the power goes off.Making a call1. Enter a phone number including the area code.2.Press the S key to call the number.3.To end the call, press the E key or the right soft key.Making an international call1. Press and hold the 0 key for the international prefix. The ‘+’character automatically selects the international access code.2.Enter the country code, area code, and the phone number.3.Press S [Send] key to call the number.Answering a call1. When you receive a call, the phone rings and the flashing phone icon appears on the screen.2.If the Any key has been set as the answer mode, any key press will answer a call except for the E key.3.To end the call, press the E key.Selecting functions and optionsYour phone offers a set of functions that allow you to customize the phone. These functions are arranged in menus andsub-menus, accessed via the two soft keys marked < and >. Each menu and sub-menu lets you view and alter thesettings of a particular function.The roles of the soft keys vary according to the current context; the label on the bottom line of the screen just aboveeach key indicates its current role.Entering TextYou can enter alphanumeric characters by using the phone’s keypad. Change the text input mode by pressing the# key. Also # key is used to change the profile to silent mode in idle screen.T9 ModeThe T9 predictive text input mode lets you enter words easily with a minimum number of key presses. As you presseach key, the phone begins to display the characters that it thinks you are typing based on the built-in dictionary.ABC ModeThis mode allows you to enter letters by pressing the key labeled with the required letter once, twice, three or fourtimes until the letter is displayed.123 Mode (Numbers Mode)Type numbers using one keystroke per number.Symbol ModeThe symbol mode enables you to enter various symbols or special characters. To enter a symbol, select Options➞Insert Symbol. Use the navigation keys to select the desired symbol and press the OK key.Anti Theft Mobile Tracker (ATMT)Anti-theft mobile tracker (ATMT) allows you to track your lost phone. When someone uses your phone without your permission, the tracking service will be activated.You are reminded by a text message sent to the default phone number you have set, without the unauthorized user’s knowledge. You can always activate the ATMT and configure your personal settings.To activate Anti-theft mobile tracker1.From the main menu, select Settings > Security > Anti theft mobile tracker and press OK.2.Select Set ATMT and press OK.3.Switch On or Off and press OK.4.Input the ATMT code to enable or disable this function.5.Edit Name, Primary and Secondary numbers and Save the settings.Note› The default ATMT code is “0000”. You have to enter the code before configuring the ATMT settings.Press the left soft key to access theavailable Menu.Press the right soft key to access theavailable Contacts.Menu ContactsQuick feature referenceThis section provides brief explanations of features on your phone.Browser Menu 1Home Connects to a homepage. The homepage will be the site which is defined in the activatedprofile. It will be defined by the service provider if you have not defined it in the activatedprofile.Yahoo! You can access to your Yahoo! Messenger, email accounts from any major providers, do a quicksearch, or view latest news on the Web. For more information, you can visit Yahoo!® Mobile formore information.Bookmarks This menu allows you to store the URL of favorite web pages for easy access at a later time.Enter address You can connect directly to the site you want. After entering a specific URL, press options thenOK key to make the connection Done to connect to the site.History This menu shows the History of recently browsed pages.Settings You can set the profile, cache and security related to internet service.Call history Menu 2All calls You can view all lists of outgoing or incoming calls.Missed calls You can view the unanswered calls.Dialled calls You can view the outgoing calls (called or attempted).Received calls You can view the Received calls.Call duration Allows you to view the duration of your incoming and outgoing calls. You can also reset the call timers.Call cost View the charges applied to your dialled numbers and the call duration of all your received and dialled calls. Also you can do Cost Settings.Data information You can check the amount of data transferred over the network through the GPRS information option. In addition, you can also view how much time you are online.Tools Menu 3Alarm clock You can set the alarm clock to go on at a specified time.Calendar When you enter this menu, a calendar appears. A square cursor is located on the current date.Tools Menu 3 (Continued)Calculator The calculator provides the basic arithmetic functions: addition, subtraction, multiplication anddivision.Memo You can add new memo, view and manage saved memos.To Do You can view, edit and add tasks to do.Unit converter This converts any measurement into a unit you want. There are 2 types that can be converted intounits: Length, WeightWorld clock The World Clock function provides time information on major cities worldwide. Also you can setany city as your Home city and Make Daylight savings ON/OFF.Multimedia Menu 4MP3 player Using the MP3 player in your phone, you can easily enjoy various music.Camera You can take photos with the built in camera and adjust its settings to suit your needs.Video camera You can record a video clip through the built-in camera.Multimedia Menu 4 (Continued)FM radio With embedded FM antenna, you can receive FM radio without an external earphone. You canlisten to your favourite radio station anytime.Note: In weak FM radio signal area the sensitivity can degrade with wireless and antenna mode.So it is advisable to insert the ear-mic for better and enhanced FM quality.Schedule FM record This function allows you to pre-schedule FM radio recordings.Voice recorder You can record voice memo.Melody composer This function allows you to compose a ring tone or melody.Ringtone creator This function allows you to create your own personal ringtones by using this tool.Messaging Menu 5New message This menu includes functions related to SMS (Short Message Service) and MMS (MultimediaMessage Service).Note: You can send SMS to many users at a time. Simply press Option and select Send to Many.This will open contact list where in user can mark/unmark contacts for sending SMS message.Note: To send the SMS to a particular group of contacts, simply press Options and select Send toGroup after composing the SMS.0168。

G781中文资料

±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。

GS88237BGD-200IV资料

GS88237BB/D-xxxV256K x 369Mb SCD/DCD Sync Burst SRAM250 MHz –200 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O119- & 165-Bump BGA Commercial Temp Industrial Temp Features• Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-bump and 165-bump BGA packages • RoHS-compliant 119-bump and 165-bump BGA packages availableFunctional DescriptionApplicationsThe GS88237BB/D-xxxV is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.SCD and DCD Pipelined ReadsThe GS88237BB/D-xxxV is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS88237BB/D-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible.Parameter Synopsis-250-200Unit Pipeline 3-1-1-1t KQ tCycle 2.54.0 2.55.0ns ns Curr (x36)330270mAGS88237BB/D-xxxV1234567A V DDQ A A ADSP A A V DDQB NC NC A ADSC A A NC C NC A A V DD A A NC D DQ C DQP C V SS ZQ V SS DQP B DQ BE DQ C DQ C V SS E 1V SS DQ B DQ BF V DDQ DQ C V SSG V SS DQ B V DDQ G DQ C D Q C B C ADV B B DQ B DQ BH DQ C DQ C V SS GW V SS DQ B DQ B J V DDQ V DD NC V DD NC V DD V DDQ K DQ D DQ D V SS CK V SS DQ A DQ A L DQ D DQ D B D SCD B A DQ A DQ A M V DDQ DQ D V SS BW V SS DQ A V DDQ N DQ D3DQ D V SS A 1V SS DQ A DQ A P DQ D DQP D V SS A 0V SS DQP A DQ A R NC A LBO V DD V DDQ /DNU A PE T NC NC A A A NC ZZ UV DDQTMSTDITCKTDONCV DDQGS88237B-xxxV Pad Out—119-Bump BGA—Top View (Package B)GS88237BB/D-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H V DDQ /NC MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQD SCD V DDQ V SS NC NC NC V SS V DDQ NC DQA N P NC NC A A TDI A1TDO A A A A17P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS88237BB/D-xxxVGS88237BB/D-xxxV BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No Connect NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low PE I 9th Bit Enable; active low (119-bump BGA only)ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS88237BB/D-xxxVA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.B AB BB CB DNC GS88237BB/D-xxxV Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS88237BB/D-xxxVNote:There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS88237BB/D-xxxVByte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3Write byte d H L H H H L 2, 3Write all bytesHLLLLL2, 3Write all bytes L X X X X X1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS88237BB/D-xxxVFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS88237BB/D-xxxVSimplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS88237BB/D-xxxVSimplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS88237BB/D-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.V DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High VoltageV IH0.6*V DD—V DD + 0.3V1GS88237BB/D-xxxVRecommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.(T A = 25= 2.5 V)V DDQ2 & V DDQ1 Range Logic LevelsAC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS88237BB/D-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VOperating CurrentsParameterTest Conditions ModeSymbol-250-200Unit0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current Device Selected; All other inputs ≥V IH o r ≤ V IL Output open (x36)PipelineI DD I DDQ 29040300402403025030mAStandby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB40504050mADeselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD85907580mAGS88237BB/D-xxxV1.I DD and I DDQ apply to any combination of V DD3 and V DDQ operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameter Symbol -250-200Unit Min Max Min Max PipelineClock Cycle Time tKC 4.0— 5.0—ns Clock to Output Valid tKQ — 2.5— 2.5ns Clock to Output Invalid tKQX 1.0— 1.0—ns Clock to Output in Low-ZtLZ 1 1.0— 1.0—ns Setup time tS 1.2— 1.4—ns Hold time tH 0.2—0.4—ns G to Output Valid tOE — 2.3— 2.5ns G to output in High-Z tOHZ 1— 2.3— 2.5ns Clock HIGH Time tKH 1.3— 1.3—ns Clock LOW Time tKL 1.7— 1.7—ns Clock to Output inHigh-Z tHZ 1 1.0 2.3 1.0 2.5ns G to output in Low-Z tOLZ 10—0—ns ZZ setup time tZZS 25—5—ns ZZ hold time tZZH 21—1—ns ZZ recoverytZZR20—20—nsGS88237BB/D-xxxVNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS88237BB/D-xxxVPipeline Mode Timing (+1)Begin Read A Cont Cont Deselect Write BRead C Read C+1Read C+2Read C+3Cont DeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKLtKH Q(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS88237BB/D-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZApplication TipsSingle and Dual Cycle DeselectSCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.JTAG Pin DescriptionsPinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS88237BB/D-xxxVJTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.Instruction RegisterID Code RegisterBoundary Scan Register120····313029120Bypass RegisterTDITDOTMS TCKTest Access Port (TAP) Controller108·1·········Control Signals·GS88237BB/D-xxxVJTAG TAP Block DiagramIdentification (ID) RegisterThe ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put inCapture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.ID Register ContentsNot UsedGSI Technology JEDEC Vendor ID CodeP r e s e n c e R e g i s t e r Bit #313029282726252423222120191817161514131211109876543210XXXXXXXXXXXXXXXXXXXX00110110011GS88237BB/D-xxxVTap Controller Instruction SetOverviewThere are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must beimplemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.Select DRCapture DRShift DRExit1 DRPause DRExit2 DRUpdate DRSelect IRCapture IRShift IRExit1 IRPause IRExit2 IRUpdate IRTest Logic ResetRun Test Idle 01111111111111111JTAG Tap Controller State DiagramInstruction DescriptionsBYPASSWhen the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-tate testing of other devices in the scan path.GS88237BB/D-xxxVSAMPLE/PRELOADSAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.EXTESTEXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state.Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-ated.IDCODEThe IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.SAMPLE-ZIf the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.RFUThese instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.。

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FEATURES Single Supply Operation Output Swings Rail to Rail Input Voltage Range Extends Below Ground Single Supply Capability from +3 V to +36 V High Load Drive Capacitive Load Drive of 500 pF, G = +1 Output Current of 15 mA, 0.5 V from Supplies Excellent AC Performance on 2.6 mA/Amplifier –3 dB Bandwidth of 16 MHz, G = +1 350 ns Settling Time to 0.01% (2 V Step) Slew Rate of 22 V/␮s Good DC Performance 800 ␮V Max Input Offset Voltage 2 ␮ V/؇ C Offset Voltage Drift 25 pA Max Input Bias Current Low Distortion –108 dBc Worst Harmonic @ 20 kHz Low Noise 16 nV/√Hz @ 10 kHz No Phase Inversion with Inputs to the Supply Rails APPLICATIONS Battery Powered Precision Instrumentation Photodiode Preamps Active Filters 12- to 16-Bit Data Acquisition Systems Medical Instrumentation

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