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GS8662Q08GE-200I中文资料

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GS8662Q08/09/18/36E-300/250/200/16772Mb SigmaQuad-II Burst of 2 SRAM300 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time • Burst of 2 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaQuad ™ Family OverviewThe GSQ8662Q08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GSQ8662Q08/09/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.Clocking and Addressing SchemesThe GSQ8662Q08/09/18/36E SigmaQuad-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C andC clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Because Separate I/O SigmaQuad-II B2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a SigmaQuad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 2048K addressable index).Parameter Synopsis-300-250-200-167tKHKH 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (288Mb)SA W BW2K BW1R SA MCL/SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA SA SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D352.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1674M x 18 SigmaQuad-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA W BW1K NC R SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA SA SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1678M x 8 SigmaQuad-II SRAM—Top View1234567891011ACQ SA SA W NW1K NC R SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA SA SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/1678M x 9 SigmaQuad-II SRAM — Top View1234567891011ACQ SA SA W NC K NC R SA SA CQ B NC NC NC SA NC K BW SA NC NC Q4C NC NC NC V SS SA SA SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNote: MCL = Must Connect LowGS8662Q08/09/18/36E-300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW Synchronous Byte Write Input Active Low x9 only BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control PinInput Active Low x8 only K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching Input Input —Qn Synchronous Data Outputs Output Dn Synchronous Data Inputs Input D off Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V NominalV SSPower Supply: GroundSupply—GS8662Q08/09/18/36E-300/250/200/167Note:NC = Not Connected to die or any other pinGS8662Q08/09/18/36E-300/250/200/167BackgroundSeparate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half.Alternating Read-Write OperationsSigmaQuad-II SRAMs follow a few simple rules of operation.- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.- Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM.- All address, data, and control inputs are sampled on clock edges.In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.SigmaQuad-II B2 SRAM DDR ReadThe read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.SigmaQuad-II B2 Double Data Rate SRAM Read FirstRead ANOPWrite BRead C Write DRead E Write FRead G Write HA B C D E F G HB B+1D D+1F F+1H H+1B B+1D D+1F F+1H H+1A A+1C C+1EKKAddress RWBWx D CCQ CQCQGS8662Q08/09/18/36E-300/250/200/167SigmaQuad-II B2 SRAM DDR WriteThe write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.SigmaQuad-II B2 Double Data Rate SRAM Write FirstWrite ARead BRead C Write DNOPRead E Write FRead G Write HNOPA B C D E F G HA A+1D D+1F F+1H H+1A A+1D D+1F F+1H H+1B B+1C C+1E E+1KKAddress RWBWx D CCQ CQCQGS8662Q08/09/18/36E-300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662Q08/09/18/36E-300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 3D0–D8Byte 4D9–D17Written Unchanged Unchanged WrittenBeat 1Beat 2Output Register ControlSigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K RW A 0–AnK W 0D 1–D nBank 0Bank 1Bank 2Bank 3R 0D A K W D A K W D A K W D R R R QQQQCCCCQ 1–Q nC W 1R 1W 2R 2W 3R 3Note:For simplicity BWn, NWn, K, and C are not shown.CQ CQ CQ CQ CQ 0CQ 1CQ 2CQ 3GS8662Q08/09/18/36E-300/250/200/167Example Four Bank Depth Expansion SchematicΣ2x 2B 2 S i g m a Q u a d -I IS R A MD e p t hE x p a n s i o nR e a d A W r i t e BR e a d C W r i t e D R e a d E W r i t e F R e a d G W r i t e H R e a d I W r i t e J R e a d K W r i t e L N O PAB C D E F G H I J K LF F +1H H +1J J +1F F +1H H +1J J +1BB +1D D +1L L +1BB +1D D +1L L +1A A +1G G +1I I +1C C +1E E +1KKA d d r e s s R (B a n k 1)R (B a n k 2)W (B a n k 1)W (B a n k 2)B W x (B a n k 1)D (B a n k 1)B W x (B a n k 2)D (B a n k 2)C (B a n k 1)C (B a n k 1)Q (B a n k 1)C Q (B a n k 1)C Q (B a n k 1)C (B a n k 2)C (B a n k 2)Q (B a n k 2)C Q (B a n k 2)C Q (B a n k 2)GS8662Q08/09/18/36E-300/250/200/167GS8662Q08/09/18/36E-300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.SigmaQuad-II B2 Coherency and Pass Through FunctionsBecause the SigmaQuad-II B2 read and write commands are loaded at the same time, there may be some confusion over what constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a write. This is true of the SigmaQuad-II B2 except in one case, as is illustrated in the following diagram. If the user holds the same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the SigmaQuad-II B2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.SigmaQuad-II B2 Coherency and Pass Through FunctionsSeparate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Read Truth TableA R Output Next StateQ Q K ↑(t n )K ↑(t n )K ↑(t n )K ↑(t n+1)K ↑(t n+1½)X 1Deselect Hi-Z Hi-Z VReadQ0Q1Notes:1.X = Don’t Care, 1 = High, 0 = Low, V = Valid.2.R is evaluated on the rising edge of K.3.Q0 and Q1 are the first and second data output transfers in a read.Separate I/O SigmaQuad-II B2 SigmaQuad-II SRAM Write Truth TableA W BWn BWn Input Next State D D K ↑(t n + ½)K ↑(t n )K ↑(t n )K ↑(t n + ½)K ↑, K ↑(t n ), (t n + ½)K ↑(t n )K ↑(t n + ½)V 000Write Byte Dx0, Write Byte Dx1D0D1V 001Write Byte Dx0, Write Abort Byte Dx1D0X V 010Write Abort Byte Dx0, Write Byte Dx1X D1X 011Write Abort Byte Dx0, Write Abort Byte Dx1X X X1XXDeselectXXNotes:1.X = Don’t Care, H = High, L = Low, V = Valid.2.W is evaluated on the rising edge of K.3.D0 and D1 are the first and second data input transfers in a write.4.BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).GS8662Q08/09/18/36E-300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662Q08/09/18/36E-300/250/200/167GS8662Q08/09/18/36E-300/250/200/167State DiagramPower-UpRead NOPLoad New Read Address DDR Read Write NOPLoad New Write AddressDDR WriteWRITEREAD READ WRITEREAD WRITEAlways (Fixed)Always (Fixed)READWRITENotes:1.Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.2.“READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same istrue for “WRITE” and “WRITE”.3.Read and write state machine can be active simultaneously.4.State machine control timing sequence is controlled by K.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662Q08/09/18/36E-300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.4 1.5V DD V Reference VoltageV REF0.68—0.95VNotes:1.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signalinputs. The power down sequence must be the reverse. V DDQ must not exceed V DD .2.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. Thepart number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662Q08/09/18/36E-300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DD + 0.3 V 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing param-eters.3.V IL (Min)DC = –0.3 V, V IL (Min)AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max)DC = V DDQ + 0.3 V, V IH (Max)AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 200—mV 3,4AC Input Logic LowV IL (ac)—V REF – 200mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V 67pF Clock CapacitanceC CLKV IN = 0 V56pFNote:This parameter is sample tested.GS8662Q08/09/18/36E-300/250/200/167AC Test ConditionsParameterConditionsInput high level 1.25 V Input low level 0.25 V Max. input slew rate 2 V/ns Input reference level 0.75 V Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –2 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 1.8 V)GS8662Q08/09/18/36E-300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-300-250-200-167Notes0to 70°C –40 to 85°C0to 70°C –40 to 85°C0to 70°C –40 to 85°C0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 900 mA920 mA 800 mA820 mA 670 mA690 mA 590 mA610 mA2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min 840 mA 860 mA 740 mA 760 mA 620 mA 640 mA 550 mA 570 mA 2, 3Standby Current (NOP): DDR I SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 V330 mA 340 mA 300 mA 310 mA 280 mA 290 mA 260 mA 270 mA 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662Q08/09/18/36E-300/250/200/167AC Electrical CharacteristicsParameter Symbol-300-250-200-167Units Notes Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKHt CHCH3.34.2 4.0 6.35.07.886.08.4nstKC Variable t KCVar—0.2—0.2—0.2—0.2ns5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKLt CHCL1.32— 1.6—2.0— 2.4—nsK, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKHt CLCH1.32— 1.6—2.0— 2.4—nsK to K HighC to C Hight KHKH 1.49— 1.8— 2.2— 2.7—nsK, K Clock High to C, C Clock High t KHCH0 1.450 1.80 2.30 2.8nsDLL Lock Time t KCLock1024—1024—1024—1024—cycle6 K Static to DLL reset t KCReset30—30—30—30—ns Output TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQVt CHQV—0.45—0.45—0.45—0.5ns3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQXt CHQX–0.45—–0.45—–0.45—–0.5—ns3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQVt CHCQV—0.45—0.45—0.45—0.5nsK, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQXt CHCQX–0.45—–0.45—–0.45—–0.5—nsCQ, CQ High Output Valid t CQHQV—0.27—0.30—0.35—0.40ns7 CQ, CQ High Output Hold t CQHQX–0.27—–0.30—–0.35—–0.40—ns7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZt CHQZ—0.45—0.45—0.45—0.5ns3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z t KHQX1t CHQX1–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH0.3—0.35—0.4—0.5—nsControl Input Setup Time t IVKH0.3—0.35—0.4—0.5—ns2 Data Input Setup Time t DVKH0.3—0.35—0.4—0.5—nsGS8662Q08/09/18/36E-300/250/200/167Hold TimesAddress Input Hold Time t KHAX 0.3—0.35—0.4—0.5—ns Control Input Hold Time t KHIX 0.3—0.35—0.4—0.5—ns Data Input Hold Timet KHDX0.3—0.35—0.4—0.5—nsNotes:1.All Address inputs must meet the specified setup and hold times for all latching clock edges.2.Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).3.If C, C are tied high, K, K become the references for C, C timing parameters4.To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and temperatures.5.Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.6.V DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V DD and input clock are stable.7.Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard bands and test setup variations.AC Electrical Characteristics (Continued)ParameterSymbol-300-250-200-167Units NotesMinMaxMinMaxMinMaxMinMax。

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清华紫光 文诚系列电脑 说明书

清华紫光 文诚系列电脑 说明书

文诚系列技术培训手册清华紫光台式电脑事业部技术支持部2004-06-01目录一、产品特点1.1优良的品质保证1.2出色的结构设计1.3可靠的安全维护二、文诚系列主机配置2.1文诚系列主机配置表三、主板技术规格3.1 精英P6VEMD2主板说明3.2 精英L4S5MG/GX+主板说明3.3 技嘉GA-8I845GV-CH2说明四、驱动程序安装4.1驱动光盘说明4.2驱动程序安装目录一、产品特点文诚系列电脑强调性能价格比，适用于教育、网吧等中低端用户，便于集中管理，统一维护。

1.1优良的品质保证1）通过国家3C认证；2）严格的部件优选体制，所有部件采用业界一线厂商的产品；3）周密的测试全集，保证部件的兼容性，同时保证系统的稳定性；4）五年保修。

1.2出色的结构设计1）立卧两用，根据不同空间随意放置；2）机箱面板模块化设计，根据不同的应用选取不同外观；3）良好的散热设计，确保立卧使用时系统内部热量有效、及时的散发；4）静音设计，减少部件共振，优化风道，降低噪音。

1.3可靠的安全维护1）集成硬盘保护功能，保证硬盘数据的安全，遭到破坏一键恢复；2）同一机型间网络传输功能，维护好一台机器即可通过网络对其他机器进行维护；3）自动维护，无人值班的情况下对整个网络环境中的机器机型维护；4）预留机箱锁孔，防止非法开启机箱。

二、文诚系列主机配置（一）文诚500 文诚800 文诚1000E 文诚1100文诚1200 CPU C3800Celeron 1.8GCeleron 1.8G Celeron 1.8G Celeron 1.8G主板 P6VEMD2L4S5MG/GX+ L4S5MG/GX+ L4S5MG/GX+GA-8I845GV-CH2内存Twinmos 128MDDR333Twinmos 128MDDR333Twinmos 128MDDR333Twinmos 128MDDR333Twinmos 128MDDR333硬盘SeagateST340015ASamsungSV0411N(40GB/5400PRM)SeagateST340015ASamsungSV0411N(40GB/5400PRM)SeagateST340015ASamsungSV0411N(40GB/5400PRM)光驱LG CR-8523B LG GCR-8523B软驱SamsungSFD-321BSamsungSFD-321BSamsungSFD-321B显示卡主板集成主板集成主板集成主板集成主板集成声卡主板集成主板集成主板集成主板集成主板集成网卡主板集成主板集成主板集成主板集成主板集成电源长城 1801-HP 长城 1801-HP 长城 1801-HP 长城 1801-HP 长城 1801-HPCPU风扇主板集成Cool MasterDI4-7H53B/DI4-7H54A-R2Cool MasterDI4-7H53B/DI4-7H54A-R2Cool MasterDI4-7H53B/DI4-7H54A-R2/EC203MBCool MasterDI4-7H53B/DI4-7H54A-R2/EC203MB机箱保利得 EN7472 保利得 EN7472 保利得 EN7472 保利得 EN7472 保利得 EN7472键盘精模 JME7010 精模 JME7010 精模 JME7010 精模 JME7010 精模 JME7010鼠标致伸 M042K0 致伸 M042K0 致伸 M042K0 致伸 M042K0 致伸 M042K0驱动光盘智能驱动光盘V2.0智能驱动光盘V2.0智能驱动光盘V2.0/2.1智能驱动光盘V2.0文诚系列主机配置（二）三、主板技术规格3.1文诚500采用的主板是：精英P6VEMD2，采用VIA CLE266 CE / VT8235 CD 芯片组。

DS08MB200中文资料

DS08MB200中文资料

DS08MB200Dual 800Mbps 1:2/2:1LVDS Mux/BufferGeneral DescriptionThe DS08MB200is a dual-port 1to 2repeater/buffer and 2to 1multiplexer.High-speed data paths and flow-through pinout minimize internal device jitter and simplify board lay-out.The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on National’s 10-,16-,and 18-bit Bus LVDS SerDes,or to CML or LVPECL signals.The 3.3V supply,CMOS process,and robust I/O ensure high performance at low power over the entire industrial -40to +85˚C temperature range.Featuresn Up to 800Mbps data rate per channeln LVDS/BLVDS/CML/LVPECL compatible inputs,LVDS compatible outputsn Low output skew and jittern On-chip 100Ωinput terminationn 15kV ESD protection on LVDS Inputs/Outputs n Hot plug Protection n Single 3.3V supplyn Industrial -40to +85˚C temperature range n 48-pin LLP PackageTypical Application20157420Block Diagram20157401FIGURE 1.DS08MB200Block DiagramJune 2006DS08MB200Dual 800Mbps 1:2/2:1LVDS Mux/Buffer©2006National Semiconductor Corporation Pin DescriptionsPin Name LLP Pin Number I/O,TypeDescriptionSWITCH SIDE DIFFERENTIAL INPUTSSIA_0+SIA_0−3029I,LVDS Switch A-side Channel 0inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.SIA_1+SIA_1−1920I,LVDS Switch A-side Channel 1inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.SIB_0+SIB_0−2827I,LVDS Switch B-side Channel 0inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.SIB_1+SIB_1−2122I,LVDSSwitch B-side Channel 1inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.LINE SIDE DIFFERENTIAL INPUTSLI_0+LI_0−4039I,LVDS Line-side Channel 0inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.LI_1+LI_1−910I,LVDSLine-side Channel 1inverting and non-inverting differential inputs.LVDS,Bus LVDS,CML,or LVPECL compatible.SWITCH SIDE DIFFERENTIAL OUTPUTSSOA_0+SOA_0−3433O,LVDS Switch A-side Channel 0inverting and non-inverting differential outputs.LVDS compatible(Notes 1,3).SOA_1+SOA_1−1516O,LVDS Switch A-side Channel 1inverting and non-inverting differential outputs.LVDS compatible(Notes 1,3).SOB_0+SOB_0−3231O,LVDS Switch B-side Channel 0inverting and non-inverting differential outputs.LVDS compatible(Notes 1,3).SOB_1+SOB_1−1718O,LVDS Switch B-side Channel 1inverting and non-inverting differential outputs.LVDS compatible(Notes 1,3).LINE SIDE DIFFERENTIAL OUTPUTSLO_0+LO_0−4241O,LVDS Line-side Channel 0inverting and non-inverting differential outputs.LVDS compatible (Notes1,3).LO_1+LO_1−78O,LVDS Line-side Channel 1inverting and non-inverting differential outputs.LVDS compatible (Notes1,3).DIGITAL CONTROL INTERFACEMUX_S0MUX_S13811I,LVTTL Mux Select Control Inputs (per channel)to select which Switch-side input,A or B,is passed through to the Line-side.ENA_0ENA_1ENB_0ENB_136133514I,LVTTLOutput Enable Control for Switch A-side and B-side outputs.Each output driver on the A-side and B-side has a separate enable pin.ENL_0ENL_1454I,LVTTLOutput Enable Control for The Line-side outputs.Each output driver on the Line-side has a separate enable pin.POWER V DD 6,12,37,43,48I,Power V DD =3.3V ±0.3V.GND2,3,46,47(Note 2)I,PowerGround reference for LVDS and CMOS circuitry.For the LLP package,the DAP is used as the primary GND connection to the device.The DAP is the exposed metal contact at the bottom of the LLP-48package.It should beconnected to the ground plane with at least 4vias for optimal AC and thermal performance.N/C1,5,23,24,25,26,44No ConnectNote 1:For interfacing LVDS outputs to CML or LVPECL compatible inputs,refer to the applications section of this datasheet.Note 2:Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.Note 3:The LVDS outputs do not support a multidrop (BLVDS)environment.The LVDS output characteristics of the DS08MB200device have been optimized for point-to-point backplane and cable applications.D S 08M B 200 2Connection Diagrams20157402 Top ViewDAP=GND20157403 Directional Signal Paths Top View (Refer to pin names for signal polarity)TRI-STATE and Powerdown Modes The DS08MB200has output enable control on each of the six onboard LVDS output drivers.This control allows each output individually to be placed in a low power TRI-STATE mode while the device remains active,and is useful to reduce power consumption on unused channels.In TRI-STATE mode,some outputs may remain active while some are in TRI-STATE.When all six of the output enables(all drivers on both chan-nels)are deasserted(LOW),then the device enters a Pow-erdown mode that consumes only0.5mA(typical)of supply current.In this mode,the entire device is essentially pow-ered off,including all receiver inputs,output drivers and internal bandgap reference generators.When returning to active mode from Powerdown mode,there is a delay until valid data is presented at the outputs because of the ramp to power up the internal bandgap reference generators.Any single output enable that remains active will hold the device in active mode even if the other five outputs are in TRI-STATE.When in Powerdown mode,any output enable that becomes active will wake up the device back into active mode,even if the other five outputs are in TRI-STATE.Input Failsafe BiasingExternal pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions.This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor.The pull up and pull down resistors should be in the 5kΩto15kΩrange to minimize loading and waveform dis-tortion to the driver.Please refer to application note AN-1194,“Failsafe Biasing of LVDS Interfaces”for more infor-mation.Output CharacteristicsThe output characteristics of the DS08MB200have beenoptimized for point-to-point backplane and cable applica-tions,and are not intended for multipoint or multidrop signal-ing.Multiplexer Truth Table(Note4)Data Inputs Control Inputs Output SIA_0SIB_0MUX_S0ENL_0LO_0X valid01SIB_0valid X11SIA_0X X X0(Note5)Z X=Don’t CareZ=High Impedance(TRI-STATE)Repeater/Buffer Truth Table(Note4)DataInput Control Inputs OutputsLI_0ENA_0ENB_0SOA_0SOB_0X00Z(Note5)Z(Note5)valid01Z LI_0valid10LI_0Zvalid11LI_0LI_0 X=Don’t CareZ=High Impedance(TRI-STATE)Note4:Same functionality for channel1Note5:When all enable inputs from both channels are Low,the deviceenters a powerdown mode.Refer to the applications section titled TRI-STATEand Powerdown modes.DS08MB2003Absolute Maximum Ratings (Note 6)Supply Voltage (V DD )−0.3V to +4.0V CMOS Input Voltage -0.3V to (V DD +0.3V)LVDS Receiver Input Voltage (Note 7)-0.3V to (V DD +0.3V)LVDS Driver Output Voltage -0.3V to (V DD +0.3V)LVDS Output Short Circuit Current +40mA Junction Temperature +150˚CStorage Temperature−65˚C to +150˚CLead Temperature (Solder,4sec)260˚C Max Pkg Power Capacity @25˚C 5.2W Thermal Resistance (θJA )24˚C/W Package Derating above +25˚C 41.7mW/˚CESD Last Passing Voltage HBM,1.5k Ω,100pF 8kV LVDS pins to GND only15kVEIAJ,0Ω,200pF 250V CDM1000VRecommended Operating ConditionsSupply Voltage (V CC ) 3.0V to 3.6V Input Voltage (V I )(Note 7)0V to V CC Output Voltage (V O )0V to V CCOperating Temperature (T A )Industrial−40˚C to +85˚C Note 6:Absolute maximum ratings are those values beyond which damage to the device may occur.The databook specifications should be met,without exception,to ensure that the system design is reliable over its power supply,temperature,and output/input loading variables.National does not recom-mend operation of products outside of recommended operation conditions.Note 7:V ID max <2.4VElectrical CharacteristicsOver recommended operating supply and temperature ranges unless other specified.SymbolParameterConditionsMinTyp (Note 8)MaxUnitsLVTTL DC SPECIFICATIONS (MUX_Sn,ENA_n,ENB_n,ENL_n)V IH High Level Input Voltage 2.0V DD V V IL Low Level Input Voltage GND 0.8V I IH High Level Input Current V IN =V DD =V DDMAX −10+10µA I IL Low Level Input Current V IN =V SS ,V DD =V DDMAX −10+10µA C IN1Input Capacitance Any Digital Input Pin to V SS 3.5pF C OUT1Output Capacitance Any Digital Output Pin to V SS 5.5pF V CL Input Clamp VoltageI CL =−18mA−1.5−0.8VLVDS INPUT DC SPECIFICATIONS (SIA ±,SIB ±,LI ±)V TH Differential Input High Threshold (Note 9)V CM =0.8V or 1.2V or 3.55V,V DD =3.6V0100mV V TL Differential Input Low Threshold (Note 9)V CM =0.8V or 1.2V or 3.55V,V DD =3.6V−1000mV V ID Differential Input Voltage V CM =0.8V to 3.55V,V DD =3.6V 1002400mV V CMR Common Mode Voltage Range V ID =150mV,V DD =3.6V 0.053.55V C IN2Input Capacitance IN+or IN−to V SS3.5pF I INInput CurrentV IN =3.6V,V DD =V DDMAX −15+15µA V IN =0V,V DD =V DDMAX−15+15µALVDS OUTPUT DC SPECIFICATIONS (SOA_n ±,SOB_n ±,LO_n ±)V OD Differential Output Voltage,(Note 9)R L is the internal 100Ωbetween OUT+and OUT−250360500mV ∆V OD Change in V OD between Complementary States -3535mV V OS Offset Voltage (Note 10) 1.05 1.22 1.475V ∆V OS Change in V OS between Complementary States -3535mV I OS Output Short Circuit Current OUT+or OUT−Short to GND −21-40mA C OUT2Output CapacitanceOUT+or OUT−to GND when TRI-STATE5.5pFD S 08M B 200 4Electrical Characteristics(Continued)Over recommended operating supply and temperature ranges unless other specified.Symbol Parameter Conditions MinTyp(Note8)Max UnitsSUPPLY CURRENT(Static)I CC Supply Current All inputs and outputs enabled andactive,terminated with differential loadof100Ωbetween OUT+and OUT-.225275mAI CCZ Supply Current-PowerdownMode ENA_0=ENB_0=ENL_0=ENA_1=ENB_1=ENL_1=L0.6 4.0mASWITCHING CHARACTERISTICS—LVDS OUTPUTSt LHT Differential Low to High Transition Time Use an alternating1and0pattern at200Mb/s,measure between20%and80%of V OD.(Note15)170250pst HLT Differential High to Low TransitionTime170250pst PLHD Differential Low to HighPropagation Delay Use an alternating1and0pattern at200Mb/s,measure at50%V ODbetween input to output.1.02.5nst PHLD Differential High to LowPropagation Delay1.02.5ns t SKD1Pulse Skew|t PLHD–t PHLD|(Note15)2575ps t SKCC Output Channel to Channel Skew Difference in propagation delay(t PLHDor t PHLD)among all output channels.(Note15)50115pst JIT Jitter(Note11)RJ-Alternating1and0at400MHz(Note12)1.3 1.5psrms DJ-K28.5Pattern,800Mbps(Note13)1534psp-p TJ-PRBS27-1Pattern,800Mbps(Note14)1634psp-pt ON LVDS Output Enable Time Time from ENA_n,ENB_n,or ENL_n toOUT±change from TRI-STATE toactive.0.5 1.5µst ON2LVDS Output Enable time frompowerdown mode Time from ENA_n,ENB_n,or ENL_n toOUT±change from Powerdown toactive1020µst OFF LVDS Output Disable Time Time from ENA_n,ENB_n,or ENL_n toOUT±change from active toTRI-STATE or powerdown.12nsNote8:Typical parameters are measured at V DD=3.3V,T A=25˚C.They are for reference purposes,and are not production-tested.Note9:Differential output voltage V OD is defined as ABS(OUT+–OUT−).Differential input voltage V ID is defined as ABS(IN+–IN−).Note10:Output offset voltage V OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.Note11:Jitter is not production tested,but guaranteed through characterization on a sample basis.Note12:Random Jitter,or RJ,is measured RMS with a histogram including1500histogram window hits.The input voltage=V ID=500mV,50%duty cycle at400 MHz,t r=t f=50ps(20%to80%).Note13:Deterministic Jitter,or D J,is measured to a histogram mean with a sample size of350hits.Stimulus and fixture jitter has been subtracted.The input voltage=V ID=500mV,K28.5pattern at800Mbps,t r=t f=50ps(20%to80%).The K28.5pattern is repeating bit streams of(00111110101100000101).Note14:Total Jitter,or T J,is measured peak to peak with a histogram including3500window hits.Stimulus and fixture jitter has been subtracted.The input voltage =V ID=500mV,27-1PRBS pattern at800Mbps,t r=t f=50ps(20%to80%).Note15:Not production tested.Guaranteed by statistical analysis on a sample basis at the time of characterization.DS08MB2005Typical Performance CharacteristicsPower Supply Current vs.Bit Data RateTotal Jitter vs.Temperature20157412Dynamic power supply current was measured with all channels active and toggling at the bit data rate.Data pattern has no effect on the power consumption.V DD =3.3V,T A =+25˚C,V ID =0.5V,V CM =1.2V.20157410Total Jitter measured at 0V differential while running a PRBS 27-1pattern with one channel active,all other channels are disabled.V DD =3.3V,V ID =0.5V,V CM =1.2V,800Mbps data rate.Stimulus and fixture jitter has been subtracted.Total Jitter vs.Bit Data Rate20157411Total Jitter measured at 0V differential while running a PRBS 27-1pattern with one channel active,all other channels are disabled.V DD =3.3V,T A =+25˚C,V ID =0.5V.Stimulus and fixture jitter has been subtracted.D S 08M B 200 6Interfacing LVPECL to LVDSAn LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source.This drives a pair of emitter-followers that require a50ohm to V CC-2.0 load.A modern LVPECL driver will typically include the ter-mination scheme within the device for the emitter follower.If the driver does not include the load,then an external scheme must be used.The 1.3V supply is usually not readily available on a PCB,therefore,a load scheme without a unique power supply requirement may be used.Figure2is a separatedπtermination scheme for a3.3V LVPECL driver.R1and R2provides proper DC load for the driver emitter followers,and may be included as part of the driver device(Note16).The DS08MB200includes a100 ohm input termination for the transmission line.The common mode voltage will be at the normal LVPECL levels–around 2V.This scheme works well with LVDS receivers that have rail-to-rail common mode voltage,V CM,range.Most National Semiconductor LVDS receivers have wide V CM range.The exceptions are noted in devices’respective datasheets. Those LVDS devices that do have a wide V CM range do not vary in performance significantly when receiving a signal with a common mode other than standard LVDS V CM of1.2 V.An AC coupled interface is preferred when transmitter and receiver ground references differ more than1V.This is a likely scenario when transmitter and receiver devices are on separate PCBs.Figure3illustrates an AC coupled interface between a LVPECL driver and LVDS receiver.R1and R2,if not present in the driver device(Note16),provide DC load for the emitter followers and may range between140-220 ohms for most LVPECL devices for this particular configura-tion.The DS08MB200includes an internal100ohm resistor to terminate the transmission line for minimal reflections.The signal after ac coupling capacitors will swing around a level set by internal biasing resistors(i.e.fail-safe)which is either V DD/2or0V depending on the actual failsafe implementa-tion.If internal biasing is not implemented,the signal com-mon mode voltage will slowly wander to GND level.Interfacing LVDS to LVPECLAn LVDS driver consists of a current source(nominal3.5mA) which drives a CMOS differential pair.It needs a differential resistive load in the range of70to130ohms to generate LVDS levels.In a system,the load should be selected to match transmission line characteristic differential impedance so that the line is properly terminated.The termination resis-tor should be placed as close to the receiver inputs as possible.When interfacing an LVDS driver with a non-LVDS receiver,one only needs to bias the LVDS signal so that it is within the common mode range of the receiver.This may be done by using separate biasing voltage which demands another power supply.Some receivers have required biasing voltage available on-chip(V T,V TT or V BB).Figure4illustrates interface between an LVDS driver and a LVPECL with a V T pin available.R1and R2,if not present in the receiver(Note16),provide proper resistive load for the driver and termination for the transmission line,and V T sets desired bias for the receiver.Figure5illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a V T pin available.The resistors R1,R2,R3,and R4,if not present in the receiver (Note16),provide a load for the driver,terminate the trans-mission line,and bias the signal for the receiver.Note16:The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device.The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility be-tween the driver and receiver terminations and common mode operating ranges.20157461 FIGURE2.DC Coupled LVPECL to LVDS Interface20157462 FIGURE3.AC Coupled LVPECL to LVDS Interface20157463 FIGURE4.DC Coupled LVDS to LVPECL Interface20157464 FIGURE5.AC Coupled LVDS to LVPECL InterfaceDS08MB2007Physical Dimensionsinches (millimeters)unless otherwise noted48-Pin LLPNS Package Number SQA48aOrdering Code DS08MB200TSQ (250piece Tape and Reel)DS08MB200TSQX (2500piece Tape and Reel)National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.For the most current product information visit us at .LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.BANNED SUBSTANCE COMPLIANCENational Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2)and Banned Substances and Materials of Interest Specification (CSP-9-111S2)for regulatory environmental compliance.Details may be found at:/quality/green.Lead free products are RoHS compliant.National Semiconductor Americas Customer Support CenterEmail:new.feedback@ Tel:1-800-272-9959National SemiconductorEurope Customer Support CenterFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National Semiconductor Asia Pacific Customer Support CenterEmail:ap.support@National SemiconductorJapan Customer Support Center Fax:81-3-5639-7507Email:jpn.feedback@ Tel:81-3-5639-7560D S 08M B 200D u a l 800M b p s 1:2/2:1L V D S M u x /B u f f e r。

GS200用户指南说明书

GS200用户指南说明书

GS200 USER GUIDEThis manual may differ from the phonedepending on the phone software versionand service provider used.P/N: MMBB0361705 (1.0)Menu tree1 Browser1 Home2 Yahoo!3 Bookmarks4 Enter address5 History6 Settings2 Call history1 All calls2 Missed calls3 Dialled calls4 Received calls5 Call duration6 Call costs7 Data information 3 T ools1 Alarm clock2 Calendar3 Calculator4 Memo5 To do6 Unit converter7 World clock8 S ervice ProviderName4 Multimedia1 MP3 player2 Camera3 Video camera4 FM radio5 Schedule FM record6 Voice recorder7 Melody composer8 Ringtone creator5 Messaging1 New message2 Inbox3 Drafts4 Outbox5 Sent6 Listen to voicemail7 Info message8 Templates9 Settings6 My stuff1 Images2 Sounds3 Videos4 Others5 External memory6 Games & Apps7 Profiles1 Normal2 Silent3 Outdoor4 Flight mode8 Contacts1 Search2 New contact3 Speed dials4 Groups5 Copy all6 Delete all7 Settings8 Information9 Settings1 Date & Time2 Languages3 Display4 Shortcut5 Call6 Security7 Connectivity8 Power save9 Reset0 Memory statusInstalling the SIM card and the handset batteryInstalling the SIM CardWhen you subscribe to a cellular network, you are provided with a plug-in SIM card loaded with your subscription details, such as your PIN, any optional services available and many others.Important! ›T he plug-in SIM card and its contacts can be easily damaged by scratches or bending, so be careful when handling, inserting or removing the card. Keep all SIM cards out of the reach of small children.›U SIM is not supported in this phone.IllustrationsAlways switch the device off and disconnect the charger before removing the battery.1 P ress the release button and remove the back cover.2 Lift battery away.3 Insert the SIM card.4 Insert the battery pack.5 Attach the back cover.6 Charge the battery. Note: Fully charge the battery before using it for the first time.1 2 34 5 6Phone ComponentsSoft keys(Left soft key / Right soft key)These keys perform the functionIndicated in the bottom of the display.End key- S witch on/off (hold down)- End or reject a call.Display screenSend key- Dial a phone number and answera call.- In standby mode: Shows a historyof calls.Navigation keysUse for quick access to phone functions.Number keyIn most of the time, the numeric keysare used to input number of characters.# key* keyEarpieceSide volume keyMicro USB Port / Earphone jack /Charger portSD card slotCamera keyTurning Your Phone On and Off1.Press and hold the End key until the power comes on.2. Press and hold the End key until the power goes off.Making a call1. Enter a phone number including the area code.2.Press the S key to call the number.3.To end the call, press the E key or the right soft key.Making an international call1. Press and hold the 0 key for the international prefix. The ‘+’character automatically selects the international access code.2.Enter the country code, area code, and the phone number.3.Press S [Send] key to call the number.Answering a call1. When you receive a call, the phone rings and the flashing phone icon appears on the screen.2.If the Any key has been set as the answer mode, any key press will answer a call except for the E key.3.To end the call, press the E key.Selecting functions and optionsYour phone offers a set of functions that allow you to customize the phone. These functions are arranged in menus andsub-menus, accessed via the two soft keys marked < and >. Each menu and sub-menu lets you view and alter thesettings of a particular function.The roles of the soft keys vary according to the current context; the label on the bottom line of the screen just aboveeach key indicates its current role.Entering TextYou can enter alphanumeric characters by using the phone’s keypad. Change the text input mode by pressing the# key. Also # key is used to change the profile to silent mode in idle screen.T9 ModeThe T9 predictive text input mode lets you enter words easily with a minimum number of key presses. As you presseach key, the phone begins to display the characters that it thinks you are typing based on the built-in dictionary.ABC ModeThis mode allows you to enter letters by pressing the key labeled with the required letter once, twice, three or fourtimes until the letter is displayed.123 Mode (Numbers Mode)Type numbers using one keystroke per number.Symbol ModeThe symbol mode enables you to enter various symbols or special characters. To enter a symbol, select Options➞Insert Symbol. Use the navigation keys to select the desired symbol and press the OK key.Anti Theft Mobile Tracker (ATMT)Anti-theft mobile tracker (ATMT) allows you to track your lost phone. When someone uses your phone without your permission, the tracking service will be activated.You are reminded by a text message sent to the default phone number you have set, without the unauthorized user’s knowledge. You can always activate the ATMT and configure your personal settings.To activate Anti-theft mobile tracker1.From the main menu, select Settings > Security > Anti theft mobile tracker and press OK.2.Select Set ATMT and press OK.3.Switch On or Off and press OK.4.Input the ATMT code to enable or disable this function.5.Edit Name, Primary and Secondary numbers and Save the settings.Note› The default ATMT code is “0000”. You have to enter the code before configuring the ATMT settings.Press the left soft key to access theavailable Menu.Press the right soft key to access theavailable Contacts.Menu ContactsQuick feature referenceThis section provides brief explanations of features on your phone.Browser Menu 1Home Connects to a homepage. The homepage will be the site which is defined in the activatedprofile. It will be defined by the service provider if you have not defined it in the activatedprofile.Yahoo! You can access to your Yahoo! Messenger, email accounts from any major providers, do a quicksearch, or view latest news on the Web. For more information, you can visit Yahoo!® Mobile formore information.Bookmarks This menu allows you to store the URL of favorite web pages for easy access at a later time.Enter address You can connect directly to the site you want. After entering a specific URL, press options thenOK key to make the connection Done to connect to the site.History This menu shows the History of recently browsed pages.Settings You can set the profile, cache and security related to internet service.Call history Menu 2All calls You can view all lists of outgoing or incoming calls.Missed calls You can view the unanswered calls.Dialled calls You can view the outgoing calls (called or attempted).Received calls You can view the Received calls.Call duration Allows you to view the duration of your incoming and outgoing calls. You can also reset the call timers.Call cost View the charges applied to your dialled numbers and the call duration of all your received and dialled calls. Also you can do Cost Settings.Data information You can check the amount of data transferred over the network through the GPRS information option. In addition, you can also view how much time you are online.Tools Menu 3Alarm clock You can set the alarm clock to go on at a specified time.Calendar When you enter this menu, a calendar appears. A square cursor is located on the current date.Tools Menu 3 (Continued)Calculator The calculator provides the basic arithmetic functions: addition, subtraction, multiplication anddivision.Memo You can add new memo, view and manage saved memos.To Do You can view, edit and add tasks to do.Unit converter This converts any measurement into a unit you want. There are 2 types that can be converted intounits: Length, WeightWorld clock The World Clock function provides time information on major cities worldwide. Also you can setany city as your Home city and Make Daylight savings ON/OFF.Multimedia Menu 4MP3 player Using the MP3 player in your phone, you can easily enjoy various music.Camera You can take photos with the built in camera and adjust its settings to suit your needs.Video camera You can record a video clip through the built-in camera.Multimedia Menu 4 (Continued)FM radio With embedded FM antenna, you can receive FM radio without an external earphone. You canlisten to your favourite radio station anytime.Note: In weak FM radio signal area the sensitivity can degrade with wireless and antenna mode.So it is advisable to insert the ear-mic for better and enhanced FM quality.Schedule FM record This function allows you to pre-schedule FM radio recordings.Voice recorder You can record voice memo.Melody composer This function allows you to compose a ring tone or melody.Ringtone creator This function allows you to create your own personal ringtones by using this tool.Messaging Menu 5New message This menu includes functions related to SMS (Short Message Service) and MMS (MultimediaMessage Service).Note: You can send SMS to many users at a time. Simply press Option and select Send to Many.This will open contact list where in user can mark/unmark contacts for sending SMS message.Note: To send the SMS to a particular group of contacts, simply press Options and select Send toGroup after composing the SMS.0168。

RG-EG易网关系列产品介绍(V3.1)

RG-EG易网关系列产品介绍(V3.1)

密级：公开文档归属：产品管理部使用对象：全员RG-EG系列易网关上网行为管理产品介绍V3.0福建星网锐捷网络有限公司版权所有侵权必究修订记录前言本文档介绍了EasyGate易网关（简称EG）的产品图片、概述、特性、技术参数、典型应用和订购信息等内容，用于市场宣传产品。

如果您在阅读中产生疑问，请与文档维护人联系。

目录1 产品图片 (1)2 产品概述 (2)3 产品特性 (3)4 技术参数 (3)5 典型应用 (9)6 订购信息 (10)1 产品图片2 产品概述随着网络的发展，互联网应用已经渗透到社会生活的每一个角落，成为人们学习、工作、生活不可或缺的工具，成为企业运营的基础平台。

互联网的开放性、交互性、延伸性为人们快速获取知识、即时沟通以及跨地域交流提供了极大的便利；与此同时，互联网的便利性与虚拟性也成为各种不和谐行为滋生的温床，诽谤中伤、网络恶搞、人肉搜索、工作时间“偷菜”、BT下载、色情网站等问题，就像打开了潘多拉盒子，越来越对国家安定、社会和谐、企业效率、青少年成长等提出了严峻的挑战。

EasyGate易网关（以下简称RG-EG）是锐捷网络公司推出的一款解决当下网络出口难题的多业务综合网关产品。

作为锐捷网络完全自主研发的综合网关，EG产品集成先进的软硬件体系构架，配以先进的DPI深入分析引擎、行为分析/管理引擎，能够在保证网络出口高效转发的基础上，提供专业的流控功能、出色的URL过滤以及本地化的日志存储/审计服务。

此外，EG 的多业务特性还体现在对WEB认证、SSL VPN等功能的支持上。

EG易网关的高性能和七层多业务特性，将大大简化中小规模网络出口的部署难题。

我们不再需要考虑应该使用防火墙、流量控制设备还是路由器，亦或者产品的相互结合。

EG易网关一台设备满足出口部署的必须要求。

锐捷承诺给予5年以上特征库的免费升级。

此外，EG还针对行业细分应用场景定制开发。

针对普教市场的实名制需求，EG推出了WEB实名身份认证、实名流控和实名日志记录功能；针对酒店市场简便易用需求，EG推出了AnyIP的用户即插即用功能，并根据酒店业主需要，支持对酒店主页或广告的推送。