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GS8322V72C-166I中文资料

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PreliminaryGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)2M x 18, 1M x 36, 512K x 7236Mb S/DCD Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA package • Pb-Free packages availableFunctional DescriptionApplicationsThe GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1KQ t KQ (x72)tCycle 3.04.0 3.04.4 3.05.0 3.56.0 3.86.7 4.07.5ns ns Curr (x18)Curr (x36)Curr (x72)285350440265320410245295370220260320210240300185215265mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns Curr (x18)Curr (x36)Curr (x72)205235315195225295185210265175200255165190240155175230mA mA mAGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)209-Bump BGA—x72 Common I/O—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V72 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.An IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCKIScan Test ClockGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V72 209-Bump BGA Pin Description (Continued)SymbolTypeDescriptionGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x36 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ A B NC A A ADSC A A NC B C NC A A V DD A A NC C D DQ DQP V SS ZQ V SS DQP B DQ B D E DQ DQ V SS E1V SS DQ B DQ B E F V DDQ DQ V SS G V SS DQ B V DDQ F G DQ DQ BC ADV BB DQ B DQ B G H DQ DQ V SS GW V SS DQ B DQ B H J V DDQ V DD NC V DD NC V DD V DDQ J K DQ D DQ D V SS CK V SS DQ A DQ A K L DQ D DQ D BD SCD BA DQ A DQ A L M V DDQ DQ D V SS BW V SS DQ A V DDQ M N DQ D DQ D V SS A1V SS DQ A DQ A N P DQ D DQP D V SS A0V SS DQP A DQ A P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump PitchC C C C C C2C C CGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x18 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode ControlTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS8322V18/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380604006035060370603205034050280403004026040280402353025530m AF l o w T h r o u g hI D DI D D Q275402854025540265402353024530225302353021030220302102022020m A(x 36)P i p e l i n eI D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid (x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid (x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.0—7.5—8.0—8.5—8.5—ns Clock to Output ValidtKQ — 6.5—7.0—7.5—8.0—8.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in High-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQd。

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3G终端型号与IMEI

3G终端型号与IMEI

IMEI SERIES COMPANY186902880G3无线座机福建闽邮终端信息技术有限公司235573500G3无线座机深圳泰丰386902400G3无线座机厦门敏讯435169203G3无线座机德赛535169303G3无线座机德赛635303602G3无线座机德赛735169203G3无线座机上海大亚科技835169303G3无线座机上海大亚科技986902500G3无线座机大唐电信1086007200G3无线座机福建瑞恒信息技术有限公司1186020700G3无线座机福建瑞恒信息技术有限公司1286007200G3无线座机福建瑞恒信息技术有限公司1386007200G3无线座机福建瑞恒信息技术有限公司1486902000G3无线座机K-Touch1535169203G3无线座机惠州侨兴电信工业有限公司1635169303G3无线座机惠州侨兴电信工业有限公司1786902600G3无线座机青岛海尔1886901300G3无线座机TCL通讯设备（惠州）有限公司1986006400G3家庭网关Haier2086006100G3家庭网关德赛2186011800G3家庭网关优思2235303602G3家庭网关深圳泰丰2386005000G3家庭网关天津中启创科技有限公司2486003900G3家庭网关华为2586005000G3家庭网关智达康2686006100G3家庭网关大唐移动2786013000G3家庭网关大唐电信2886006100G3家庭网关中兴2986006100G3家庭网关深圳唐信通光电有限公司3086017300G3家庭网关浙江通普通信技术有限公司3186006100G3家庭网关上海大亚科技3286017800G3家庭网关中启创3386017800G3家庭网关中启创3486012600G3家庭网关优思3586020200G3家庭网关上海贝尔3635303602G3家庭网关重庆大唐新数码股份有限公司3786010300G3家庭网关厦门敏讯信息技术股份有限公司3835532003G3家庭网关北京时代动力数码科技有限公司3935303602G3家庭网关福建思特4086010100G3家庭网关福建鑫诺4186006100G3家庭网关南京永成网络电子工程有限公司4235303602G3家庭网关福建星网锐捷通讯股份有限公司4335814002G3家庭网关Rousing4486008600/86006100G3上网笔记本产品宏碁电脑（上海）有限公司4586008600G3上网笔记本产品宏碁电脑（上海）有限公司4686015800G3上网笔记本产品宏碁电脑（上海）有限公司4786008600G3上网笔记本产品宏碁电脑（上海）有限公司4886008600G3上网笔记本产品宏碁电脑（上海）有限公司4986008600G3上网笔记本产品宏碁电脑（上海）有限公司5086008600G3上网笔记本产品宏碁电脑（上海）有限公司5186008600G3上网笔记本产品惠普5286008600G3上网笔记本产品惠普5386008600G3上网笔记本产品惠普5486006100G3上网笔记本产品富士通5586015700G3上网笔记本产品富士通5686006100G3上网笔记本产品明基5786008600G3上网笔记本产品明基5886015800G3上网笔记本产品明基5986006100G3上网笔记本产品明基6086008600G3上网笔记本产品明基6186015800G3上网笔记本产品明基6235303602G3上网笔记本产品三星6386008600G3上网笔记本产品神舟电脑6435303602G3上网笔记本产品神舟电脑6586008600G3上网笔记本产品浙江通普6686008600G3上网笔记本产品浙江通普6786008600G3上网笔记本产品浙江通普6886008600G3上网笔记本产品浙江通普6986006100G3上网笔记本产品北京满疆科技开发有限公司7086008600G3上网笔记本产品北京满疆科技开发有限公司7135303602G3上网笔记本产品TCL7235303602G3上网笔记本产品TCL7386008600G3上网笔记本产品TCL7486006100G3上网笔记本产品北京华旗资讯数码科技有限公司7586014700G3上网笔记本产品北京爱国者存储科技有限责任公司7686014700G3上网笔记本产品北京爱国者存储科技有限责任公司7735303602G3上网笔记本产品DELL7886015800G3上网笔记本产品DELL7935303602G3上网笔记本产品DELL8086006100G3上网笔记本产品苏州海尔信息科技有限公司8186010800G3上网笔记本产品苏州海尔信息科技有限公司8286006100G3上网笔记本产品苏州海尔信息科技有限公司8386006100G3上网笔记本产品万利达8486006100G3上网笔记本产品万利达8586006100G3上网笔记本产品方正8686006100G3上网笔记本产品方正8735303602G3上网笔记本产品长城8835303602G3上网笔记本产品长城8935303602G3上网笔记本产品长城9035303602G3上网笔记本产品长城9186010800G3上网笔记本产品长城9286006100G3上网笔记本产品MSI9386006100G3上网笔记本产品MSI9486008600G3上网笔记本产品Lenovo9586008600G3上网笔记本产品Lenovo9686008600G3上网笔记本产品Lenovo9786008600G3上网笔记本产品Lenovo9886006100G3上网笔记本产品同方股份有限公司9986006100G3上网笔记本产品同方股份有限公司10035303602G3上网笔记本产品同方股份有限公司10135303602G3上网笔记本产品同方股份有限公司10286010800G3上网笔记本产品同方股份有限公司10335303602G3上网笔记本产品KONKA10486006100G3上网笔记本产品神舟电脑10586010800G3上网笔记本产品神舟电脑10686010800G3上网笔记本产品华硕10786006100G3上网笔记本产品华硕10886006100G3上网笔记本产品华硕10986010800G3上网笔记本产品华硕11086010800G3上网笔记本产品华硕11186015800G3上网笔记本产品华为11286010800G3上网笔记本产品重庆大唐新数码股份有限公司11386008600G3上网笔记本产品重庆大唐新数码股份有限公司11486010800G3上网笔记本产品重庆大唐新数码股份有限公司11586008600G3上网笔记本产品明基11686008600G3上网笔记本产品北京睿格先锋电脑有限公司11786006100G3上网笔记本产品七喜11886015800G3上网笔记本产品波导11986008600G3上网笔记本产品宏碁电脑（上海）有限公司12086008600G3上网笔记本产品宏碁电脑（上海）有限公司12186008600G3上网笔记本产品重庆大唐新数码12286015700G3上网笔记本产品华硕12335303602G3上网笔记本产品创维移动通信技术（北京）有限公司12486008600G3上网笔记本产品联想12586017900G3上网笔记本产品12686008600G3上网笔记本产品联想12786010800G3上网笔记本产品KONKA12886010800G3上网笔记本产品KONKA12986010800G3上网笔记本产品深圳市星王电子有限公司130********G3上网笔记本产品苏州海尔信息科技有限公司131********G3上网笔记本产品中国普天132********G3手机产品夏新133********G3手机产品多普达134********G3手机产品大唐电信135********G3手机产品Haier136********G3手机产品Haier137********G3手机产品海信138********G3手机产品海信139********G3手机产品海信14086006000G3手机产品海信14135636702G3手机产品HUAWEI14286000400G3手机产品lenovo14386001400G3手机产品LG144G3手机产品龙旗14586002300G3手机产品MOTOROLA14686000000G3手机产品PANDA147待确认G3手机产品SAMSUNG148待确认G3手机产品SAMSUNG14986004300G3手机产品SAMSUNG150********G3手机产品UT斯达康151********G3手机产品宇龙152********G3手机产品宇龙153********G3手机产品ZTE15486001500G3手机产品ZTE155********G3手机产品ZTE156********G3手机产品ZTE157********G3手机产品ZTE158********G3手机产品华立通信159********G3手机产品OKWAP160G3手机产品新邮通161G3手机产品新邮通16286800000G3手机产品宇龙16386011100G3手机产品宇龙16486800800G3手机产品宇龙16586009000G3手机产品联想移动166********G3手机产品金立16786016800G3手机产品金立16886002800G3手机产品TCL16986004700G3手机产品TCL17086004800G3手机产品TCL17186003500G3手机产品UT斯达康17286008500G3手机产品LG173G3手机产品新邮通17486003100G3手机产品大唐电信175********G3手机产品大唐电信176********G3手机产品华为177********G3手机产品桑菲178********G3手机产品东信17986011600G3手机产品LG180********G3手机产品PANDA181********G3手机产品CECT182********G3手机产品ZTE183********G3手机产品宇龙184********G3手机产品K-Touch185********G3手机产品SAMSUNG186********G3手机产品SAMSUNG187********G3手机产品SAMSUNG188********G3手机产品华为189********G3手机产品华为19086022400G3手机产品华为19186015200G3手机产品LG19235633003G3手机产品扬州万事通通讯电子发展有限公司19386018300G3手机产品港利通19486014200G3手机产品中兴19586017200G3手机产品中兴19686019900G3手机产品宇龙19786019100G3手机产品TCL198********G3手机产品KONKA199********G3手机产品特灵通20086018600G3手机产品LG20186017000G3手机产品K-Touch20286017100G3手机产品K-Touch20386020000G3手机产品宇龙通信20486014900G3手机产品SAMSUNG20586012900G3手机产品Lenovo20686022400G3手机产品HUAWEI20786021100G3手机产品Haier20886020100G3手机产品宇龙计算机通信科技（深圳）有限公司20986017400G3手机产品多普达21086021900G3手机产品中兴21135920203G3手机产品SAMSUNG21286018900G3手机产品SAMSUNG21386021500G3手机产品德赛21486019600G3手机产品美菱21586358300G3手机产品美菱21686010800G3上网笔记本产品中通嘉铭科技（北京）有限公司21735424803G3上网笔记本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MACHINE_TYPE RATE RATE_INFO PROVINCE G3无线座机5112湖南G3无线座机HWCD888（6）湖南G3无线座机TD1000湖南G3无线座机TD-169(J)湖南G3无线座机TD-169(J)湖南G3无线座机TD-169(J)湖南G3无线座机DT306湖南G3无线座机DT306湖南G3无线座机TDW810湖南G3无线座机"5212(行业应用终端)"湖南G3无线座机"5212(行业应用终端)"湖南G3无线座机"5312(可视终端)"湖南G3无线座机"5312(可视终端)"湖南G3无线座机W01湖南G3无线座机HR8188（1）TD湖南G3无线座机HR8188（1）TD湖南G3无线座机HT-FT100湖南G3无线座机TD100湖南G3家庭网关HT-DM300+湖南G3家庭网关TD-166(U)湖南G3家庭网关TG300湖南G3家庭网关G6-W1湖南G3家庭网关 PM-HGW-T-1300湖南G3家庭网关D100+ET128湖南G3家庭网关Z3G-700湖南G3家庭网关DTA-202湖南G3家庭网关TDR900湖南G3家庭网关ZTE FT281湖南G3家庭网关H-60湖南G3家庭网关U-GT180湖南G3家庭网关DB5005湖南G3家庭网关PM-HGW-T-1301湖南G3家庭网关PM-HGW-T-1302湖南G3家庭网关TG200湖南G3家庭网关DA8201-B湖南G3家庭网关DTD-H101湖南G3家庭网关DT1000湖南G3家庭网关TD 3G800 湖南G3家庭网关HCD-986T-R湖南G3家庭网关TD-G9（分体）湖南G3家庭网关TF3000湖南G3家庭网关HG-T800湖南G3家庭网关RX800-P湖南acer Aspire One ZG5湖南acer Aspire One ZG8湖南acer Aspire One ZG8湖南Aspire Timeline Series Aspire 4810TZ湖南Aspire Timeline Series Aspire 3810TZ湖南Aspire Timeline Series Aspire 1810TZ湖南Aspire Timeline Series Aspire 1410湖南Mini mini 1131/1065湖南HP probook hp 4415s湖南HP probook HP 4310s湖南U系列U2010湖南Lifebook P3110湖南Joybook U101湖南Joybook U101湖南Joybook U101湖南Joybook U101C湖南Joybook U101C湖南Joybook U101C湖南NC10系列NC10湖南优雅U10T湖南优雅Q130T湖南U-NT100湖南netbook NT-200湖南MID U-NT300湖南MID U-NT400湖南CM102CM102-1湖南CM102CM102-2湖南T T36湖南T T18湖南T T28湖南MID P8880T湖南Netbook U6610T湖南Netbook U6600T湖南Inspiron Mini10湖南Inspiron Mini10湖南Inspiron1110湖南开心小本海尔X105湖南开心小本海尔X105湖南开心小本海尔X200湖南M-Book灵动PC-81006N湖南M-Book灵动PC-81009/升级版湖南BiG B102湖南颐和E100湖南A系列LA91湖南A系列LT91湖南A系列LA92湖南A系列LA93湖南A NB A100湖南MS-N033U123H湖南MS-1351X320H湖南昭阳M10W湖南Ideapad S11W湖南昭阳K43G湖南Ideapad Y450A湖南超锐X30湖南超锐X32A湖南imini S2湖南imini S5湖南锋锐S5湖南E E3湖南优雅U10T湖南优雅Q130T湖南Eee PC1000HG湖南NB N20A湖南NB N81A湖南Eee PC1003HAG湖南NB U6Vc湖南上网本HUAWEI M3801T湖南大唐数码3G上网本DTD-N101湖南大唐数码3G上网本DTD-N104D湖南大唐数码3G上网本DTD-N106湖南U系列U101C15湖南名师M1湖南YOYO S120湖南F35600湖南Aspire Timeline Series3810T/TZ湖南Aspire Timeline series4810T/TZ湖南大唐数码3G上网本DTD-N102湖南UL UL30湖南@BOOK S40湖南昭阳S10-2湖南湖南Ideapad U350w湖南E系列E500湖南E系列E520湖南E102E10202-TD湖南开心小本海尔X105P湖南上网本POTEVIO_CPNB1020-T湖南G3手机产品T5湖南G3手机产品S700湖南G3手机产品TG2000湖南G3手机产品HT-T300湖南G3手机产品HT-TV001湖南G3手机产品HS-T66湖南G3手机产品HS-T68湖南G3手机产品HS-TG95湖南G3手机产品HS-TM86湖南G3手机产品HUAWEI S660湖南G3手机产品TD800湖南G3手机产品KD876湖南G3手机产品TD290湖南G3手机产品L800T湖南G3手机产品TD988湖南G3手机产品SGH-L288湖南G3手机产品SGH-i688湖南G3手机产品GT-I6320C湖南G3手机产品D60湖南G3手机产品CoolPad 6268湖南G3手机产品CoolPad 6168湖南G3手机产品U85湖南G3手机产品U860湖南G3手机产品U981湖南G3手机产品U728湖南G3手机产品ZTE-T U210湖南G3手机产品H8310湖南G3手机产品OK982湖南G3手机产品N269湖南G3手机产品T809湖南G3手机产品CoolPad 6260湖南G3手机产品6168H湖南G3手机产品6268H湖南G3手机产品TD900T湖南G3手机产品TD86湖南G3手机产品TD108湖南G3手机产品TCL U398湖南G3手机产品TCL U298湖南G3手机产品TCL U888湖南G3手机产品S68湖南G3手机产品KD877湖南G3手机产品T811湖南G3手机产品TG2028湖南G3手机产品TG2008湖南G3手机产品HUAWEI T550湖南G3手机产品Philips TM700湖南G3手机产品EZ388湖南G3手机产品KT878湖南G3手机产品PT701湖南G3手机产品T3湖南G3手机产品ZTE-T U862湖南G3手机产品F69湖南G3手机产品E500湖南G3手机产品GT-S3930C湖南G3手机产品GT-S5630C湖南G3手机产品GT-S5630C湖南G3手机产品HUAWEI T550+湖南G3手机产品HUAWEI T552湖南G3手机产品HUAWEI T2211湖南G3手机产品GD300s湖南G3手机产品MASTONE G1湖南G3手机产品KPT KP800T湖南G3手机产品ZTE-T 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RTL8326中文资料

RTL8326中文资料

6．引脚说明使用类型代码：P=电源、G=地、I=输入电路、O=输出电路、Pu=内部上拉75KΩ电阻、Pd=内部下拉75KΩ电阻6.1 SMII接口（Port0-23）符号类型引脚描述P0TXD P1TXD P2TXD P3TXD P4TXD P5TXD P6TXD P7TXD P8TXD P9TXD P10TXD P11TXD P12TXD P13TXD P14TXD P15TXD P16TXD P17TXD P18TXD P19TXD P20TXD P21TXD P22TXD P23TXD O 579131618202629313537404246515456586267697173SMII发送数据输出：SMII传输10位串行字节每个字都包含一个数据字节（4B编码数据两个半字节）和2个状态位SMII使用一个全球性的参考时钟频率125 MHz输入时钟和同步帧信号SMII数据输入引脚，端口0〜7接收数据同步SYNC_0_7和REFCLK_0_7引脚端口8〜15接收数据同步SYNC_8_15和REFCLK_8_15引脚端口16〜23接收数据同步SYNC_16_23和REFCLK_16_23引脚P0RXD P1RXD P2RXD P3RXD P4RXD P5RXD P6RXD P7RXD P8RXD P9RXD P10RXD P11RXD P12RXD P13RXD P14RXD I 6810141719212730323638414347SMII接收数据输入：SMII数据输入引脚，端口0〜7接收数据同步SYNC_0_7和REFCLK_0_7引脚端口8〜15接收数据同步SYNC_8_15和REFCLK_8_15引脚端口16〜23接收数据同步SYNC_16_23和REFCLK_16_23引脚P15RXD P16RXD P17RXD P18RXD P19RXD P20RXD P21RXD P22RXD P23RXD 52 55 57 59 63 68 70 72 74SYNC_0_7 SYNC_8_15 SYNC_16_23 O 153966SMII同步输出SMII发送、接收10位的同步帧数据SYNC_0_7 同步数据端口0~7.SYNC_8_15 同步数据端口8~15.SYNC_16_23 同步数据端口16~23.REFCLK_0_7 REFCLK_8_15 REFCLK_16_23 O 285377SMII参考时钟输出SMII参考时钟输出125M +-50ppm频率误差Port0-7发送或接收同步到REFCLK_0_7Port8-15发送或接收同步到REFCLK_8_15Port16-23发送或接收同步到REFCLK_16_236.2 TBI/GMII/MII接口（PortG0-G1）符号模式类型引脚描述G0TX_CLK G0TX_CLK Not Used TBIGMIIMIIO 96 千兆端口发送时钟输出（TBI的模式）。

北斗车载终端参考资料

北斗车载终端参考资料

北斗车载终端参考资料1、航天智科技◆技术参数▲产品型号: 航天智科HT-310W▲核心处理器:STM32F103VC+TCC8902▲主频：720M赫兹▲操作系统:WIN CE6.0▲闪存FLASH :4G▲内存:256MB▲液晶显示屏:5寸TFT高亮屏,支持1080P全高清播放，分辨率800*480▲触摸屏:高精度耐磨触摸屏▲USB :USB client 2.0▲扩展接口:1路RS232串口、485接口、CAN总线、3路I/O▲SD卡插槽:双SD卡插槽，单个最大支持32GB▲通讯模块:3G：WCDMA/CDMA2000▲定位模块：北斗/GPS双模或GPS▲冷启动：<35秒▲热启动：<2秒（在空旷地方）▲输入电压/电流：宽幅输入电压:DC 10.5V～36V 电流：2A▲温度范围：工作温度：－20℃～70℃▲储存温度：－30℃～80℃▲行驶记录仪升级：串口或远程▲应用程序升级：通过SD卡▲产品尺寸：160mm*100mm*34mm L*W*H2、贝尔科技北斗部标车载终端产品介绍：产品类型：北斗部标车载终端视频处理芯片：DAVINCI 处理器视频压缩标准：H.264铝制外壳、设备体积小、功耗低产品标配主机1台、汽车连接线1套、北斗+GPS双模天线1条、GPRS天线2条、包装盒1个实现功能：1、实时监控——指挥平台随时远程调取每个前端摄像机查看实时的图像；2、实时录音功能——指挥中心随时远程预览前端画面的声音信息；3、同步录像——3G无线监控的前端移动监察终端本地同步记录处理过的全部视音数据，后台中心记录应急指挥等视频；4、浏览历史录像——指挥平台随时可以调取每个视频终端的历史视音记录；5、超速报警功能——当车辆超速的情况下，设备会将报警信息发送到平台；6、超速报警联动功能——设备发生超速报警时服务器终端会自动录制超速报警时的录像，直接本地保存；7、高速路进出自动录像功能——便于合适车上实际乘客人数；8、信息叠加功能——设备的速度，位置经纬度，时间，车牌号，图像进行叠加功能，每秒25帧画面记录；9、客运车辆——蚂蚁线功能将客运车辆的运营线路按一定比例尺规划成一条线，出发车辆在直线上行进，返回车辆按线段两端按发车时序上下排序；直线用不同的颜色先进行标注国道，升到和高速；10、云台控制——支持远程云台控制，控制云台的摄像头的变倍，放大缩小；11、门磁报警功能——支持三路门磁报警功能当车辆开门时间进行报警录像；技术参数：操作系统嵌入式RTOS操作系统视频压缩标准H.264预览分辨率PAL：704×576(4CIF)；NTSC：704×480(4CIF)回放分辨率4CIF/DCIF/2CIF/CIF/QCIF视频输入1/4路(PAL/NTSC自动识别；电平：1.0Vp-p，阻抗：75Ω)，视频输出1路(PAL/NTSC可选；电平：1.0Vp-p，阻抗：75Ω)视频帧率PAL：1/16 ~ 25帧/秒；NTSC：1/16 ~ 30帧/秒视频压缩码率32K ~ 2M可调，也可自定义，上限8M(单位：bps)音频压缩标准OggVorbis音频输入1/2路(电平：2.0~2.4Vp-p，阻抗：1000Ω)音频输出1路(电平：2.0~2.4Vp-p，阻抗：600Ω)码流类型可选择单一视频流或复合流报警输入3路电平信号输入报警输出1路开关量或干节点信号输出无线网络传输模块内置，SMA天线接口GPS定位内置高灵敏度北斗模块，SMA天线接口数据存储硬盘存储支持最大容量500G数据备份硬盘备份、USB备份通讯接口LAN、USB接口各1个延时关机车辆熄火后可延时5min ~ 6h后关机电源输入DC +6 ~ +36V电源输出DC +12V/2A、+5V/2A（USB口输出）设备功耗5W工作温度-10℃ ~ +55℃工作湿度10％~ 95％产品尺寸175mm（宽）×71mm（高）×129mm（深）产品重量约1Kg物理接口：①SD 存储卡插口；②SIM/UIM 卡插口；③LAN；④USB；⑤指示灯。

GS8322V72GC-133I中文资料

GS8322V72GC-133I中文资料

PreliminaryGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)2M x 18, 1M x 36, 512K x 7236Mb S/DCD Sync Burst SRAMs250 MHz –133 MHz1.8 V V DD 1.8 V I/O119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable• IEEE 1149.1 JTAG-compatible Boundary Scan• ZQ mode pin for user-selectable high/low output drive • 1.8 V +10%/–10% core power supply • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications• JEDEC-standard 119-, 165-, and 209-bump BGA package • Pb-Free packages availableFunctional DescriptionApplicationsThe GS8322V18/36/72 is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count ineither linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM inPipeline mode, activating the rising-edge-triggered Data Output Register.SCD and DCD Pipelined ReadsThe GS8322V18/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.FLXDrive™The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.Parameter Synopsis-250-225-200-166-150-133UnitPipeline 3-1-1-1KQ t KQ (x72)tCycle 3.04.0 3.04.4 3.05.0 3.56.0 3.86.7 4.07.5ns ns Curr (x18)Curr (x36)Curr (x72)285350440265320410245295370220260320210240300185215265mA mA mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.07.07.57.58.08.08.58.58.58.5ns ns Curr (x18)Curr (x36)Curr (x72)205235315195225295185210265175200255165190240155175230mA mA mAGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)209-Bump BGA—x72 Common I/O—Top View (Package C)1234567891011A DQ G DQ G A E2ADSP ADSC ADV E3A DQB DQ B AB DQ G DQ G BC BG NC BW A BB BF DQ B DQ B BC DQ G DQ G BH BD NC E1NC BE BA DQ B DQ B CD DQ G DQ G V SS NC NC G GW NC V SS DQ B DQ B DE DQP G DQP C V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQPF DQP B EF DQ C DQ C V SS V SS V SS ZQ V SS V SS V SS DQ F DQ F FG DQ C DQ C V DDQ V DDQ V DD MCH V DD V DDQ V DDQ DQ F DQ F GH DQ C DQ C V SS V SS V SS MCL V SS V SS V SS DQ F DQ F H J DQ C DQ C V DDQ V DDQ V DD MCL V DD V DDQ V DDQ DQ F DQ F J K NC NC CK NC V SS MCL V SS NC NC NC NC K L DQ H DQ H V DDQ V DDQ V DD FT V DD V DDQ V DDQ DQ A DQ A L M DQ H DQ H V SS V SS V SS MCL V SS V SS V SS DQ A DQ A M N DQ H DQ H V DDQ V DDQ V DD SCD V DD V DDQ V DDQ DQ A DQ A N P DQ H DQ H V SS V SS V SS ZZ V SS V SS V SS DQ A DQ A P R DQP D DQP H V DDQ V DDQ V DD V DD V DD V DDQ V DDQ DQP A DQP E R T DQ D DQ D V SS NC NC LBO NC NC V SS DQ E DQ E T U DQ D DQ D NC A A A A A A DQ E DQ E U V DQ D DQ D A A A A1A A A DQ E DQ E V W DQ D DQ D TMS TDI A A0A TDO TCK DQ E DQ E W11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V72 209-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset Inputs.An IAddress InputsDQ A DQ B DQ C DQ D DQ E DQ F DQ G DQ H I/O Data Input and Output pinsB A , B B I Byte Write Enable for DQ A , DQ B I/Os; active low BC ,BD I Byte Write Enable for DQ C , DQ D I/Os; active low BE , BF , BG ,B HI Byte Write Enable for DQ E , DQ F , DQ G , DQ H I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highGW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowSCD I Single Cycle Deselect/Dual Cycle Deselect Mode ControlMCH IMust Connect High MCL Must Connect Low BW I Byte Enable; active lowZQ I FLXDrive Output Impedance Control(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCKIScan Test ClockGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V72 209-Bump BGA Pin Description (Continued)SymbolTypeDescriptionGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x18 Commom I/O—Top View (Package E)1234567891011A NC A E1BB NC E3BW ADSC ADV A A AB NC A E2NC BA CK GW G ADSP A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB SCD V DDQ V SS NC A NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A A PR LBO A A A TMS A0TCK A A A A R11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)165-Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3BW ADSC ADV A NC A B NC A E2BD BA CK GW G ADSP A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCL NC V DD V SS V SS V SS V DD NC ZQ ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD SCD V DDQ V SS NC A NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A A P RLBOAAATMSA0TCKAAAAR11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch(Package E)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low (x36 Version)NC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active l0w ADSC, ADSPI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect LowSCD —Single Cycle Deselect/Dual Cyle Deselect Mode ControlV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x36 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ A B NC A A ADSC A A NC B C NC A A V DD A A NC C D DQ DQP V SS ZQ V SS DQP B DQ B D E DQ DQ V SS E1V SS DQ B DQ B E F V DDQ DQ V SS G V SS DQ B V DDQ F G DQ DQ BC ADV BB DQ B DQ B G H DQ DQ V SS GW V SS DQ B DQ B H J V DDQ V DD NC V DD NC V DD V DDQ J K DQ D DQ D V SS CK V SS DQ A DQ A K L DQ D DQ D BD SCD BA DQ A DQ A L M V DDQ DQ D V SS BW V SS DQ A V DDQ M N DQ D DQ D V SS A1V SS DQ A DQ A N P DQ D DQP D V SS A0V SS DQP A DQ A P R NC A LBO V DD FT A NC R T NC NC A A A A ZZ T UV DDQTMSTDITCKTDONCV DDQU7 x 17 Bump BGA—14 x 22 mm 2 Body—1.27 mm Bump PitchC C C C C C2C C CGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)119-Bump BGA—x18 Common I/O—Top View1234567A V DDQ A A ADSP A A V DDQ AB NC A A ADSC A A NC BC NC A A V DD A A NC CD DQ B NC V SS ZQ V SS DQP A NC DE NC DQ B V SS E1V SS NC DQ A EF V DDQ NC V SSG V SS DQ A V DDQ FG NC DQ B BB ADV NC NC DQ A GH DQ B NC V SS GW V SS DQ A NC HJ V DDQ V DD NC V DD NC V DD V DDQ JK NC DQ B V SS CK V SS NC DQ A KL DQ B NC NC SCD BA DQ A NC LM V DDQ DQ B V SS BW V SS NC V DDQ MN DQ B NC V SS A1V SS DQ A NC NP NC DQP B V SS A0V SS NC DQ A PR NC A LBO V DD FT A NC RT NC A A A A A ZZ TU V DDQ TMS TDI TCK TDO NC V DDQ U7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump PitchGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)GS8322V18/36 119-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsAn I Address Inputs DQ A DQ B DQ C DQ D I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active highBW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active lowE 1I Chip Enable; active low G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [LowDrive])SCD I Single Cycle Deselect/Dual Cyle Deselect Mode ControlTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock V DD I Core power supply V SS I I/O and Core Ground V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)A1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–An LBO ADV CK ADSC ADSP GW BW E 1FT GZZPower Down ControlMemory Array36364AQD DQx1–DQx93636Note: Only x36 version shown for simplicity.SCD3636B AB BB CB DGS8322V18/36 Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance ControlZQL High Drive (Low Impedance)H or NCLow Drive (High Impedance)GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110I nterleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Byte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXX1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C , and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1ADSPADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CWH X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend BurstCurrentHXHHTDNotes:1.X = Don’t Care, H = High, L = Low2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)First WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs andassumes ADSP is tied high and ADV is tied low.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Simplified State Diagram with GAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 3.6V V DDQ Voltage in V DDQ Pins –0.5 to 3.6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 3.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 3.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD 1.6 1.82.0V 1.8 V V DDQ I/O Supply VoltageV DDQ1.61.82.0VNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed3.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 100 uA FT, SCD, and ZQ Input Current I IN2V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL–100 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V—Output Low VoltageV OL1I OL = 4 mA, V DD = 1.6 V—0.4 VGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)O p e r a t i n g C u r r e n t sP a r a m e t e r T e s t C o n d i t i o n s M o d eS y m b o l -250-225-200-166-150-133U n i t0t o 70°C –40 t o 85°C0t o 70°C–40 t o 85°C 0t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C 0 t o 70°C –40t o 85°C O p e r a t i n g C u r r e n tD e v i c e S e l e c t e d ; A l l o t h e r i n p u t s ≥V I H o r ≤ V I LO u t p u t o p e n(x 72)P i p e l i n eI D DI D D Q380604006035060370603205034050280403004026040280402353025530m AF l o w T h r o u g hI D DI D D Q275402854025540265402353024530225302353021030220302102022020m A(x 36)P i p e l i n eI D DI D D Q300503205027545295452554027540225352453521030230301902521025m AF l o w T h r o u g hI D DI D D Q210252202520025210251902020020180201902017020180201601517015m A(x 18)P i p e l i n eI D DI D D Q260252802524025260252252024520200202202019020210201701519015m AF l o w T h r o u g hI D DI D D Q190152001518015190151701518015160151701515015160151401515015m AS t a n d b y C u r r e n tZ Z ≥ V D D – 0.2 V—P i p e l i n eI S B 608060806080608060806080m AF l o w T h r o u g hI S B608060806080608060806080m AD e s e l e c t C u r r e n tD e v i c e D e s e l e c t e d ; A l l o t h e r i n p u t s ≥ V I H o r ≤ V I L—P i p e l i n eI D D100115951109010585100851008095m AF l o w T h r o u g hI D D85100851008095809575907085m AN o t e s : 1.I D D a n d I D D Q a p p l y t o a n y c o m b i n a t i o n o f V D D 3, V D D 2, V D D Q 3, a n d V D D Q 2 o p e r a t i o n .2.A l l p a r a m e t e r s l i s t e d a r e w o r s t c a s e s c e n a r i o .AC Electrical CharacteristicsParameterSymbol-250-225-200-166-150-133UnitMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 4.0— 4.4— 5.0— 6.0— 6.7—7.5—ns Clock to Output Valid (x18/x36)tKQ — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns Clock to Output Valid (x72)tKQ — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Setup time tS 1.2— 1.3— 1.4— 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.3—0.4—0.5—0.5—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.0—7.5—8.0—8.5—8.5—ns Clock to Output ValidtKQ — 6.5—7.0—7.5—8.0—8.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in High-Z (x18/x36)tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns Clock to Output in High-Z (x72)tHZ 1 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid (x18/x36)tOE — 2.5— 2.7— 3.0— 3.5— 3.8— 4.0ns G to Output Valid(x72)tOE — 3.0— 3.0— 3.0— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z (x18/x36)tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns G to output in High-Z (x72)tOHZ 1— 3.0— 3.0— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—20—nsGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Notes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Pipeline Mode Timing (SCD)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8322V18(B/E)/GS8322V36(B/E)/GS8322V72(C)Flow Through Mode Timing (SCD)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQd。