KK74LV245DW中文资料

MC74LCX245Low−Voltage CMOS Octal TransceiverWith 5 V−Tolerant Inputs and Outputs (3−State, Inverting)The MC74LCX245 is a high performance, non−inverting octal transceiver operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows MC74LCX245 inputs to be safely driven from 5 V devices. The MC74LCX245 is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24 mA at both A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bi−directional transceiver. Transmit (active−HIGH) enables data from A ports to B ports; Receive (active−LOW) enables data from B to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. Features•Designed for 2.3 to 3.6 V V CC Operation•5 V Tolerant − Interface Capability With 5 V TTL Logic •Supports Live Insertion and Withdrawal•I OFF Specification Guarantees High Impedance When V CC = 0 V •LVTTL Compatible•LVCMOS Compatible•24 mA Balanced Output Sink and Source Capability•Near Zero Static Supply Current in All Three Logic States (10 m A) Substantially Reduces System Power Requirements •Latchup Performance Exceeds 500 mA•ESD Performance:Human Body Model >2000 VMachine Model >200 V•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.ORDERING INFORMATIONB0OE 19T/R 1A0B1A1B2A2B3A3B4A4B5A5B6A6B7A7Figure 1. Pinout (Top View)192018171615142134567V CC 1381291110OE B0B1B2B3B4B5B6B7T/RA0A1A2A3A4A5A6A7GNDH = High Voltage Level L = Low Voltage Level Z = High Impedance StateX = High or Low Voltage Level and Transitions are Acceptable For I CC reasons, Do Not Float InputsFigure 2. Logic DiagramMAXIMUM RATINGSvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.I O absolute maximum rating must be observed.RECOMMENDED OPERATING CONDITIONSORDERING INFORMATIONSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.DC ELECTRICAL CHARACTERISTICSIAC CHARACTERISTICS t R = t F = 2.5 ns; R L = 500 WThe specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OSHL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.DYNAMIC SWITCHING CHARACTERISTICSmeasured in the LOW state.CAPACITIVE CHARACTERISTICSWAVEFORM 1 − PROPAGATION DELAYS t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns V CC0 VV OHV OLAn, BnWAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMESt R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns0 V Figure 3. AC WaveformsV OH V HZV OLV CCV LZ Symbol V CC3.3 V ±0.3 V2.7 V 2.5 V ±0.2 VVmi 1.5 V 1.5 V V CC /2Vmo 1.5 V 1.5 V V CC /2V HZ V OL + 0.3 V V OL + 0.3 V V OL + 0.15 V V LZV OH − 0.3 VV OH − 0.3 VV OH − 015 VBn, AnOPENV6 V GNDC L = 50 pF at V CC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)C L = 30 pF at V CC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)R L = R 1 = 500 W or equivalentR T = Z OUT of pulse generator (typically 50 W )Figure 4. Test CircuitPACKAGE DIMENSIONSSOIC−20DW SUFFIX CASE 751D−05ISSUE GTSSOP−20DT SUFFIX CASE 948E−02ISSUE BDIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION:MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.6.400.252−−−−−−PACKAGE DIMENSIONSSOEIAJ−20M SUFFIX CASE 967−01ISSUE ODIM MIN MAX MIN MAX INCHES−−− 2.05−−−0.081MILLIMETERS 0.050.200.0020.0080.350.500.0140.0200.180.270.0070.01112.3512.800.4860.5045.10 5.450.2010.2151.27 BSC 0.050 BSC 7.408.200.2910.3230.500.850.0200.0331.10 1.500.0430.0590 0.700.900.0280.035−−−0.81−−−0.032A 1H E Q 1L E _10 _0 _10 _NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH ORPROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).A b c D E e L M ZON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

74LVC245A; 74LVCH245AOctal bus transceiver; 3-stateRev. 9 — 11 September 2018Product data sheet1. General descriptionThe 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state buscompatible outputs in both send and receive directions. The device features an output enable(OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls theoutputs so that the buses are effectively isolated.Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied tothe outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up resistors to holdunused inputs.2. Features and benefits• 5 V tolerant inputs/outputs for interfacing with 5 V logic•Wide supply voltage range from 1.2 V to 3.6 V•CMOS low-power consumption•Direct interface with TTL levels•Inputs accept voltages up to 5.5 V•High-impedance when V CC = 0 V•Bus hold on all data inputs (74LVCH245A only)•Complies with JEDEC standard:•JESD8-7A (1.65 V to 1.95 V)•JESD8-5A (2.3 V to 2.7 V)•JESD8-C/JESD36 (2.7 V to 3.6 V)•ESD protection:•HBM JESD22-A114F exceeds 2000 V•MM JESD22-A115B exceeds 200 V•CDM JESD22-C101E exceeds 1000 V•Specified from -40 °C to +85 °C and -40 °C to +125 °C3. Ordering information4. Functional diagram5. Pinning information5.1. Pinning74LVC245A 74LVCH245ADIR V CC A0OE A1B0A2B1A3B2A4B3A5B4A6B5A7B6GND B7001aak2921234567891012111413161518172019Fig. 3.Pin configuration SOT163-1 (SO20),SOT339-1 (SSOP20) and SOT360-1 (TSSOP20)001aak29374LVC245A 74LVCH245AT ransparent top viewB6A6A7B5A5B4A4B3A3B2A2B1A1B0A0OE G N D B 7D I R V C C9128137146155164173182191011120terminal 1 index areaGND (1)(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND.Fig. 4.Pin configuration SOT764-1 (DHVQFN20)5.2. Pin description6. Functional descriptionTable 3. Function selectionH = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.7. Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1]The minimum input voltage ratings may be exceeded if the input current ratings are observed.[2]The output voltage ratings may be exceeded if the output current ratings are observed.[3]For SO20 packages: above 70 °C derate linearly with 8 mW/K.For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.8. Recommended operating conditions9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).[1]All typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb = 25 °C.[2]The bus hold circuit is switched off when V I ˃ V CC allowing 5.5 V on the input terminal.[3]For I/O ports the parameter I OZ includes the input leakage current.[4]Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit.[5]The specified sustaining current at the data input holds the input below the specified V I level.[6]The specified overdrive current at the data input forces the data input to the opposite input state.10. Dynamic characteristicsTable 7. Dynamic characteristicsVoltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.[1]Typical values are measured at T amb = 25 °C and V CC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.[2]t pd is the same as t PLH and t PHL.t en is the same as t PZL and t PZH.t dis is the same as t PLZ and t PHZ.[3]Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.[4]C PD is used to determine the dynamic power dissipation (P D in μW).P D = C PD × V CC2 × f i × N + Σ(C L × V CC2 × f o) where:f i = input frequency in MHz; f o = output frequency in MHzC L = output load capacitance in pFV CC = supply voltage in VoltsN = number of inputs switchingΣ(C L × V CC2 × f o) = sum of the outputs.10.1. Waveforms and test circuit11. Package outlineSO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1Fig. 8.Package outline SOT163-1 (SO20)SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1Fig. 9.Package outline SOT339-1 (SSOP20)TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Fig. 10.Package outline SOT360-1 (TSSOP20)DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;Fig. 11.Package outline SOT764-1 (DHVQFN20)12. Abbreviations13. Revision history14. Legal informationData sheet status[1]Please consult the most recently issued document before initiating orcompleting a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available onthe internet at https://.DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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The English version shall prevail in case of any discrepancy between the translated and English versions.TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.Contents1. General description (1)2. Features and benefits (1)3. Ordering information (2)4. Functional diagram (2)5. Pinning information (3)5.1. Pinning (3)5.2. Pin description (3)6. Functional description (3)7. Limiting values (4)8. Recommended operating conditions (4)9. Static characteristics (5)10. Dynamic characteristics (7)10.1. Waveforms and test circuit (8)11. Package outline (10)12. Abbreviations (14)13. Revision history (14)14. Legal information (15)© Nexperia B.V. 2018. All rights reservedFor more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release: 11 September 2018。

74LV245是低压硅栅CMOS器件，与74HC245和74HCT245针脚和功能兼容。

74LV245是八位元收发器，在发送和接收方向上都具有非反相3态总线兼容输出。

发送/接收(DIR)输入控制方向，而输出使能(OE)输入则可实现轻松级联。

针脚OE控制输出，因此总线可以得到有效隔离。

特性和优势
•宽工作电压范围：1.0 V至5.5 V
•最适合低压应用：1.0 V至3.6 V
•接受介于VCC = 2.7 V和VCC = 3.6 V之间的TTL输入电平
•VCC = 3.3 V且T amb = 25 °C时的典型输出地弹：< 0.8 V
•VCC = 3.3 V且T amb = 25 °C时的典型高电平输出电压(VOH)欠冲：> 2 V •ESD保护：
o HBM JESD22-A114E超过2000 V
o MM JESD22-A115-A超过200 V
•多种封装选择
•额定温度范围为-40 °C至+85 °C和-40 °C至+125 °C
外形图
显示功能框图
真值表
INPUTS INPUTS/OUTPUT OE DIR An Bn
H=高电压L=低电压X=无输入、Z=高阻态。

元器件交易网DIP20:plastic dual in-line package; 20 leads (300 mil)SOT146-1SO20:plastic small outline package; 20 leads; body width 7.5 mm SOT163-1SSOP20:plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1TSSOP20:plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.This data sheet contains preliminary data, and supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to make changes at any time without notice in order to improve designand supply the best possible product.Philips Semiconductors811 East Arques AvenueP .O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381DEFINITIONSData Sheet IdentificationProduct Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full ProductionThis data sheet contains the design target or goal specifications for product development. Specificationsmay change in any manner without notice.This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changesat any time without notice, in order to improve design and supply the best possible product.© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print codeDate of release: 05-96。