KK74VHC244中文资料

最小 额定 最大
电源电压Vcc 54 4.5 5 5.5 V
74 4.75 5 5.25
输入高电平电ViH 2 V
输入低电平电ViL 54 0.7 V
74 0.8
输出高电平电流IOH 54 -12 mA
74 -15
输出低电平电流IOL 54 12 mA
74 24
求关于74HC244线接收器(3S,两组控制)
简要说明:
244为三态输出的八组缓冲器和总线驱动器,其主要电器特性的典型值如下(不同厂家具体值有差别):
型号 tPLH tphl PD
54LS241/74LS241 12ns 12ns 110mW
引出端符号:
1A1~1A4,2A1~2A4 输入端
/1G, /2G 三态允许端(低电平有效)
1Y1~1Y4,2Y1~2Y4 输出端
逻辑图:
双列直插封装
极限值:
电源电压 …………………………………………. 7V
输入电压 …………………………………………. 5.5V
tPHZ输出由高到高阻态禁止时间 Vcc=5V CL=5pF
RL=90 Ω 18 ns
tPLZ输出由低到高阻态禁止时间 25 ns
静态特性（TA为工作环境温度范围）
参 数 测 试 条 件【1】 LS244 单位
最小 最大
VIK输入嵌位电压 Vcc=最小，Iik=-18mA -1.5 V
输出高阻态时高电平电压 …………………………. 5.5V
工作环境温度
54XXX …………………………………. -55~125℃
74XXX …………………………………. 0~70℃

© 1999 Fairchild Semiconductor Corporation DS500154July 1999Revised August 199974LVT244 •74LVTH244 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs74LVT244 •74LVTH244Low Voltage Octal Buffer/Line Driver with 3-STATE OutputsGeneral DescriptionThe LVT244 and LVTH244 are octal buffers and line drivers designed to be employed as memory address drivers,clock drivers and bus oriented transmitters or receivers which provide improved PC board density.The LVTH244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These octal buffers and line drivers are designed for low-voltage (3.3V) V CC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT244and LVTH244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for externalpull-up resistors to hold unused inputs (74LVTH244),also available without bushold feature (74LVT244)s Live insertion/extraction permitteds Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mAs Functionally compatible with the 74 series 244s Latch-up performance exceeds 500 mAOrdering Code:Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Logic SymbolIEEE/IECOrder Number Package NumberPackage Description74LVT244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVT244MSA MSA2020-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVT244MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVTH244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LVTH244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH244MSA MSA2020-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LVTH244MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 274L V T 244 •74L V T H 244Connection Diagram Pin DescriptionsTruth TablesH = HIGH Voltage Level L = LOW Voltage Level X = ImmaterialZ = High ImpedancePin Names DescriptionOE 1, OE 23-STATE Output Enable Inputs I 0–I 7Inputs O 0–O 7OutputInputs OutputsOE 1I n (Pins 12, 14, 16, 18)L L L L H H HXZ Inputs OutputsOE 2I n (Pins 3, 5, 7, 9)L L L L H H HXZ74LVT244 •74LVTH244Absolute Maximum Ratings (Note 1)Recommended Operating ConditionsNote 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 2: I O Absolute Maximum Rating must be observed.Symbol ParameterValue ConditionsUnits V CC Supply Voltage −0.5 to +4.6V V I DC Input Voltage −0.5 to +7.0V V O DC Output Voltage −0.5 to +7.0Output in 3-STATEV −0.5 to +7.0Output in HIGH or LOW State (Note 2)V I IK DC Input Diode Current −50V I < GND mA I OK DC Output Diode Current −50V O < GND mA I O DC Output Current64V O > V CC Output at HIGH State mA 128V O > V CCOutput at LOW State I CC DC Supply Current per Supply Pin ±64mA I GND DC Ground Current per Ground Pin ±128mA T STGStorage Temperature−65 to +150°CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current −32mA I OL LOW-Level Output Current 64T A Free-Air Operating Temperature−4085°C ∆t/∆VInput Edge Rate, V IN = 0.8V–2.0V, V CC = 3.0V10ns/V 474L V T 244 •74L V T H 244DC Electrical CharacteristicsNote 3: All typical values are at V CC = 3.3V, T A = 25°C.Note 4: Applies to bushold versions only (74LVTH244).Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 8)Note 8: Characterized in SOIC package. Guaranteed parameter, but not tested.Note 9: Max number of outputs defined as (n). n −1 data inputs are driven 0V to 3V. Output under test held LOW.Symbol ParameterV CC (V)T A =−40°C to +85°C UnitsConditionsMinTyp Max(Note 3)V IK Input Clamp Diode Voltage 2.7−1.2V I I = −18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O ≤ 0.1V or V IL Input LOW Voltage 2.7–3.60.8V O ≥ V CC − 0.1V V OHOutput HIGH Voltage2.7–3.6V CC −0.2V I OH = −100 µA 2.7 2.4V I OH = −8 mA 3.02.0V I OH = −32 mA V OLOutput LOW Voltage2.70.2V I OL = 100 µA 2.70.5V I OL = 24 mA3.00.4V I OL = 16 mA 3.00.5V I OL = 32 mA 3.00.55V I OL = 64 mA I I(HOLD)Bushold Input Minimum Drive 3.075µA V I = 0.8V (Note 4)−75µA V I = 2.0V I I(OD)Bushold Input Over-Drive Current to Change State 3.0500µA (Note 5)(Note 4)−500µA (Note 6)I IInput Current3.610µA V I = 5.5V Control Pins 3.6±1µA V I = 0V or V CC Data Pins3.6−5µA V I = 0V 1µA V I = V CCI OFF Power Off Leakage Current 0±100µA 0V ≤ V I or V O ≤ 5.5V I PU/PD Power up/down 3-STATE 0–1.5V ±100µA V O = 0.5V to 3.0V Output CurrentV I = GND or V CC I OZL 3-STATE Output Leakage Current 3.6−5µA V O = 0.5V I OZH 3-STATE Output Leakage Current 3.65µA V O = 3.0V I OZH +3-STATE Output Leakage Current 3.610µA V CC < V O ≤ 5.5V I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ +Power Supply Current3.60.19mA V CC ≤ V O ≤ 5.5V,Outputs Disabled ∆I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC − 0.6V (Note 7)Other Inputs at V CC or GNDSymbol ParameterV CC (V)T A = 25°CUnits ConditionsC L = 50 pF, R L = 500ΩMinTyp MaxV OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 9)V OLVQuiet Output Minimum Dynamic V OL3.3−0.8V(Note 9)74LVT244 •74LVTH244AC Electrical CharacteristicsNote 10: All typical values are at V CC = 3.3V, T A = 25°C.Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design.Capacitance (Note 12)Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.SymbolParameterT A = −40°C to +85°C C L = 50 pF, R L = 500ΩUnitsV CC = 3.3V ± 0.3VV CC = 2.7V MinTyp MaxMinMax(Note 10)t PLH Propagation Delay Data to Output1.1 3.8 1.1 4.0ns t PHL 1.3 3.9 1.3 4.2t PZH Output Enable Time1.1 4.5 1.1 5.3ns t PZL 1.4 4.4 1.4 5.0t PHZ Output Disable Time 1.9 4.9 1.9 5.1ns t PLZ 1.84.4 1.84.4t OSHL Output to Output Skew 1.01.0nst OSLH(Note 11)Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC = 0V, V I = 0V or V CC 3pF C OUTOutput CapacitanceV CC = 3.0V, V O = 0V or V CC6pF 674L V T 244 •74L V T H 244Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 WidePackage Number M20B20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D•74LVTH244874L V T 244 •74L V T H 244 L o w V o l t a g e O c t a l B u f f e r /L i n e D r i v e r w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm WidePackage Number MSA20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

O CTAL 3-S TATE N ONINVERTINGB UFFER/L INE D RIVER/L INE R ECEIVERHigh-Speed Silicon-Gate CMOS The IN74ACT244 is identical in pinout to the LS/ALS244, HC/HCT244. The IN74ACT244 may be used as a level converterfor interfacing TTL or NMOS outputs to High Speed CMOSinputs.designed to be used with 3-state memory address drivers, clocknoninverting outputs and two active-low output enables.•TTL/NMOS Compatible Input Levels•Outputs Directly Interface to CMOS, NMOS, and TTL•Operating Voltage Range: 4.5 to 5.5 V •Low Input Current: 1.0 µA; 0.1 µA @ 25°C •Outputs Source/Sink 24 mAORDERING INFORMATIONIN74ACT244N PlasticIN74ACT244DW SOICT A = -40° to 85° C for allpackagesFUNCTION TABLEInputs Outputs Enable A,Enable BA,B YA,YBL L LL H HH X ZX=don’t careZ = high impedanceLOGIC DIAGRAMPIN 20=V CCPIN 10 = GNDPIN ASSIGNMENTMAXIMUM RATINGS*Symbol Parameter ValueUnit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 VV IN DC Input Voltage (Referenced to GND) -0.5 to V CC +0.5 VV OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 VI IN DC Input Current, per Pin ±20 mAI OUT DC Output Sink/Source Current, per Pin ±50 mAI CC DC Supply Current, V CC and GND Pins ±50 mAP D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750500mWTstg Storage Temperature -65 to +150 °CT L Lead Temperature, 1 mm from Case for 10Seconds(Plastic DIP or SOIC Package)260 °C*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°CSOIC Package: - 7 mW/°C from 65° to 125°CRECOMMENDED OPERATING CONDITIONSSymbol Parameter MinMaxUnit V CC DC Supply Voltage (Referenced to GND) 4.5 5.5 VV IN, V OUT DC Input Voltage, Output Voltage (Referenced toGND)0 V CC VT J Junction Temperature (PDIP) 140 °CT A Operating Temperature, All Package Types -40 +85 °CI OH Output Current - High -24 mAI OL Output Current - Low 24 mAt r, t f Input Rise and Fall Time * (except Schmitt Inputs) V CC=4.5 VV CC =5.5 V108.0ns/V* VINfrom 0.8 V to 2.0 VThis device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)V CC Guaranteed LimitsSymbol Parameter Test Conditions V 25 °C -40°C to85°CUnit V IH Minimum High-Level Input VoltageV OUT = V CC -0.1 V 4.5 5.5 2.0 2.0 2.0 2.0 VV IL Maximum Low -Level Input VoltageV OUT =0.1 V 4.5 5.5 0.8 0.8 0.8 0.8 VV OH Minimum High-Level Output VoltageI OUT ≤ -50 µA 4.5 5.5 4.4 5.4 4.4 5.4 V*V IN =V IHI OH =-24 mAI OH =-24 mA4.55.5 3.86 4.86 3.76 4.76 V OL Maximum Low-Level Output VoltageI OUT ≤ 50 µA 4.5 5.5 0.1 0.1 0.1 0.1 V*V IN =V ILI OL =24 mAI OL =24 mA4.55.5 0.36 0.36 0.44 0.44 I IN Maximum Input Leakage CurrentV IN =V CC or GND 5.5 ±0.1 ±1.0 µAI OZ Maximum Three-State Leakage Current V IN (OE)=V IL or V IH V IN =V CC or GND V OUT =V CC or GND5.5 ±0.5 ±5.0 µA∆I CCT Additional MaxI CC /InputV IN =V CC - 2.1 V 5.5 1.5 mA I OLD +Minimum Dynamic Output CurrentV OLD =1.65 V Max 5.5 75 mAI OHD +Minimum Dynamic Output CurrentV OHD =3.85 V Min 5.5 -75 mAI CC Maximum Quiescent Supply Current(per Package)V IN =V CC or GND 5.5 8.0 80 µAAll outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time.AC ELECTRICAL CHARACTERISTICS(V CC=5.0 V ± 10%, C L=50pF,Input t r=t f=3.0 ns)LimitsGuaranteedUnitSymbol Parameter 25 °C -40°C to85°CMax MinMaxMin t PLH Propagation Delay, A to YA or B to YB2.0 9.0 1.5 10.0 ns(Figure 1)2.0 9.0 1.5 10.0 nst PHL Propagation Delay, A to YA or B to YB(Figure 1)1.5 8.5 1.0 9.5 nst PZH Propagation Delay, Output Enable to YAor YB (Figure 2)t PZL Propagation Delay, Output Enable to YA2.0 9.5 1.5 10.5 nsor YB (Figure 2)2.0 9.5 1.5 10.5 nst PHZ Propagation Delay, Output Enable to YAor YB (Figure 2)2.5 10.0 2.0 10.5 nst PLZ Propagation Delay, Output Enable to YAor YB (Figure 2)C IN Maximum Input Capacitance 4.5 4.5 pFTypical @25°C,V CC=5.0VC PD Power Dissipation Capacitance 45 pFFigure 1. Switching Waveforms Figure 2. Switching Waveforms。

© 2005 Fairchild Semiconductor Corporation DS011522November 1992Revised April 200574VHC244 Octal Buffer/Line Driver with 3-STATE Outputs74VHC244Octal Buffer/Line Driver with 3-STATE OutputsGeneral DescriptionThe VHC244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissi-pation. The VHC244 is a non-inverting 3-STATE buffer hav-ing two active-LOW output enables. These devices are designed to be used as 3-STATE memory address drivers,clock drivers, and bus oriented transmitter/receivers.An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt-age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir-cuit prevents device destruction due to mismatched supply and input voltages.Featuress High Speed: t PD 3.9ns (typ) at V CC 5V s High noise immunity: V NIH V NIL 28% V CC (min)s Power down protection is provided on all inputs s Low noise: V OLP 0.6V (typ)s Low power dissipation: I CC 4 P A (max) @ T A 25q C s Pin and function compatible with 74HC244Ordering Code:Surface mount packages are also available on T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.Pb-Free package per JEDEC J-STD-020B.Logic SymbolIEEE/IECConnection DiagramOrder Number Package NumberPackage Description74VHC244M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74VHC244SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74VHC244MTC MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC244NN20A20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 274V H C 244Pin DescriptionsTruth TablesH HIGH Voltage Level L LOW Voltage Level I ImmaterialZ High ImpedancePin NamesDescriptionOE 1, OE 23-STATE Output Enable Inputs I 0–I 7InputsO 0–O 73-STATE OutputsInputsOutputsOE 1I n (Pins 12, 14, 16, 18)L L L L H H HXZ InputsOutputsOE 2I n (Pins 3, 5, 7, 9)L L L L H H HXZ74VHC244Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 2)Note 1: Absolute Maximum Ratings are values beyond which the devicemay be damaged or have its useful life impaired. The databook specifica-tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari-ables. Fairchild does not recommend operation outside databook specifica-tions.Note 2: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsNoise CharacteristicsNote 3: Parameter guaranteed by design.Supply Voltage (V CC ) 0.5V to 7.0V DC Input Voltage (V IN ) 0.5V to 7.0V DC Output Voltage (V OUT ) 0.5V to V CC 0.5VInput Diode Current (I IK ) 20 mA Output Diode Current (I OK )r 20 mA DC Output Current (I OUT )r 25 mA DC V CC /GND Current (I CC )r 75 mAStorage Temperature (T STG ) 65q C to 150q CLead Temperature (T L )(Soldering, 10 seconds)260q CSupply Voltage (V CC ) 2.0V to 5.5VInput Voltage (V IN )0V to 5.5VOutput Voltage (V OUT )0V to V CCOperating Temperature (T OPR ) 40q C to 85q C Input Rise and Fall Time (t r , t f )V CC 3.3V r 0.3V 0 ns/V a 100 ns/V V CC 5.0V r 0.5V0 ns/V a 20 ns/VSymbol ParameterV CC T A 25q C T A 40q C to 85q C Units Conditions(V)Min TypMaxMin MaxV IH HIGH Level 2.0 1.5 1.5V Input Voltage 3.0 5.50.7 V CC0.7 V CCV IL LOW Level 2.00.50.5VInput Voltage 3.0 5.50.3 V CC0.3 V CC V OHHIGH Level 2.0 1.9 2.0 1.9V IN V IH I OH 50 P AOutput Voltage3.0 2.9 3.0 2.9Vor V IL4.5 4.4 4.54.43.0 2.58 2.48VI OH 4 mA 4.53.943.80I OH 8 mAV OLLOW Level 2.00.00.10.1V IN V IH I OL 50 P AOutput Voltage3.00.00.10.1V or V IL4.50.00.10.13.00.360.44V I OL 4 mA 4.50.360.44I OL 8 mAI OZ 3-STATE Output 5.5r 0.25r 2.5P AV IN V IH or V IL Off-State Current V OUT V CC or GND I IN Input Leakage Current 0 5.5r 0.1r 1.0P A V IN 5.5V or GND I CCQuiescent Supply Current5.54.040.0P AV IN V CC or GND Symbol ParameterV CC T A 25q C Units Conditions(V)Typ Limits V OLP Quiet Output Maximum 5.00.60.9VC L 50 pF(Note 3)Dynamic V OLV OLV Quiet Output Minimum 5.00.60.9VC L 50 pF(Note 3)Dynamic V OLV IHD Minimum HIGH Level 5.03.5VC L 50 pF(Note 3)Dynamic Input Voltage V ILD Maximum HIGH Level 5.01.5VC L 50 pF(Note 3)Dynamic Input Voltage 474V H C 244AC Electrical CharacteristicsNote 4: Parameter guaranteed by design. t OSLH |t PLHmax t PLHmin |; t OSHL |t PHLmax t PHLmin |.Note 5: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (OPR.) C PD * V CC * f IN I CC /8 (per bit).Symbol ParameterV CC T A 25q C T A 40q C to 85q C Units Conditions(V)MinTyp Max Min Max t PLH Propagation Delay 3.3 r 0.35.88.4 1.010.0ns C L 15 pF t PHLTime8.311.9 1.013.5C L 50 pF 5.0 r 0.53.9 5.5 1.0 6.5ns C L 15 pF 5.47.5 1.08.5C L 50 pF t PZL 3-STATE Output 3.3 r 0.3 6.610.6 1.012.5nsR L 1 k :C L 15 pF t PZHEnable Time9.114.1 1.016.0C L 50 pF 5.0 r 0.54.77.3 1.08.5ns C L 15 pF 6.29.3 1.010.5C L 50 pF t PLZ 3-STATE Output 3.3 r 0.310.314.0 1.016.0ns R L 1 k :C L 50 pF t PHZ Disable Time5.0 r 0.56.79.2 1.010.5C L 50 pF t OSLH Output to Output 3.3 r 0.3 1.5 1.5ns (Note 4)C L 50 pF t OSHL Skew5.0 r 0.51.0 1.0C L 50 pFC IN Input Capacitance 41010pF V CC Open C OUT Output Capacitance6pF V CC 5.0V C PDPower Dissipation Capacitance19pF(Note 5)74VHC244Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 674V H C 244Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 74VHC244Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20874V H C 244 O c t a l B u f f e r /L i n e D r i v e r w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N20AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。