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CY7C1487V33-133BGXC中文资料

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72-Mbit (2M x 36/4M x 18/1M x 72)Flow-Through SRAMCY7C1483V33CY7C1487V33Features•Supports 133 MHz bus operations •2M x 36/4M x 18/1M x 72 common IO •3.3V core power supply (V DD )•2.5V or 3.3V I/O supply (V DDQ )•Fast clock-to-output times—6.5 ns (133 MHz version)•Provide high-performance 2-1-1-1 access rate•User selectable burst counter supporting Intel ® Pentium ® interleaved or linear burst sequences•Separate processor and controller address strobes •Synchronous self timed write •Asynchronous output enable•CY7C1481V33, CY7C1483V33 available inJEDEC-standard Pb-free 100-pin TQFP , Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V33 available in Pb-free and non-Pb-free 209 ball FBGA package•IEEE 1149.1 JTAG-Compatible Boundary Scan •“ZZ” Sleep Mode optionFunctional Description [1]The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V,2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE 1), depth-expansion Chip Enables (CE 2 and CE 3), Burst Control inputs (ADSC, ADSP , and ADV), Write Enables (BW x and BWE), and Global Write (GW).Asynchronous inputs include the Output Enable (OE) and the ZZ pin.The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC)inputs. Address advancement is controlled by the Address Advancement (ADV) input.Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC ) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.Selection Guide133 MHz100 MHz Unit Maximum Access Time 6.58.5ns Maximum Operating Current 335305mA Maximum CMOS Standby Current150150mANote1.For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines .CY7C1487V33 Logic Block Diagram – CY7C1481V33 (2M x 36)CY7C1487V33 Logic Block Diagram – CY7C1487V33 (1M x 72)CY7C1487V33Pin ConfigurationsA A A A A 1A 0A A V S SV D DA A A A A A A ADQP B DQ B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP ADQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SSQ DQ D DQ D DQ D DQ D V SSQ V DDQ DQ D DQ D DQP DA A C E 1C E 2B W DB W CB W BB W AC E 3V D DV S SC L K G W B W E O E AD S C A D S P A D V A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281M O D E CY7C1481V33(2Mx 36)NC A A A A A 1A 0A A V S SV D DA A A A A A A AA NC NC V DDQ V SSQ NC DQP A DQ A DQ A V SSQ V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SSQ DQ A DQ A NC NC V SSQ V DDQ NC NC NCNC NC NC V DDQ V SSQ NC NC DQ B DQ B V SSQ V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SSQ DQ B DQ B DQP BNC V SSQ V DDQ NC NC NCA A C E 1C E 2N C N C B W BB W AC E 3V D DV S SC L K G W B W E O E AD S C A D S P A D V A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281M O D E CY7C1483V33(4M x 18)NC A A 100-Pin TQFP PinoutCY7C1487V33Pin Configurations (continued)165-Ball FBGA (15 x 17 x 1.4 mm) PinoutCY7C1481V33 (2M x 36)CY7C1483V33 (4M x 18)2345671A B C D E F G H J K L M N P RTDO NC/288M NC/144M DQP C DQ C DQP D NC DQ D CE 1BW B CE 3BW C BWE A CE 2DQ C DQ D DQ D MODENC DQ C DQ C DQ D DQ D DQ D A AV DDQ BW D BW A CLKGWV SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKV SS TDI AA DQ C V SS DQ C V SS DQ C DQ C NC V SS V SS V SS V SS NC V SS A1DQ D DQ D NC NC V DDQ V SS TMS891011A ADV A ADSC NC OEADSP A NC/576M V SS V DDQ NC/1G DQP B V DDQ V DD DQ B DQ B DQ B NC DQ B NC DQ A DQ A V DD V DDQ V DD V DDQ DQ B V DD NC V DD DQ A V DD V DDQ DQ A V DDQ V DD V DD V DDQ V DD V DDQ DQ A V DDQ AAV SS AAADQ B DQ B DQ B ZZ DQ A DQ A DQP A DQ A A V DDQ AA0A V SS A2345671A B C D E F G H J K L M N P RTDO NC/288M NC/144M NC NC DQP B NC DQ B A CE 1NC CE 3BW B BWE A CE 2NC DQ B DQ B MODENC DQ B DQ B NC NC NC A AV DDQ NC BW A CLKGWV SS V SS V SS V SS V DDQ V SS V DD V SS V SS V SS V SS V SS V SS V SS V DDQ V DDQ NC V DDQ V DDQ V DDQ V DDQ A AV DD V SS V DD V SS V SS V DDQ V DD V SS V DD V SS V DD V SS V SS V SS V DD V DD V SS V DD V SS V SS NC TCKA0V SS TDIAA DQB V SS NC V SS DQ B NC NC V SS V SS V SS V SS NC V SS A1DQ B NC NC NC V DDQ V SS TMS891011A ADV A ADSC A OEADSP A NC/576M V SS V DDQ NC/1G DQP A V DDQ V DD NC DQ A DQ A NC NC NC DQ A NC V DD V DDQ V DD V DDQ DQ A V DD NC V DD NC V DD V DDQ DQ A V DDQ V DD V DD V DDQ V DD V DDQ NC V DDQ AAV SS AAADQ A NC NC ZZ DQ A NC NC DQ A A V DDQ AACY7C1487V33 Pin Configurations (continued)CY7C1487V33 (1M × 72)A B C D E F G H J K L M N P R T U V W1234567891110DQ GDQ GDQ GDQ GDQ GDQ GDQ GDQ GDQ CDQ CDQ CDQ CNCDQP GDQ HDQ HDQ HDQ HDQ DDQ DDQ DDQ DDQP DDQP CDQ CDQ CDQ CDQ CNCDQ HDQ HDQ HDQ HDQP HDQ DDQ DDQ DDQ DDQ BDQ BDQ BDQ BDQ BDQ BDQ BDQ BDQ FDQ FDQ FDQ FNCDQP FDQ ADQ ADQ ADQ ADQ EDQ EDQ EDQ EDQP ADQP BDQ FDQ FDQ FDQ FNCDQ ADQ ADQ ADQ ADQP EDQ EDQ EDQ EDQ EA ADSP ADV ANC NCA A A AA A AA A A A1A0A A AA AANC/144MNC/288MNC/576MGW NCNCBWS B BWSFBWS E BWS ABWS C BWS GBWS DBWS HTMS TDI TDO TCKNCNC MODE NCV SS V SSNCCLK NC V SSV DD V DD V DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV SS V SSV SSV SSV SSV SS V SSV SSNC/1GV DDNCOECE3CE1CE2ADSCBWV SSV SSV SSV SS V SS V SS V SSZZV SS V SS V SS V SSNCV DDQV SSV SS NC V SS V SSV SS V SS VSSV SSNCV SSV DDQ V DDQ V DDQ V DDQV DDQ NC V DDQ VDDQV DDQ V DDQ NC V DDQ V DDQV DDQ V DDQ NC V DDQ VDDQV DDQV DDQV DDQ V DDQV DDQ VDDQV DDQ V DDQ209-Ball FBGA (14 x 22 x 1.76 mm) PinoutCY7C1487V33Pin DefinitionsPin Name IO DescriptionA0, A1, A Input-Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, and CE3are sampled active. A[1:0] feed the two-bit counter.BW A,BW B,BW C,BW D, BW E,BW F,BW G,BW HInput-SynchronousByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writesto the SRAM. Sampled on the rising edge of CLK.GW Input-Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW X and BWE).CLK Input-Clock Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation.CE1Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.CE2Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3to select or deselect the device. CE2 is sampled only when a new external address is loaded.CE3Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.OE Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.ADV Input-Synchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle.ADSP Input-Synchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGHADSC Input-Synchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.BWE Input-Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.ZZ Input-Asynchronous ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down.DQ s IO-Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ s and DQP X are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X IO-Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ s. During write sequences, DQP x is controlled by BW X correspondingly.MODE Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tiedto V DD or left floating, selects interleaved burst sequence. This is a strap pin and mustremain static during device operation. Mode Pin has an internal pull up.CY7C1487V33Functional OverviewAll synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device).The CY7C1481V33/CY7C1483V33/CY7C1487V33 supports secondary cache in systems using either a linear or inter-leaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry.Three synchronous Chip Selects (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE 1is HIGH.Single Read AccessesA single read access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE 2, and CE 3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must bedeasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core.If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to t CDV after clock rise. ADSP is ignored if CE 1 is HIGH.Single Write Accesses Initiated by ADSPThis access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE 2, CE 3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW X ) are ignored during this first clock cycle. If the write inputs are asserted active (see “Truth Table for Read/Write” on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are supported. All IOs are tri-stated during a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated before the presentation of data to DQ s . As a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of OE.Single Write Accesses Initiated by ADSCThis write access is initiated when the following conditions are satisfied at clock rise: (1) CE 1, CE 2, and CE 3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX)indicate a write access. ADSC is ignored if ADSP is active LOW.The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ s will be written into the specified address location. Byte writes are supported.V DD Power Supply Power supply inputs to the core of the device . V DDQ IO Power Supply Power supply for the IO circuitry .V SS Ground Ground for the core of the device . V SSQ [2}I/O Ground Ground for the IO circuitry .TDOJTAG Serial Output SynchronousSerial Data-Out to the JTAG Circuit . Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin should be left unconnected. This pin is not available on TQFP packages.TDIJTAG Serial Input Synchronous Serial Data-In to the JTAG Circuit . Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be left floating or connected to V DD through a pull upresistor. This pin is not available on TQFP packages.TMSJTAG Serial Input Synchronous Serial Data-In to the JTAG Circuit . Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to V DD . This pin is notavailable on TQFP packages.TCK JTAG ClockClock Input to the JTAG Circuit . If the JTAG feature is not used, this pin must be connected to V SS . This pin is not available on TQFP packages.NC-No Connects . Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die.Pin Definitions (continued)Pin Name IO DescriptionNote2.Applicable for TQFP package. For BGA package V SS serves as ground for the core and the IO circuitry.CY7C1487V33All IOs are tri-stated when a write is detected, even a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated before the presentation of data to DQ s. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.Burst SequencesThe CY7C1481V33/CY7C1483V33/CY7C1487V33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence.Sleep ModeThe ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep”mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressA1: A0SecondAddressA1: A0ThirdAddressA1: A0FourthAddressA1: A0 00011011010011101011000111100100Linear Burst Address Table(MODE = GND)FirstAddressA1: A0SecondAddressA1: A0ThirdAddressA1: A0FourthAddressA1: A0 00011011011011001011000111000110ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit I DDZZ Sleep mode standby current ZZ > V DD– 0.2V150mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsCY7C1487V33 Truth TableThe truth table for CY7C1481V33, CY7C1483V33, and CY7C1487V33 follows.[3, 4, 5, 6, 7]Cycle Description ADDRESSUsed CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle,None H X X L X L X X X L-H Tri-State Power DownNone L L X L L X X X X L-H Tri-State Deselected Cycle,Power DownDeselected Cycle,None L X H L L X X X X L-H Tri-State Power DownDeselected Cycle,None L L X L H L X X X L-H Tri-State Power DownDeselected Cycle,None X X X L H L X X X L-H Tri-State Power DownSleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L-H Q Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H DNotes3.X = Do Not Care, H = Logic HIGH, L = Logic LOW.4.WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.5.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.6.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW X. Writes may occur only on subsequent clocks aftercare for the remainder of the write cycle.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE isCY7C1487V33 Truth Table for Read/WriteThe read-write truth table for CY7C1481V33 follows.[3, 8]BW A Function GW BWE BW D BW C BWBRead H H X X X X Read H L H H H H Write Byte A (DQ A, DQP A)H L H H H L Write Byte B(DQ B, DQP B)H L H H L H Write Bytes A, B (DQ A, DQ B, DQP A, DQP B)H L H H L L Write Byte C (DQ C, DQP C)H L H L H H Write Bytes C, A (DQ C, DQ A, DQP C, DQP A)H L H L H L Write Bytes C, B (DQ C, DQ B, DQP C, DQP B)H L H L L H Write Bytes C, B, A (DQ C, DQ B, DQ A, DQP C, DQP B, DQP A)H L H L L L Write Byte D (DQ D, DQP D)H L L H H H Write Bytes D, A (DQ D, DQ A, DQP D, DQP A)H L L H H L Write Bytes D, B (DQ D, DQ A, DQP D, DQP A)H L L H L H Write Bytes D, B, A (DQ D, DQ B, DQ A, DQP D, DQP B, DQP A)H L L H L L Write Bytes D, B (DQ D, DQ B, DQP D, DQP B)H L L L H H Write Bytes D, B, A (DQ D, DQ C, DQ A, DQP D, DQP C, DQP A)H L L L H L Write Bytes D, C, A (DQ D, DQ B, DQ A, DQP D, DQP B, DQP A)H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/WriteThe read-write truth table for CY7C1483V33 follows.[3, 8]Function GW BWE BW B BW ARead H H X XRead H L H HWrite Byte A - (DQ A and DQP A)H L H LWrite Byte B - (DQ B and DQP B)H L L HWrite All Bytes H L L LWrite All Bytes L X X XTruth Table for Read/WriteThe read-write truth table for CY7C1487V33 follows.[3, 8]Function GW BWE BW x[9]Read H H XRead H L All BW = HWrite Byte x – (DQ x and DQP x)H L LWrite All Bytes H L All BW = LWrite All Bytes L X XNotes8.Table only lists a partial listing of the byte write combinations. Any combination of BW X is valid. An appropriate write is performed based on which byte write is active.9.BWx represents any byte write signal BW X.To enable any byte write BW x , a Logic LOW signal must be applied at clock rise. Any number of byte writes can beenabled at the same time for any given write.CY7C1487V33IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1481V33/CY7C1483V33/CY7C1487V33 incorpo-rates a serial boundary scan test access port (TAP). This portoperates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V IO logic levels.The CY7C1481V33/CY7C1483V33/CY7C1487V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (V SS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to V DD through a pull up resistor. TDO must be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. The 0/1 next to each state represents the value of TMS at therising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test Mode Select (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)Performing a TAP ResetTo perform a RESET, force TMS HIGH (V DD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.Instruction RegisterThree-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in the “TAP Controller Block Diagram” on page12. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with theTAP Controller State DiagramTAP Controller Block DiagramCY7C1487V33IDCODE instruction if the controller is placed in a reset state, as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test data path. Bypass RegisterTo save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.Boundary Scan RegisterThe boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register, and the x18 configuration has a 54-bit-long register.The boundary scan register is loaded with the contents of the RAM I/ ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO.Identification (ID) RegisterThe ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Defini-tions” on page15.TAP Instruction SetOverviewEight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below.The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed.Instructions are loaded into the TAP controller during the Shift-IR state, when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.EXTESTEXTEST is a mandatory 1149.1 instruction, which is to be executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODEThe IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state.SAMPLE ZThe SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.SAMPLE/PRELOADSAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible.To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t CS plus t CH).The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.。

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CY7C64713资料

CY7C64713资料



The 8051 microprocessor embedded in the FX1 family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs. 4.2.1 8051 Clock Frequency
24 MHz Ext. XTAL High-performance micro using standard tools with lower-power options
• • • • • • •
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— Supports multiple Ready (RDY) inputs and Control (CTL) outputs Integrated, industry standard 8051 with enhanced features — Up to 48-MHz clock rate — Four clocks per instruction cycle — Two USARTS — Three counter/timers — Expanded interrupt system — Two data pointers 3.3V operation with 5V tolerant inputs Smart SIE Vectored USB interrupts Separate data buffers for the Setup and DATA portions of a CONTROL transfer Integrated I2C controller, runs at 100 or 400 KHz 48-MHz, 24-MHz, or 12-MHz 8051 operation Four integrated FIFOs — Brings glue and FIFOs inside for lower system cost — Automatic conversion to and from 16-bit buses — Master or slave operation — FIFOs can use externally supplied clock or asynchronous strobes — Easy interface to ASIC and DSP ICs Vectored for FIFO and GPIF interrupts Up to 40 general purpose I/Os Three package options—128-pin TQFP, 100-pin TQFP, and 56-pin QFN Lead-free
USB控制芯片cy7c68013中文手册

USB控制芯片cy7c68013中文手册

■ 符合行业标准的集成增强型 8051 ❐ 48 MHz、 24 MHz 或 12 MHz CPU 操作 ❐ 每个指令周期四个时钟 ❐ 两个 USART ❐ 三个计数器/定时器 ❐ 扩展的中断系统 ❐ 两个数据指针
■ 3.3V 工作电压，容限输入为 5V
■ 向量化 USB 中断和 GPIF/FIFO 中断
■ 16 K 字节片上代码/数据 RAM
■ 四个可编程的 BULK/INTERRUPT/ISOCHRONOUS 端点 ❐ 缓冲区大小选项：两倍，三倍，四倍
■ 附加的可编程 (BULK/INTERRUPT) 64 位端点
■ 8 位或 16 位外部数据接口
■ 可生成智能介质标准错误校正码 ECC
■ 通用可编程接口 (General Programmable Interface， GPIF) ❐ 可与大多数并行接口直接连接 ❐ 由可编程波形描述符和配置寄存器定义波形 ❐ 支持多个 Ready (RDY) 输入和 Control (CTL) 输出
4 KB8/16源自FIFO丰富的 I/O 接口包含 两个 USART
通用可编程 I/F 符合 ASIC/DSP 或 总线标准，例如 ATAPI、 EPP 等
高达 96 MB/s 突发速率
增强型 USB 核 简化 8051 代码
“软配置”容易 进行固件更换
FIFO 和端点存储器 （主控端或从属端操作）
1.1 特色 （仅限 CY7C68013A/14A）
片上 PLL 可根据收发器 /PHY 的需要将 24 MHz 振荡器倍频到 480 MHz，而内部计数器可将其分频以用作 8051 时钟。默认的 8051 时钟频率是 12 MHz。 8051 的时钟频率可以由 8051 通过 CPUCS 寄存器动态更改。
CY7C1470V33中文资料

CY7C1470V33中文资料

CONTROL LOGIC
WRITE DRIVERS
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INPUT REGISTER 1 E
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Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices.
CY37384VP44-167BAXC资料

CY37384VP44-167BAXC资料

5V, 3.3V, ISR™ High-Performance CPLDsUltra37000 CPLD FamilyFeatures•In-System Reprogrammable™ (ISR™) CMOS CPLDs —JTAG interface for reconfigurability—Design changes do not cause pinout changes—Design changes do not cause timing changes •High density—32 to 512 macrocells—32 to 264 I/O pins—Five dedicated inputs including four clock pins •Simple timing model—No fanout delays—No expander delays—No dedicated vs. I/O pin delays—No additional delay through PIM—No penalty for using full 16 product terms—No delay for steering or sharing product terms •3.3V and 5V versions•PCI-compatible[1]•Programmable bus-hold capabilities on all I/Os •Intelligent product term allocator provides:—0 to 16 product terms to any macrocell—Product term steering on an individual basis—Product term sharing among local macrocells •Flexible clocking—Four synchronous clocks per device—Product term clocking—Clock polarity control per logic block•Consistent package/pinout offering across all densities —Simplifies design migration—Same pinout for 3.3V and 5.0V devices •Packages—44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages—Lead(Pb)-free packages available General DescriptionThe Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Inter-connect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs.All of the Ultra37000 devices are electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os.Ultra37000 5.0V DevicesThe Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. V CCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the V CCO pins to 5V the user insures 5V TTL levels on the outputs. If V CCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming.Ultra37000V 3.3V DevicesDevices operating with a 3.3V supply require 3.3V on all V CCO pins, reducing the device’s power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming.Note:1.Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V CC, PCI V IH = 2V.Selection Guide5.0V Selection GuideGeneral InformationDevice Macrocells Dedicated Inputs I/O Pins Speed (t PD)Speed(f MAX) CY37032325326200 CY3706464532/646200 CY37128128564/128 6.5167 CY3719219251207.5154 CY372562565128/160/1927.5154 CY373843845160/19210118 CY375125125160/192/26410118Speed BinsDevice2001671541431251008366 CY37032X X XCY37064X X XCY37128X X XCY37192X X XCY37256 X X XCY37384X XCY37512X X XDevice-Package Offering and I/O CountDevice44-LeadTQFP44-LeadPLCC44-LeadCLCC84-LeadPLCC84-LeadCLCC100-LeadTQFP160-LeadTQFP160-LeadCQFP208-LeadPQFP208-LeadCQFP256-LeadBGA352-LeadBGACY370323737CY370643737376969CY37128696969133CY37192125CY37256133133165197CY37384165197CY37512165165197269 3.3V Selection GuideGeneral InformationDevice Macrocells Dedicated Inputs I/O Pins Speed (t PD)Speed(f MAX) CY37032V325328.5143 CY37064V64532/648.5143 CY37128V128564/80/12810125 CY37192V192512012100 CY37256V2565128/160/19212100 CY37384V3845160/1921583 CY37512V5125160/192/2641583Architecture Overview of Ultra37000 FamilyProgrammable Interconnect MatrixThe PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations.The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family.An important feature of the PIM is its simple timing. The propa-gation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing param-eters on the Ultra37000 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37000 specifications. Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software—no hand routing is necessary. Warp and third-party development packages automatically route designs for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments.Logic BlockThe logic block is the basic building block of the Ultra37000architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram.Product Term ArrayEach logic block features a 72 x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs. Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE)product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block.The other two OE product terms are available to the lower half of the I/O macrocells in a logic block.The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array.Speed BinsDevice 2001671541431251008366CY37032V X X CY37064V XXCY37128V XXCY37192V X X CY37256V XX CY37384V X X CY37512VXXDevice-Package Offering and I/O CountDevice 44-L e a d T Q F P 44-L e a d C L C C 48-L e a d F B G A 84-L e a d C L C C 100-L e a d T Q F P 100-L e a d F B G A 160-L e a d T Q F P 160-L e a d C Q F P 208-L e a d P Q F P 208-L e a d C Q F P 256-L e a d B G A 256-L e a d F B G A 352-L e a d B G A 400-L e a d F B G ACY37032V 3737CY37064V 3737376969CY37128V 696985133CY37192V 125CY37256V 133133165197197CY37384V 165197CY37512V165165197269269Low-Power OptionEach logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conser-vation. The logic block mode is set by the user on a logic block by logic block basis. Product Term AllocatorThrough the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting perfor-mance: product term steering and product term sharing. Product Term SteeringProduct term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will “steer” ten product terms to one macrocell and three to the other. On Ultra37000 devices,product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register. Product Term SharingProduct term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in avariable fashion. The software automatically takes advantage of this capability—the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worst-case steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000devices.Ultra37000 MacrocellWithin each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device.Buried MacrocellFigure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features program-mable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression.Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features program-mable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.Figure 1. Logic Block with 50% Buried MacrocellsI/O CELL 0PRODUCT TERM ALLOCATORI/O CELL 14MACRO-CELL 0MACRO-CELL 1MACRO-CELL 140−16PRODUCT TERMS72x 87PRODUCT TERMARRAY8036816TO PIMFROM PIM732MACRO-CELL 152to cells2, 4, 6 8, 10, 120−16PRODUCT TERMS0−16PRODUCT TERMS0−16PRODUCT TERMSThe buried macrocell also supports input register capability.The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration. I/O MacrocellFigure 2 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many appli-cations.The Ultra37000 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input.Bus Hold Capabilities on all I/OsBus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board,which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connec-tions to V CC or GND. For more information, see the application note Understanding Bus-Hold—A Feature of Cypress CPLDs .Programmable Slew Rate ControlEach output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high perfor-mance the fast edge rate provides maximum system perfor-mance.C2C3DECODE C2C3DECODE 0123OC6C5“0” “1”1OD/T/LQRP 0123OC001OC4FEEDBACK TO PIM FEEDBACK TO PIMBLOCK RESET0−16TERMSI/O MACROCELLI/O CELLFROM PTM1OD/T/LQRP FROM PTM 1OC7FEEDBACK TO PIMBURIED MACROCELLASYNCHRONOUS PRODUCT 0−16TERMSPRODUCT C140123Q4C24C0C1C24C25C254 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)1 ASYNCHRONOUS CLOCK(PTCLK)BLOCK PRESETASYNCHRONOUSFASTSLOWC26SLEW011011OE0OE1Figure 2. I/O and Buried MacrocellsClockin gEach I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks.Dedicated Inputs/ClocksFive pins on each member of the Ultra37000 family are desig-nated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins.Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered,double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control.Figure 4 illustrates the architecture for the input/clock pins.Like the input pins, input/clock pins can be combinatorial,registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity. Product Term ClockingIn addition to the four synchronous clocks, the Ultra37000family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.Timing ModelOne of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input set-up time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used.The Ultra37000 features:•No fanout delays •No expander delays•No dedicated vs. I/O pin delays •No additional delay through PIM •No penalty for using 0–16 product terms •No added delay for steering product terms •No added delay for sharing product terms •No routing delays •No output bypass delaysThe simple timing model of the Ultra37000 family eliminates unexpected performance penalties.Figure 4. Input/Clock MacrocellFigure 3. Input Macrocell0123OC10C11TO PIMDQDQD QLEINPUT/CLOCK PIN012OFROM CLOCK CLOCK PINS01OC12TO CLOCK MUX ONALL INPUT MACROCELLSTO CLOCK MUX IN EACH301CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUTPOLARITY INPUTLOGIC BLOCKC8C9C13,C14,C15OR C16O 0123O C12C13TO PIMDQDQD QLEINPUT PIN012OC10FROM CLOCK POLARITY MUXES3C11JTAG and PCI StandardsPCI Compliance5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37000 family’s simple and predictable timing model ensures compliance with the PCI AC specifica-tions independent of the design. IEEE 1149.1-compliant JTAGThe Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR.Boundary ScanThe Ultra37000 family supports Bypass, Sample/Preload,Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6.In-System Reprogramming (ISR)In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins.The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routingresources for pinout flexibility, and a simple timing model for consistent system performance.Development Software SupportWarpWarp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones pre-optimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis. Warp Professional ™Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes.Warp Enterprise ™Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches.Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC , Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress’s web site ().Third-Party SoftwareAlthough Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors.ProgrammingThere are four programming options available for Ultra37000devices. The first method is to use a PC with the 37000UltraISR programming cable and software. With this method,the ISR pins of the Ultra37000 devices are routed to a connector at the edge of the printed circuit board. The 37000UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configu-ration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions.For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i).The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information.Figure 5. Timing Model for CY37128Figure 6. JTAG InterfaceCOMBINATORIAL SIGNALREGISTERED SIGNALD,T,LOCLOCKINPUTINPUTOUTPUTOUTPUTt S = 3.5 nst CO = 4.5 nst PD = 6.5 ns Instruction RegisterBoundary Scan idcode Usercode ISR Prog.Bypass Reg.Data RegistersJTAG TAPCONTROLLERTDOTDITMS TCKThe third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of Ultra37000 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option.The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program F LASH370i devices.For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY3700i).Third-Party ProgrammersAs with development software, Cypress support is available on a wide variety of third-party programmers. All major third-party programmers (including BP Micro, Data I/O, and SMS) support the Ultra37000 family.Logic Block DiagramsCY37032/CY37032VLOGIC BLOCK B LOGIC BLOCK A36163616Input Clock/Input 16 I/Os16 I/OsI/O 0−I/O 15I/O 16−I/O 314441616TDI TCK TMSTDOJTAG Tap Controller1PIMJTAG ENLOGIC BLOCK D LOGIC BLOCK CLOGIC BLOCK A LOGIC BLOCK B3616361636163616InputClock/Input16 I/Os16 I/Os16 I/Os16 I/OsI/O 0-I/O 15I/O 16-I/O 31I/O 48-I/O 63I/O 32-I/O 474443232TDI TCK TMSTDOJTAG Tap Controller1PIMCY37064/CY37064V (100-Lead TQFP)Logic Block Diagrams (continued)TDITCK TMSTDOJTAG Tap ControllerCY37128/CY37128V (160-lead TQFP)PIMINPUTMACROCELL CLOCKINPUTS 4436161636LOGIC BLOCK3616163616 I/Os3636361616361616646441INPUT/CLOCK MACROCELLSI/O 0–I/O 15AINPUTS LOGIC BLOCKCLOGIC BLOCKBLOGIC BLOCKDLOGIC BLOCKHLOGIC BLOCKGLOGIC BLOCKFLOGIC BLOCKEI/O 16–I/O 31I/O 32–I/O 47I/O 28–I/O 63I/O 112–I/O 127I/O 96–I/O 111I/O 80–I/O 95I/O 64–I/O 7916 I/Os16 I/Os16 I/Os16 I/Os16 I/Os16 I/Os16 I/OsJTAG ENLOGIC BLOCK H LOGIC BLOCK L LOGIC BLOCKI LOGIC BLOCK J LOGIC BLOCK K LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK G LOGIC BLOCK F361636163616361636163616361636163616361636163616PIMInput Clock/Input 10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/Os10 I/OsI/O 0–I/O 9I/O 10–I/O 19I/O 20–I/O 29I/O 30–I/O 39I/O 40–I/O 49I/O 50–I/O 59I/O 110–I/O 119I/O 100–I/O 109I/O 90–I/O 99I/O 80–I/O 89I/O 70–I/O 79I/O 60–I/O 694446060TDI TCK TMSTDOJTAG Tap Controller1CY37192/CY37192V (160-lead TQFP)Logic Block Diagrams (continued)CY37256/CY37256V (256-lead BGA)LOGIC BLOCK G LOGIC BLOCK HLOGIC BLOCKI LOGIC BLOCK J LOGIC BLOCK L LOGIC BLOCK P LOGIC BLOCK M LOGIC BLOCK N LOGIC BLOCK O LOGIC BLOCK A LOGIC BLOCK B LOGIC BLOCK C LOGIC BLOCK D LOGIC BLOCK E LOGIC BLOCK K LOGIC BLOCK F 3616361636163616361636163616361636163616361636163616361636163616PIMInput Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 36−I/O 47I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 84−I/O 95I/O 180−I/O 191I/O 168−I/O 179I/O 156−I/O 167I/O 144−I/O 155I/O 132−I/O 143I/O 120−I/O 131I/O 108−I/O 119I/O 96−I/O 1074449696TDI TCK TMSTDOJTAG Tap Controller1Logic Block Diagrams (continued)CY37384/CY37384V (256-Lead BGA)LOGIC BLOCK AH LOGIC BLOCK AI LOGIC BLOCK BD LOGIC BLOCK BE LOGIC BLOCK BG LOGIC BLOCK BL LOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BK LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK ADLOGIC BLOCK AFLOGIC BLOCK BF LOGIC BLOCK AG 3616361636163616361636163616361636163616361636163616361636163616PIMInput Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 168−I/O 191I/O 156−I/O 179I/O 144−I/O 167I/O 120−I/O 143I/O 108−I/O 1314449696TDI TCK TMSTDOJTAG Tap Controller1LOGIC BLOCK AJLOGIC BLOCK BC 161612 I/OsI/O 96−I/O 119LOGIC BLOCK AK LOGIC BLOCK BB 161612 I/OsI/O 84−I/O 95LOGIC BLOCK ALLOGIC BLOCK BA161612 I/OsI/O 96−I/O 107LOGIC BLOCK AE LOGIC BLOCK BH 161612 I/Os12 I/OsI/O 36−I/O 47I/O 132−I/O 1553636363636363636Logic Block Diagrams (continued)CY37512/CY37512V (352-Lead BGA)LOGIC BLOCK AG LOGIC BLOCK AHLOGIC BLOCK BI LOGIC BLOCK BJ LOGIC BLOCK BL LOGIC BLOCK BP LOGIC BLOCK BM LOGIC BLOCK BN LOGIC BLOCK BO LOGIC BLOCK AA LOGIC BLOCK AB LOGIC BLOCK AC LOGIC BLOCK ADLOGIC BLOCK AE LOGIC BLOCK BK LOGIC BLOCK AF361636163616361636163616361636363616361636163616361636163616Input Clock/Input 12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/Os12 I/OsI/O 0−I/O 11I/O 12−I/O 23I/O 24−I/O 35I/O 36−I/O 47I/O 48−I/O 59I/O 60−I/O 71I/O 72−I/O 83I/O 84−I/O 95I/O 252−I/O 263I/O 240−I/O 251I/O 228−I/O 239I/O 216−I/O 227I/O 204−I/O 215444TDI TCK TMSTDOJTAG T ap Controller1PIM16363616LOGIC BLOCK AI LOGIC BLOCK BH 12 I/OsI/O 96−I/O 10716363616LOGIC BLOCK AJLOGIC BLOCK BG 12 I/Os12 I/OsI/O 108−I/O 119I/O 192−I/O 20316363616LOGIC BLOCK AK LOGIC BLOCK BF 12 I/OsI/O 120−I/O 13116363616LOGIC BLOCK AL LOGIC BLOCK BE 12 I/OsI/O 180−I/O 19116363616LOGIC BLOCK AM LOGIC BLOCK BD 12 I/OsI/O 168−I/O 17916363616LOGIC BLOCK AN LOGIC BLOCK BC 12 I/OsI/O 156−I/O 16716363616LOGIC BLOCK AO LOGIC BLOCK BB 12 I/OsI/O 144−I/O 155********LOGIC BLOCK AP LOGIC BLOCK BA 12 I/OsI/O 132−I/O 1431613216。