CY7C1350G-250BGXI中文资料

PRELIMINARY18-Mbit (512K x 36/1M x 18) PipelinedSRAM with NoBL™ ArchitectureCY7C1370D CY7C1372DFeatures•Pin-compatible and functionally equivalent to ZBT™ •Supports 250-MHz bus operations with zero wait states —Available speed grades are 250, 225, 200, and 167MHz •Internally self-timed output buffer control to eliminate the need to use asynchronous OE•Fully registered (inputs and outputs) for pipelined operation•Byte Write capability •Single 3.3V power supply •3.3V/2.5V I/O power supply •Fast clock-to-output times —2.6 ns (for 250-MHz device)—2.8 ns (for 225-MHz device)—3.0 ns (for 200-MHz device)—3.4 ns (for 167-MHz device)•Clock Enable (CEN) pin to suspend operation •Synchronous self-timed writes•Available in lead-Free 100 TQFP , 119 BGA, and 165 fBGA packages•IEEE 1149.1 JTAG Boundary Scan•Burst capability—linear or interleaved burst order •“ZZ” Sleep Mode option and Stop Clock optionFunctional DescriptionThe CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and 1Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL ™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal,which when deasserted suspends operation and extends the previous clock cycle.Write operations are controlled by the Byte Write Selects (BW a –BW d for CY7C1370D and BW a –BW b for CY7C1372D)and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.Selection GuideCY7C1370D-250 CY7C1372D-250CY7C1370D-225CY7C1372D-225CY7C1370D-200CY7C1372D-200CY7C1370D-167CY7C1372D-167UnitMaximum Access Time 2.6 2.8 3.0 3.4ns Maximum Operating Current350325300275mA Maximum CMOS Standby Current70707070mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.Pin ConfigurationsA A A A A 1A 0V S SV D DA A A A A AV DDQV SS DQb DQb DQb V SSV DDQDQb DQb V SSNCV DDDQaDQa V DDQV SSDQa DQa V SS V DDQ V DDQV SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A C E 1C E 2B W aC E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZCY7C1370D 100-pin TQFP PackagesA A A A A 1A 0V S SV D DA A A A A AA NC NC V DDQ V SS NC DQPa DQa DQa V SS V DDQ DQa DQa V SS NC V DD DQa DQa V DDQ V SS DQa DQa NC NC V SS V DDQ NC NC NCNC NC NC V DDQ V SSNC NC DQb DQbV SS V DDQ DQb DQbV DD V SS DQb DQbV DDQ V SS DQb DQb DQPbNC V SS V DDQNC NC NCA A C E 1C E 2N C N C B W b B W a C E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZ M O D E CY7C1372DB W d M O D E B W c DQc DQc DQc DQc DQPc DQd DQd DQd DQPbDQbDQa DQaDQa DQaDQPa DQbDQb(512K × 36)(1M × 18)B W b NC NC NC DQc NC E (288)E (144)E (72)E (36)E (288)E (144)E (72)E (36)DQPdA APin Configurations (continued)2345671ABCDEFGHJKLMNP R T UDQ a V DDQNCNCDQ cDQ dDQ cDQ dA A A AA V DDQCE2AV DDQV DDQV DDQV DDQNCNCADQ cDQ cDQ dDQ dTMSV DDAE(72)DQP dAAADV/LD A CE3NCV DD A A NCV SS V SSNC DQP bDQ bDQ bDQ aDQ bDQ bDQ aDQ aNCTDI TDO V DDQTCKV SSV SSV SSNCV SSV SSV SSV SSMODECE1V SSOE V SS V DDQBW c AV SSWEV DDQV DD NC V DDV SSCLKNC BW aCEN V SS V DDQV SSZZNCAAA1A0V SSV DD NCCY7C1370D (512K × 36) – BGADQP c DQ bA E(36)DQ c DQ bDQ cDQ cDQ cDQ bDQ bDQ aDQ aDQ aDQ aDQP aDQ dDQ dDQ dDQ dBW d119-ball BGA PinoutBW b234567 1A B C D E F G H J K L M N P RT UE(36)DQ a V DDQNCNCNCDQ bDQ bDQ bDQ bA A A AA V DDQCE2ANCV DDQNCV DDQV DDQV DDQNCNCNCE(72)ADQ bDQ bDQ bDQ bNCNCNCNCTMSV DDAADQP bAAADV/LD A CE3NCV DD A A NCV SS V SSNC NCDQP aDQ aDQ aDQ aDQ aDQ aDQ aDQ aNCTDI TDO V DDQTCKV SSV SSV SSNCV SSNCV SSV SSV SSMODECE1V SS NCOE V SS V DDQBW b A NC NCV SSWE NCV DDQV DD NC V DDNCV SSCLKNC NCBW aCEN V SS NC V DDQV SS NCZZNCAAAA1A0V SS NCV DD NCCY7C1372D (1M x 18) – BGAPin Configurations (continued)234567 1ABCDEFGHJKLMNP RTDOE(288)NCDQP cDQ cDQP dNCDQ dA CE1BW b CE3BW c CENA CE2DQ cDQ dDQ dMODENCDQ cDQ cDQ dDQ dDQ dE(36)E(72)V DDQBW d BW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ c V SSDQ c V SSDQ cDQ cNCV SSV SSV SSV SSNCV SSA1DQ dDQ dNCNCV DDQV SSTMS891011NCA AADV/LD NCOE A A E(144)V SS V DDQ NC DQP bV DDQV DD DQ bDQ bDQ bNCDQ bNCDQ aDQ aV DD V DDQV DD V DDQ DQ bV DDNCV DDDQ aV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ DQ aV DDQAAV SSAAADQ bDQ bDQ bZZDQ aDQ aDQP aDQ aAV DDQA2345671A B C D E F G H J K L M NP RTDOE(288)NCNCNCDQP bNCDQ bA CE1NC CE3BW b CENA CE2NCDQ bDQ bMODENCDQ bDQ bNCNCNCE(36)E(72)V DDQNC BW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ b V SSNC V SSDQ bNCNCV SSV SSV SSV SSNCV SSA1DQ bNCNCNCV DDQV SSTMS891011NCA AADV/LD AOE A A E(144)V SS V DDQ NC DQP aV DDQV DD NCDQ aDQ aNCNCNCDQ aNCV DD V DDQV DD V DDQ DQ aV DDNCV DDNCV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ NCV DDQAAV SSAAADQ aNCNCZZDQ aNCNCDQ aAV DDQACY7C1372D (1M × 18) – fBGACY7C1370D (512K × 36) – fBGA165-Ball fBGA PinoutPin DefinitionsPin Name I/O Type Pin DescriptionA0 A1 AInput-SynchronousAddress Inputs used to select one of the address locations. Sampled at the rising edge ofthe CLK.BW a BW b BW c BW dInput-SynchronousByte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.Sampled on the rising edge of CLK. BW a controls DQ a and DQP a, BW b controls DQ b and DQP b,BW c controls DQ c and DQP c, BW d controls DQ d and DQP d.WE Input-Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.ADV/LD Input-Synchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.CE1Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.CE2Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE3Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.OE Input-Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.CEN Input-Synchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.DQ S I/O-Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a–DQ d are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X I/O-Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ s. During write sequences, DQP a is controlled by BW a, DQP b is controlled by BW b, DQP c is controlled by BW c, and DQP d is controlled by BW d.MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.Pulled LOW selects the linear burst order. MODE should not change states during operation.When left floating MODE will default HIGH, to an interleaved burst order.TDO JTAG serial outputSynchronousSerial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.TDI JTAG serial inputSynchronousSerial data-In to the JTAG circuit. Sampled on the rising edge of TCK.TMS Test Mode SelectSynchronousThis pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. TCK JTAG-Clock Clock input to the JTAG circuitry.V DD Power Supply Power supply inputs to the core of the device.V DDQ I/O Power Supply Power supply for the I/O circuitry.V SS Ground Ground for the device. Should be connected to ground of the system.IntroductionFunctional OverviewThe CY7C1370D and CY7C1372D are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 2.6 ns (250-MHz device).Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW X can be used to conduct byte write operations.Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.Single Read AccessesA read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.Burst Read AccessesThe CY7C1370D and CY7C1372D have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented suffi-ciently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.Single Write AccessesWrite access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block.On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D & DQ a,b/DQP a,b for CY7C1372D) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete.The data written during the write operation is controlled by BW (BW a,b,c,d for CY7C1370D and BW a,b for CY7C1372D) signals. The CY7C1370D/CY7C1372D provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.Because the CY7C1370D and CY7C1372D are common I/O devices, data should not be driven into the device while theNC–No connects. This pin is not connected to the die.E(36,72, 144, 288)–These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and 288M densities.ZZ Input-Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to V SS or left floating.Pin Definitions (continued)Pin Name I/O Type Pin Descriptionoutputs are active. The Output Enable (OE) can be deassertedHIGH before presenting data to the DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQ a,b,c,d/ DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE.Burst Write AccessesThe CY7C1370D/CY7C1372D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subse-quent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BW a,b,c,d for CY7C1370D and BW a,b for CY7C1372D) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep”mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011010011101011000111100100 Linear Burst Address Table (MODE = GND)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011011011001011000111000110ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min.Max Unit I DDZZ Sleep mode standby current ZZ > V DD − 0.2V80mA t ZZS Device operation to ZZ ZZ > V DD− 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsNotes:1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.2.X . See Write Cycle Description table for details.3.When a write cycle is detected, all I/Os are tri-stated, even during byte writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal.5.6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ s and DQP X is inactive or when the device is deselected, and DQ s = data when OE is active.8.Table only lists a partial listing of the byte write combinations. Any Combination of BW X is valid Appropriate write will be done based on which byte write is active.Truth Table [1, 2, 3, 4, 5, 6, 7]OperationAddress Used CE ZZ ADV/LDWE BW x OE CENCLK DQ Deselect CycleNone H L L X X X L L-H Three-State Continue Deselect Cycle None X L H X X X L L-H Three-State Read Cycle (Begin Burst)External L L L H X L L L-H Data Out (Q)Read Cycle (Continue Burst)Next X L H X X L L L-H Data Out (Q)NOP/Dummy Read (Begin Burst)External L L L H X H L L-H Three-State Dummy Read (Continue Burst)Next X L H X X H L L-H Three-State Write Cycle (Begin Burst)External L L L L L X L L-H Data In (D)Write Cycle (Continue Burst)Next X L H X L X L L-H Data In (D)NOP/Write Abort (Begin Burst)None L L L L H X L L-H Three-State Write Abort (Continue Burst)Next X L H X H X L L-H Three-StateIgnore Clock Edge (Stall)Current X L X X X X H L-H –Sleep ModeNoneXHXXXXX XThree-StateIEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1370D/CY7C1372D incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.The CY7C1370D/CY7C1372D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(V SS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alter-nately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1370D)WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a)L H H H L Write Byte b – (DQ b and DQP b)L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and DQP c)L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQ d and DQP d)L L H H H Write Bytes d, a L L H H L Write Bytes d,b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L LFunction (CY7C1372D)WE BW b BW a Read H x x Write – No Bytes Written L H H Write Byte a – (DQ a and DQP a)L H L Write Byte b – (DQ b and DQP b)L L H Write Both Bytes L L LTAP Controller State DiagramThe 0/1 next to each state represents the value of TMS at the rising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test Mode Select (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most signif-icant bit (MSB) of any register. (See Tap Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)TAP Controller Block DiagramPerforming a TAP ResetA Reset is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.Instruction RegisterThree-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass RegisterTo save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass-register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.Boundary Scan RegisterThe boundary scan register is connected to all the input and bidirectional balls on the SRAM.The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when。

可控硅参数注释范文可控硅（SCR）是一种具有控制能力的半导体器件，它主要用于功率电子应用中的开关和控制。

可控硅的特殊之处在于，一旦启动，它将一直处于导通状态，直到电流降至零或有外部信号来控制其关断。

以下是可控硅的一些重要参数的注释。

1. 负阻抗比例器（Negative Impedance Proportioner，NIP）：负阻抗比例器是此器件的一项重要参数。

它是可控硅的输入特性的度量标准，它表示了控制电压和控制电流之间的关系。

只有当控制电压的变化导致控制电流的相反变化时，负阻抗比例器才被视为合适的。

2. 正向阻抗（Forward Impedance）：正向阻抗是指从可控硅正向电压到正向电流之间的阻抗。

通常使用恒定的电流作为输入，并测量输出的电压。

正向阻抗的数值约低，可控硅的性能越好，因为这意味着它能更好地通过电流。

3. 反向阻抗（Reverse Impedance）：反向阻抗是指从可控硅反向电压到反向电流之间的阻抗。

类似于正向阻抗，较低的数值代表了更好的性能。

反向阻抗通常很高，以防止在正向电压下产生反向电流。

4. 触发电压（Trigger Voltage）：触发电压是指可控硅所需的最低电压，以便使其从关断状态转变为导通状态。

较低的触发电压意味着它更容易被启动，而较高的触发电压可能导致可控硅无法正常启动。

5. 保持电流（Holding Current）：保持电流是可控硅在导通状态下所需的最低电流。

一旦电流低于保持电流，可控硅将自动从导通状态切换到关断状态。

保持电流的数值取决于设备的特性和工作要求。

6. 最大正向电压（Maximum Forward Voltage）：最大正向电压是可控硅所能承受的最大正向电压。

超过这个值，可控硅可能被损坏或无法正常工作。

因此，在设计和使用可控硅时，必须确保正向电压不超过最大正向电压。

7. 极限温度（Junction Temperature Limits）：极限温度是可控硅能够承受的最高温度和最低温度。

PRELIMINARYAX™ A TM-SONET/SDH TransceiverCY7C955Features•WAN and LAN ATM physical layer device•Provides complete physical layer transport of ATM cells at:—STS−3c/ STM−1 rate of 155.52 MHz—STS−1 rate of 51.84 MHz•Compliant with ATM Forum User Network Interface 3.1 specification•UTOPIA ATM interface•ATM cell processing including:—HEC generation/verification—Cell scrambling/descrambling—Rate adaption/idle cell filtering—Local Flow Control—Cell alignment•SONET frame processing including:—Compliant with Bellcore GR−253, I.432,T1.105, and G.709 for Jitter Tolerance and JitterGeneration—Frame generation/recovery—SONET scrambling/descrambling—Frequency justification/pointer processing •Complete line interface including:—Clock and data recovery—Transmit timing derived from receiver or byte-rate source—SONET compliant PLL—100K PECL compatible I/O•Alarm indications including:—Loss Of Signal—Out Of Frame, Loss Of Frame—Line Far End Receive Failure—Line Alarm Indication Signal—B1 Parity Error—Loss Of Cell Alignment—Loss Of Receive Data•Controller interface for internal interrupt andconfiguration registers including:—Error monitoring—Status indication—Device configuration•0.65µ Low Power CMOS•128-pin PQFPFunctional DescriptionThe Cypress Semiconductor CY7C955 is a Transceiver chip designed to carry ATM cells across SONET/SDH systems. On the transmit side, A TM cells coming from the Utopia inter-face are being mapped into SONET/SDH frames and then se-rialized for transmission over fiber or twisted pair (through an optical module or an equalizer chip).On the receive side, serial SONET/SDH datastreams coming from an optical module or an equalizer chip are being recov-ered by the intergrated clock and data recovery phase-locked loop, framed, processed, and presented as parallel A TM cells on the Receive Utopia Interface.The CY7C955 can be used in a Network Interface Card (NIC) design to connect the segmentation and Reassembly (SAR) chip to the optical modules or equalizer chip.The CY7C955 can also be used in work group or enterprise switches to connect the I/O FIFOs of the switch fabric to the optical module or equalizer in the interface boards.The applications of the CY7C955 include adapters, switches, routers, hubs, and proprietary systems.TABLE OF CONTENTSFeatures 1 Functional Description1 Pin Descriptions 2 Pin Configuration7 Description8 Transmit Section8 Receive Section10 Controller Interface (CI) 12 Loopback Operation 16 SONET Overhead Description17 CY7C955 Register Map 18 Electrical Characteristics 60 Capacitance 61 AC T est Loads and Waveforms61 Switching Characteristics61元器件交易网Pin DescriptionsCY7C955 ATM-SONET/SDH Transceiver Switching Waveforms63Functional Timing Diagram69Interface Termination and Biasing Schemes 73Filter Pin Configuration 75Ordering Information 76Package Diagram77TABLE OF CONTENTS (continued)INTB RALMR F PR A T E 1ALE A[7:0]D[7:0]T D A T [7:0]T S O C T F C L K R B Y PR R D E N B R F C L K R S O C R X P R T Y RRCLK±TXD±T X P R T Y Rate SelectionError MonitoringConfiguration and StatusInterfaceController SONET/SDH RecoveryProcessorProcessorProcessor BufferTransmit Multiplier &Clock Transmit ProcessorATM Cell Transmit Transmit TransmitTransmit Transmit UTOPIA I/F Transmit FIFO 4 Cell by 8 bit4 Cell by 8 bitUTOPIA I/F Path Overhead Overhead Overhead Line Section Section Line Overhead Overhead Overhead Path ATM Cell ProcessorProcessor Processor ProcessorReceive Receive Receive Receive Receive Receive FIFO Register FileT B Y P TRCLK±TXC±Clock R A T E 0RXD±RXDO±R C AR C L K T C AT F P OR D A T [7:0]T W R E N B RDB WRB CSB T S E N T C L K R C P R G F CX O F FT G F C T C P RSTB ALOS±7C955−1T ransmit Utopia Interface Name Pin I/O DescriptionTDA T[7:0]87−94Input T ransmit Utopia data: Byte-wide data driven from the A TM to PHY layer. TDAT[7] is the MSB.TPRTY 95Input T ransmit Utopia Data Parity: Data parity calculated over TDAT[7:0]. Odd parity is as-sumed unless the TXPTYP bit (Reg –63, bit 7) is set to even parityTSOC96InputT ransmit Utopia Start of Cell: Assert TSOC HIGH when TDA T[7:0] contains the first byte of an ATM cell. If TSOC is asserted sooner than 53 writes after the previous SOC, an error condition will be generated. This input is optional after the first TSOC pulse.TFCLK 84Input T ransmit Utopia Clock: Data transfer clock. Data is transferred to the AX on the rising edge of TFCLK when TWRENB is asserted (LOW).TWRENB85InputT ransmit Utopia Data Enable: Enables the TFCLK input for data transfer to the AX. This signal is active LOW.TCA86OutputT ransmit Utopia Cell Available: An active state on this signal indicates that the Transmit FIFO can accept at least N more cells (53 octets) of data where N and the active state of the signal (HIGH or LOW) are programmable through the configuration registers (Reg −63H and Reg −01H). In a special case, if Reg –63H bit2−3 is set to 00, Reg −01H, bit 3 is set to 0, and TCALEVEL0 (Reg –63H, bit 1) set to 0. TCA will behave as an active HIGH FULL indicator.T ransmit Utopia Interface (continued)Name Pin I/O DescriptionT ransmit A TM Interface Name Pin I/O DescriptionXOFF50InputT ransmit Idle Cell: A HIGH state on this pin will force the A TM Cell Processor to send an IDLE cell even if there are cells to send in the Transmit FIFO. XOFF is an asynchro-nous input and has an integrated pull down resistor.TGFC 52InputT ransmit Generic Flow Control: This bit serial input provides the ability to overwrite the four bits of the ATM cell header GFC field. These bits may be optionally written during the four TCLK clock periods following the assertion of the TCP output.TCP 51OutputT ransmit Start Of GFC: This indicates that the first bit of the GFC for the next cell read from the T ransmit FIFO is expected on the TGFC pin during the next rising edge of TCLK.T ransmit Clock Generator Name Pin I/ODescriptionTRCLK ±9−10Differential InT ransmit Input Clock: Accepts either a differential PECL, or a TTL or a CMOS byte rate reference connected to TRCLK − with TRCLK+ grounded for the T ransmit frequency multiplier PLL. Optionally, this input can accept also the bit rate reference when TBYP is true (held HIGH). In this mode the T ransmit frequency multiplier is bypassed and the bit rate clock is used directly for transmit side clocking.TXC ±13−14Differential OutT ransmit Output Clock: Provides clock output for the transmit data. TXD ± is updated on the falling edge of this signal. In the default setting, TXC is disabled if RATE0 is HIGH and a 51.84-MHz clock if RA TE0 is LOW. XORTXC (Reg −04H, bit 6) can be used to invert the default setting such that TXC is a 155.52-MHz clock if RA TE0 is HIGH and is disabled when RA TE0 is LOW.TXD ±15−16Differential Out T ransmit Data Output: Accepts NRZ encoded output data. This signal is updated on the falling edge of TXC ±.TBYP2InputT ransmit Clock Bypass: When this input is held HIGH the transmit frequency multiplier is disabled and TRCLK ± input is used directly for transmit side clocking. When this input is held LOW the transmit frequency multiplier multiplies the TRCLK ± input by 8, 24, or 8/3 (depending on the TREFSEL (Reg −06H, bit 0) setting to provide the internal bit rate clock.RATE0RATE197−98InputRATE: When the RA TE0 input is HIGH the Transmit frequency generator and the Re-ceive clock recovery are selected to operate at the STS −3c/STM −1 rate of 155.52 MHz. When the RATE0 pin is LOW, the T ransmit frequency generator and the Receive clock recovery are selected to operate at the STS −1 rate of 51.84 MHz. RA TE1 is for factory testing use only and should be tied HIGH. Both RATE0 and RA TE1 have integrated pull-up resistors.TCLK 54Output T ransmit Byte Reference: Byte rate reference clock derived from the transmit line bit rate.TFPO53OutputT ransmit Frame Reference. This signal is an 8-kHz frame rate reference that goes HIGH during the transmission of the first A1 byte of the SONET/SDH frame. TFPO is updated by the rising edge of TCLK.Receive Clock Recovery Name Pin I/ODescriptionRXD ±25−26Differential InReceive Input Data: These line receiver inputs are connected to an internal Receive PLL that recovers the embedded clock and data information. The incoming data rate can be within one of two frequency ranges depending on the state of the RATE0 pin.RXDO ±22−23Differential OutReceive Output Data: These differential outputs represent the retimed version of the input data stream (RXD ±) in normal mode and the buffered version of the input datas-tream (RXD ±) in bypass mode. This output pair can be used as inputs to decision feedback equalizers to correct for baseline wander. RXDO can be turned off to save power by setting RXDOD (Reg −04H, bit 7) to 1.RRCLK ±33−34Differential InReceive Clock: These inputs are used to clock in the differential data (RXD ±) when the Receive clock recovery block is bypassed (RBYP=HIGH). If RBYP is LOW, RRCLK is multiplied by 8, 24, or 8/3 depending on the setting of RREFSEL (Reg −07H, bit 0) and use as a reference for the Receiver PLL. Refer to the section on “Interface T ermination and Bias of Schemes ” for connection examples to these pins.RBYP 41InputReceive Clock Bypass: When this input is HIGH the Receiver clock recovery block is bypassed. In this mode the device does not recover clock and data from the Receive input data stream (RXD ±) but instead uses the RRCLK ± inputs to clock the differential data into the device. When this input is LOW the Receiver clock recovery block recovers the clock and data from the input data stream. In this mode a byte-rate clock is expected on the RRCLK ± inputs.RCLK 57Output Receive Byte Reference: Provides a byte-rate reference derived from the recovered bit- rate Receive clock. RALM, RCP , and RGFC are aligned with this clock.RFP58OutputReceive Frame Reference: This output provides a frame-rate reference clock aligned to the SONET/SDH frame alignment bytes. RFP will pulse HIGH for one RCLK cycle every 125 seconds even at OOF and LOF situations.LF+42Input NC. This pin is for factory testing only.LF –, LFO43, 44InputThese are the PLL filter pins. Connect a 0.47-µF capacitor across LF – and LFO.Receive Clock Recovery (continued)Name Pin I/ODescriptionReceive A TM Interface Name Pin I/O DescriptionRGFC59OutputReceive Generic Flow Control: This output provides the four bits of the current ATM cell header GFC locations at each successive RCLK pulse. The RCP output indicates the first GFC bit location. This output is forced LOW if the A TM Cell Processor has lost cell delineation.RALM 63Output Receive Interrupt: This active HIGH signal is aligned with the RCLK byte-rate clock and signals the presence of LAIS, P AIS, LOS, LOF , LOP , or LCD.RCP60OutputReceive Start Of GFC: This output indicates the first bit of the GFC presented on the RGFC output. This output goes HIGH for 1 RCLK cycle 6 byte times after the corre-sponding cell is written into the Receive FIFO.Receive Utopia Interface Name Pin No I/O DescriptionRDA T[7:0]70−7174−79Output Receive Utopia Data: Byte-wide data driven from the PHY to ATM layer. RDA T[7] is the MSBRPRTY 82Output Receive Utopia Data Parity: Data parity calculated over RDA T[7:0]. Odd parity is as-sumed unless the TXPRTY bit is set to even parity by Reg −50H, bit 6.RSOC 83Output Receive Utopia Start of Cell: Asserted HIGH when RDA T[7:0] contains the first byte of an ATM cell.RFCLK 67Input Receive Utopia Clock: Data transfer clock. Data is transferred from the AX on the rising edge of RFCLK when RRDENB is asserted (LOW).RRDENB 68Input Receive Utopia Enable: Enables the RFCLK input for data transfers from the AX.RCA69OutputReceive Utopia Cell Available: An active signal indicates that the Receive FIFO con-tains at least 1 or 4 more bytes of data. RCA is controlled by RCAINV (Reg −01H, bit 2) and RCALEVEL0 (Reg −59H, bit 2).TSEN66InputReceive Output Enable: This output operates in conjunction with the RRDENB output. When TSEN is HIGH and RRDENB is HIGH the Receive UTOPIA data bus (RDAT[7:0], RPRTY , and RSOC) is three-stated. When TSEN is HIGH and RRDENB is LOW the data bus is driven with the requested data. When TSEN is LOW the data bus will not three-state.Receive Utopia Interface (continued)Name Pin No I/O DescriptionController Interface Name Pin No I/O DescriptionD[7:0]110−112115−118I/O Data[7:0]: Bidirectional data bus used to transfer data to and from the internal config-uration, status, and error monitoring registers.A[7:0]119−126Input Address[7:0]: Address bus used to select the internal register for reading or writing.ALE127InputAddress Latch Enable: When this input is LOW the address is latched from the A[7:0] inputs. When this input is HIGH, the input is transparent. ALE has an integrated pull- up resistor.RDB 105Input Read: This active LOW signal is used to read the internal register. The AX drives D[7:0] when RDB and CSB are both LOW.WRB 104Input Write: This active LOW signal is used to write the internal registers. Data is latched into the specified address register on the rising edge of WRB when CSB is LOW.CSB 100Input Select: This active LOW device select has to be enabled during register accesses. INTB108OutputInterrupt: This active LOW open drain output transitions LOW when an unmasked interrupt source is active. This output transitions HIGH when the appropriate register has been read. This interrupt signals the most critical error states of the device includ-ing Loss of Pointer, Line Alarm Indication Signal (LAIS), Line Far End Receive Failure (LFERF), Loss of Frame (LOF), Out of Frame (OOF), Loss of Signal (LOS), and many others.ALOS ±27−28Differential InCarrier Detect: This differential input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at a Logic Low, the input data stream (RXD ±) is recovered normally by the Receive Clock Recovery PLL. When this input is at a Logic High, the Receive PLL no longer aligns to RXD ±, but instead aligns with the RRCLK * 8 frequency and the LOS alarm register (RDOOLV) will be set. Besides differential PECL, the ALOS − input can be set to accept single ended PECL input if ALOS+ is tied to GND. ALOS − has to be decoupled.RSTB 101InputReset: This active LOW signal provides a device reset. This line can be pulled LOW to put the CY7C955 into the power-down mode. RSTB has an integrated pull-up resis-tor.VCLK 99InputFactory test pin. Must be LOW for normal operation. VCLK has an integrated pull-down resistor.T ransmit Power Name Pin No I/O DescriptionTXVDD12PowerThe T ransmit Pad Power supplies the TXD ± outputs. TXVDD is physically isolated from the other device power pins and should be well regulated +5V DC and noise-free for good performance when driving category 5 unshielded twist pair cabling.TAVD14Power The power pin for the transmit clock synthesizer reference circuitry. T AVD1 should be connected to analog +5V .TAVD26Power The power pin for the transmit clock synthesizer oscillator. T AVD2 should be connected to analog +5V .TAVD38Power The power pin for the transmit PECL inputs. T AVD3 should be connected to analog +5V .TVDDO18PowerPower for TXC ± and RXDO ±.Receive PowerName Pin No I/O DescriptionRAVD130Power The power pin for receive clock and data recovery block reference circuitry. RAVD1 shouldbe connected to analog +5V.RAVD236Power The power pin for receive clock and data recovery block active loop filter and oscillator.RAVD2 should be connected to analog +5V.RAVD324Power The power pin for the RXD± and ALOS± PECL inputs. RAVD3 should be connected toanalog +5V.RAVD432Power The power pin for the RRCLK± PECL inputs. RAVD4 should be connected to analog +5V. Core PowerName Pin No I/O DescriptionV DDI20, 61,107Power The core power pins should be connected to a well decoupled +5V DC in common with V DDO.V DDO55, 73,81, 114Power The pad ring power pins should be connected to a well decoupled +5V DC in common with V DDI.GroundName Pin No I/O DescriptionTAVS15Ground The ground pin for the transmit clock synthesizer reference circuitry. TAVS1 should beconnected to analog GND.TAVS27Ground The ground pin for the transmit clock synthesizer oscillator. TAVS2 should be connectedto analog GND.TAVS311Ground The ground pin for the transmit PECL inputs. TAVS3 should be connected to analog GND. TXV SS17Ground The transmit pad ground is the return path for the TXC± and TXD± outputs. TXV SS isphysically isolated from the other device ground pins and should be noise-free for goodperformance when driving category 5 unshielded twisted pair cabling.RAVS131Ground The ground pin for receive clock and data recovery block reference circuitry. RAVS1 shouldbe connected to analog GND.RAVS237Ground The ground pin for receive clock and data recovery block active loop filter and oscillator.RAVS2 should be connected to analog GND.RAVS329Ground The ground pin for the RRCLK± PECL inputs. RAVS3 should be connected to analog GND. RAVS435Ground The ground pin for the RSD± and ALOS± PECL inputs. RAVS4 should be connected toanalog GND.RVSSO21Ground This pin is grounded for TXC± and RXDO±.V SSI19, 62,106,48Ground The core ground (V SSI) pins should be connected to GND in common with V SSO.V SSO56, 72,80, 113,49Ground The pad ring ground (V SSO) pins should be connected to GND in common with V SSI.V SS1, 38,39, 46,47, 64,65, 102,103,128Ground These pins must be connected to GND for correct operation.ATP1, ATP2, ATP340, 3,46I/O These Analog Test Points (ATPx) are for factory testing use only. These pins have to be tied to GND for correct chip operation.Pin Configuration128-pin PQFP Top ViewTBYP ATP2T AVD1T AVS1T AVD2CY7C955T AVS2A TMT AVD3TRCLK –SONET / SDH TRCLK+TRANSCEIVERTXV DD AX TXC+RVSS TXC –TXD+TXD –TXV SS TVDDO VSSI RAVD3RXD –RXD+ALOS –ALOS+RAVS3RAVD1RAVS1RRCLK –RRCLK+RAVS4RAVD2RAVS2VSST AVS3VDDI RXDO+RXDO –RAVD4A T P 1V S S I R G F C R B Y P L F +L F −L F O A T P 3V S S V S S V S S O X O F F T C P T G F C T F P O T C L K V D D O V S S O R C L K R F PR C P V D D IV S S I R A L M V S SVSSTSEN RFCLK RRDENB RDA T[0]RDA T[1]VSSO VDDO RDA T[2]RDA T[3]RDA T[4]RDA T[5]RDA T[6]RDA T[7]VSSO VDDO RPRTY TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TPRTY TWRENB RSOC TCATSOC RA TE[1]RA TE[0]VSS CSB RSTB VSS A [0]D [0]I N T B V D D I D [1]V S SV S SW R B R D B V S S I D [2]D [3]V S S O V D D O D [4]D [5]D [6]D [7]A [1]A [2]A [3]A [4]A [5]A [6]A [7]A L E TFCLK VSS RCAV S S 2345678910111213141516171819202122232425262728293031323334353637383941421284312744126451254612447123481224912150120511195211853117541165511556114102571131015811210059111996011098611099762639664108107951061059410410393929190408918887868584838281807978777675747372717069656668677C955−2DescriptionTransmit SectionTransmit Utopia Interface (TUI)The transmit interface provides a simple access from the ex-ternal environment to the ATM T ransceiver. The operation of this interface is compliant with the Utopia interface specifica-tion. The interface provides a 9-bit by 4-cell FIFO to decouple the system interface from the ATM physical layer timing. 9-bit words are clocked into the device through a clocked FIFO sys-tem interface. These 9 bits include an 8-bit data word along with a Start Of Cell (SOC) indication. The interface also pro-vides full and almost full indications (TCA). Maximum clock rate for this interface is 33 MHz.Transmit ATM Cell Processor (TACP)The ATM cell processor provides HEC generation, idle/unas-signed cell header modification, payload scrambling, and GFC insertion.HEC GeneratorThe Header Error Check (HEC) code is contained in the last byte of the A TM cell header and is capable of single error cor-rection and multiple error detection. When optionally generat-ed, the Transmit A TM Cell Processor calculates a CRC−8 over the first four bytes of the ATM cell header using the polynomial x8 + x2+ x + 1. The coset x6 + x4 + x2 + 1 is added (modulo 2) to the residue of this function. The HEC is calculated in accor-dance with ANSI T1.624−1993 and CCITT Recommendation I.432. This HEC sequence is placed in the 5th byte of the A TM cell header.Idle/Unassigned Cell Header ModificationIdle (Unassigned) cells are sent by the ATM cell processor whenever a complete cell is not contained within the T ransmit FIFO. This transforms the non-continuous cell input stream into a continuous stream of assigned and unassigned cells. The A TM cell processor provides the ability to overwrite the Generic Flow Control (GFC), the Payload T ype Indication (PTI), and the Cell Loss Priority (CLP) fields of Idle (Unas-signed) cells with the values contained in the corresponding configuration registers. VPI and VCI are set to zero in Idle (Un-assigned) cells.Payload ScramblerThe 48 bytes of the A TM payload are scrambled using a par-allel implementation of the polynomial x43 + 1 as described in CCITT Recommendation I.432. The scrambler can be option-ally deselected.GFC InsertionThe transmitted GFC field of an ATM cell can be derived from different sources. For assigned cells, the default is from pins TDAT[7:0]. For Idle (Unassigned) cells, the default is from GFC[3:0] (Reg−61H, bit 7−bit 4). However, if any bit of TGFCE[3:0] (Reg−67H, bit 7−bit4) is set, the corresponding transmitted GFC location will instead be taken from the serial TGFC (pin 52) input following the functional timing specifica-tions described in the section on Transmit GFC Serial Link Interface.Transmit SONET Path Overhead Processor (TPOP)The SONET path overhead processor provides payload point-er alignment (H1, H2), path overhead insertion, and insertion of the Synchronous Payload Envelope (SPE). ATM cells (both assigned and unassigned) are inserted into the SPE for trans-mission in the SONET frameSONET Overhead InsertionThe SONET/SDH STS−3c/STM−1 frame structure is shown in Figure 1 and the SONET STS−1 frame structure is shown in Figure 2. The SONET frame occurs once every 125 µs and is transmitted beginning with the A1 bytes, followed by the A2 bytes, C1 bytes, 261 bytes (87 bytes for STS−1) of the Syn-chronous Payload Envelope (SPE), B1 bytes, etc., until the entire frame is transmitted.The TPOP generates the H1 and H2 bytes that indicate the beginning of the SPE and the H4 byte that indicates the ATM cell offset within the SPE. The default initial value for H1 and H2 pointer is 522, meaning that the first byte of the SPE (J1) corresponding to a frame actually starts after the C1 byte of the next frame.In the default case described above, a 6h is present in the New Data Flag (NDF) portion of the first H1 (bits 0−4), a 2h is present in bits 5−7 and a 0Ah is present in the first H2 byte. The remaining H1 bytes for STS−3c/STM−1 are set to 93h and the remaining H2 bytes are set to FFh which is the concatena-tion indication for the J1 pointer. The Pointer Action byte, H3, is set to 00h. During Path AIS all of the H1 and H2 bits are set to 1.The STS path trace J1 is set to all zeros. The path BIP−8 (B3) byte provides path error monitoring. This function calculates the bit-interleaved parity-8 code using even parity over the pre-vious SPE before scrambling and is inserted into the current B3 byte before scrambling. Bit-interleaved parity-8 forces the number of 1s in the xth bit of every byte in the previous SPE plus the xth bit of the B3 byte in the current SPE to be an even number.The path signal level indicator, C2, defaults to 13h.The path status, G1, has several functions. Bits 1 through 4 are used to indicate Far End Block Errors (FEBE) derived by counting the number of BIP−8 errors occurred in the last frame received. Valid codes are 0 through 8. If more than 8 errors have accumulated since the last, frame the maximum value is sent with the current frame, the FEBE counter is decremented by 8, and the remaining errors are sent with the next frame. FEBE may be inserted through register control for diagnostic purposes. Bits 1 through 4 can also be used to transmit Far End Receive Failures by setting these bits to 9 (1001). This error indicates to the far end that cell delineation has been lost. Bit 5 can be used to generate a yellow alarm condition. The default value for this bit is 0 (no alarm).The multi-frame indicator, H4, is used to indicate the first ATM cell and may take on values of 00 to 34h.The remaining bytes, F2, Z3, Z4, and Z5, are not used by the SONET path processing and are set to 00h upon transmission. When operating in STS−1 mode, SPE columns 30 and 59 can be configured as fixed stuff columns.Figure 1. STS −3c/STM − 1 Framing FormatA1A1A1A2A2A2C1C1C1B1H1H1H1H2H2H2H3H3H3B2B2B2K2Z2J1B3C2G1H4L i n eS e c t i o nP a t h PayloadPayloadF2Z3Z4Z5E1F1D1D2D3K1D4D5D6D7D8D9D10D11D12Z1Z1Z1Z2Z2E2HD1HD2HD3HD4HEC PAYLOAD9Bytes261Bytes9 B y t e s7C955−3Figure 2. STS −1 Framing FormatA1A2C1B1H1H2H3B2K2J1B3C2G1H4L i n eS e c t i o nP a t hPayloadPayloadF2Z3Z4Z5E1F1D1D2D3K1D4D5D6D7D8D9D10D11D12Z1Z2E2HD1HD2HD3HD4HEC PAYLOAD3Bytes 87Bytes9 B y t e s7C955−4Transmit SONET Line Overhead Processor (TLOP)The Transmit SONET line overhead processor (TLOP) pro-vides BIP−8/24 generation and line level alarms.The BIP−8/24 code is calculated as if the STS−3c frame was composed of three STS−1s. The first B2 byte is calculated over the first STS−1 frame, the second B2 byte over the second STS−1 frame and the third B2 byte over the third STS−1 frame. Each B2 bit is calculated over the line and SPE portions of the previous frame before scrambling using even parity and insert-ed into the current frame before scrambling. For STS−1 RA TE, a BIP−8 is calculated over the entire SPE and line overhead and placed in B2.The Line Alarm Indication Signal (LAIS), is asserted by chang-ing all bits of the SONET frame into 1 before scrambling. LAIS generation is controlled by a register setting (Reg−14H, bit 0). The Line Far End Receive Failure (LFERF), also called Line RDI, is indicated by placing a 110 pattern in bits 6,7, and 8 of the first K2 byte. LFERF can be asserted under register (Reg−20H, bit 0) control.The Line Far End Block Errors (LFEBE) are located in the third Z2 byte and indicate the number of B2 errors in the previous frame interval. Legal values for this byte are 00h through 18h. All bytes of the line data communication channel (D4−D12) and all other unused bytes are encoded to 00h.Transmit SONET Section Overhead Processor (TSOP) The T ransmit SONET Line Overhead Processor (TSOP) pro-vides A1,A2 framing pattern generation, section BIP−8 (B1) insertion, section level alarm insertion, and frame scrambling. The A1 and A2 bytes provide a framing pattern for frame align-ment. All A1 bytes are coded to F6h and all A2 bytes are coded to 28h. These bytes are not scrambled upon transmission. The STS−1 identification bytes, C1, are used for framing and de-interleaving purposes and are coded the order in their ap-pearance in the STS−3c frame. The first C1 byte is coded to 01h, the second to 02h, and the third to 03h.The section BIP−8 (B1) is the byte-interleaved parity-8 calcu-lated over all bytes of the previous frame after scrambling and inserted into the current frame before scrambling.The bytes of the section data communication channel, D1−D3 and the remaining unused bytes are set to 00h.The frame is scrambled prior to transmission with the generat-ing polynomial x7 + x6 + 1. The A1, A2, and C1 bytes are not scrambled. The scrambler runs continuously through the frame and resets at the beginning of the next transmission frame. The scrambler may be optionally disabled.Transmit Clock Generator (TCG)The TCG accepts a byte-rate transmit clock from TRCLK that operates at either 19.44 MHz for STS−3c/STM−1 RA TE or at 6.48 MHz for STS−1 RATE. The T ransmit PLL multiplies this byte-rate reference by eight to produce the bit-rate clock used by the parallel-to-serial converter. Optionally a bit-rate source can be taken from an external source (TBYP = 1) or from the Receive Clock Recovery block when in loop-time mode (LOOPT = 1). In loop-time mode the recovered clock is used to provide timing to the transmitter.Parallel to Serial Converter (PSC)The PSC converts the parallel data from the TSOP to serial data. The bit rate clock is derived from the T ransmit Clock Gen-erator. The serialized data and aligned output clock are pre-sented to the Transmit Output Multiplexer.Transmit Output Multiplexer (TOM)The TOM selects between the serialized output data stream and associated clock provided by the PSC and the recovered data and clock from the Receive Clock Recovery block for transmission based on the state of the local loop back enable (LLE) register (Reg−05H, bit 2). When LLE = 1 the recovered data and recovered clock is selected for output on the transmit data lines (TXD±) and the transmit clock lines (TXC±). The output signal is 100K compatible differential Positive-refer-enced ECL (PECL) signal capable of driving any copper or fiber based media with impedances as LOW as 50Ω. Receive SectionReceive Clock Recovery (RCR)The RCR provides clock and data recovery from an incoming differential PECL data stream. Clock and data are recovered from the incoming differential PECL data stream without the need for external buffering and AC-coupling. The built-in line receiver inputs have a wide common-mode range (2.5−5V) and the ability to receive signals with as little as 200 mV differ-ential voltage. They are compatible with all PECL signals. They are compatible with all PECL signals driven by optical modules or twisted-pair equalizers. The Receive PLL uses the RRCLK as a byte-rate reference. This input is multiplied by 8 and is used to improve PLL lock time and to provide a center frequen-cy for operation in the absence of input data stream transitions. The receiver can recover clock and data in two different fre-quency ranges depending on the state of the RATE0 pin. T o insure accurate data and clock recovery, the received data stream must be within 1000 ppm of RRCLK * 8 (The PLL will declare Out Of Lock if the data rate is different from REFCLK x 8 by more than 2000 ppm. The PLL will remain Out Of Lock until the data rate pulls back to within 700 ppm of REFCLK x 8 frequency). The standards, however, specify that the RRCLK*8 frequency accuracy be within 20−100 ppm. The wid-er frequency tolerance range of the CY7C955 is an advantage that allows for higher frequency tolerance in bench testing set-ups.A Loss of Signal (ROOL V = 1) is declared when no transitions have been detected on the incoming data stream for more than 512 bit-times. LOS is cleared when two valid framing patterns (A1, A2) have been found and the intervening data does not contain a period that violates the minimum transitions limit. Serial to Parallel Conversion (SPC)The SPC converts bit serial data to byte serial data from either the recovered received data or the transmit data from the PSC depending on the state of the DLE register (Reg−05H, bit 1). When DLE =1 transmit data is used for serial to parallel con-version. The SPC also provides SONET framing by scanning the incoming data for the SONET framing pattern A1,A2. For STS−1 RA TE the framer looks for the pattern F628h and for STS−3 RA TE the framer looks for the pattern F6F6F6282828h. Out of Frame (OOF) is declared when four consecutive frames contain a framing error. OOF clears when two frames contain valid framing characters. Loss of Frame。

元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。