CY7C1041DV33-12VXE中文资料

±2G/±4G/±8G/±16G三轴微机械数字加速度计描述SC7A20是一款高精度12bit数字三轴加速度传感器芯片，内置功能更丰富，功耗更低，体积更小，测量更精确。

芯片通过I²C/SPI接口与MCU通信，加速度测量数据以中断方式或查询方式获取。

INT1和INT2中断管脚提供多种内部自动检测的中断信号，适应多种运动检测场合，中断源包括6D/4D方向检测中断信号、自由落体检测中断信号、睡眠和唤醒检测中断信号、单击和双击检测中断信号。

芯片内置高精度校准模块，对传感器的失调误差和增益误差进行精确补偿。

±2G、±4G、±8G和±16G四种可调整的全量程测量范围，灵活测量外部加速度，输出数据率1HZ和400HZ间可选。

芯片内置自测试功能允许客户系统测试时检测系统功能，省去复杂的转台测试。

芯片内置产品倾斜校准功能，对贴片和板卡安装导致的倾斜进行补偿，不占系统资源，系统文件升级不影响传感器参数。

主要特点宽电压范围1.71V-3.6V1.8V兼容数字IO口低功耗模式下电源电流低至2µA±2G/±4G/±8G/±16G动态全量程范围 12bit有效数据(HR)I²C/SPI数字输出接口6D/4D方向检测自由落体检测单击双击检测及运动检测可编程中断生成电路内嵌自测试功能内嵌FIFO10000g高G抗击能力应用手机平板室内导航图像旋转运动激活用户接口游戏产品规格分类产品名称 封装形式 打印名称 材料 包装形式 SC7A20TR LGA-12-2x2x1.0 SC7A20 无铅编带内部框图XY ZC-to-V Converter Gain数符号测试条件最小值V CC电路不损坏-0.3 3.6V P电路不损坏V in电路不损坏T OPR电路不损坏T STG电路不损坏(VDD=2.5V, T测试条件123FS=0 (HR mode)FS=1 (HR mode)FS=2 (HR mode)FS=3 (HR mode)参 数符 号测试条件最小值 典型值 最大值 单位 零漂 Ty Off0 FS =0 --±40--mg温漂TC Off 与25°C 的最大偏差 -- ±0.5 -- mg/°C 自测输出V st1FS=0， X 轴 -- 276 -- LSb V st2 FS=0， Y 轴 -- 276 -- LSb V st3FS=0， Z 轴-- 984 -- LSb 系统带宽 BW -- ODR/2 -- HZ 工作温度T OPR-40--+85°C注意：电路2.5V 出厂校准。

PRELIMINARY 8-Mbit (512K x 16) Static RAMCY7C1051DV33Features•High speed —t AA = 10 ns •Low active power—I CC = 110 mA @ 10 ns •Low CMOS standby power —I SB2 = 20 mA •2.0V data retention•Automatic power-down when deselected •TTL-compatible inputs and outputs•Easy memory expansion with CE and OE features•Available in lead-free 48-ball FBGA and 44-pin TSOP II packagesFunctional Description [1]The CY7C1051DV33 is a high-performance CMOS Static RAM organized as 512K words by 16 bits.Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,then data from IO pins (IO 0–IO 7), is written into the location specified on the address pins (A 0–A 18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO 8–IO 15) is written into the location specified on the address pins (A 0–A 18).Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO 0–IO 7.If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on IO 8 to IO 15. See the “Truth Table” on page 8 for a complete description of Read and Write modes.The input/output pins (IO 0–IO 15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,and WE LOW) is in progress.The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.Note1.For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at .1415Logic Block DiagramA 1A 2A 3A 4A 5A 6A 7A 8COLUMN DECODERR O W D E C O D E RS E N S E A M P SINPUT BUFFER512K × 16ARRAYA 0A 11A 13A 12A A A 16A 17A 18A 9A 10IO 0–IO 7OE IO 8–IO 15CE WE BLEBHEPRELIMINARY CY7C1051DV33Selection Guide–10Unit Maximum Access Time 10ns Maximum Operating Current 110mA Maximum CMOS Standby Current20mAPin Configurations [2]48-ball Mini FBGAWE V CC A 11A 10NC A 6A 0A 3CE IO 10IO 8IO 9A 4A 5IO 11IO 13IO 12IO 14IO 15V SS A 9A 8OE V SS A 7IO 0BHE NC A 17A 2A 1BLE V CC IO 2IO 1IO 3IO 4IO 5IO 6IO 7A 15A 14A 13A 12NC A 18NC326541D E B A C F G HA 16(Top View)TSOP IIWE 1234567891011143132363534333740393812134144434216152930V CC A 5A 6A 7A 8A 0A 1OE V SS A 17IO 15A 2CE IO 2IO 0IO 1BHE A 3A 418172019IO 32728252622212324V SS IO 6IO 4IO 5IO 7A 16A 15BLE V CC IO 14IO 13IO 12IO 11IO 10IO 9IO 8A 14A 13A 12A 11A 9A 10A 18(Top View)Note2.NC pins are not connected on the diePRELIMINARY CY7C1051DV33Maximum Ratings(Exceeding the maximum ratings may impair the useful life of the device. These are for user guidelines, they are not tested.)Storage Temperature .................................–65°C to +150°C Ambient Temperature withPower Applied.............................................–55°C to +125°C Supply Voltage on V CC to Relative GND [3]....–0.5V to +4.6V DC Voltage Applied to Outputsin High-Z State [3]....................................–0.3V to V CC + 0.3V DC Input Voltage [3].................................–0.3V to V CC + 0.3VCurrent into Outputs (LOW).........................................20 mA Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015)Latch-up Current......................................................>200 mAOperating RangeRange Ambient Temperature V CC Industrial–40°C to +85°C3.3V ± 0.3VDC Electrical Characteristics Over the Operating RangeParameter DescriptionTest Conditions–10Unit Min MaxV OH Output HIGH Voltage V CC = Min, I OH = –4.0 mA 2.4V V OL Output LOW Voltage V CC = Min, I OL = 8.0 mA0.4V V IH Input HIGH Voltage 2.0V CC + 0.3V V IL [3]Input LOW Voltage –0.30.8V I IX Input Leakage Current GND < V I < V CC–1+1μA I OZ Output Leakage Current GND < V OUT < V CC , Output Disabled –1+1μA I CCV CC Operating Supply CurrentV CC = Max, f = f MAX = 1/t RC100 MHz 110mA83 MHz 100 66 MHz 9040 MHz80I SB1Automatic CE Power Down Current —TTL Inputs Max V CC , CE > V IH V IN > V IH or V IN < V IL , f = f MAX 40mA I SB2Automatic CE Power Down Current —CMOS Inputs Max V CC , CE > V CC – 0.3V,V IN > V CC – 0.3V or V IN < 0.3V, f = 020mACapacitance [4]Parameter DescriptionTest ConditionsMax.Unit C IN Input Capacitance T A = 25°C, f = 1 MHz, V CC = 3.3V12pF C OUTIO Capacitance12pFNotes3.V IL (min) = –2.0V and V IH (max) = V CC + 2.0V for pulse durations of less than 20 ns.4.Tested initially and after any design or process changes that may affect these parametersThermal Resistance [4]ParameterDescription Test ConditionsFBGA PackageTSOP II PackageUnit ΘJA Thermal Resistance (Junction to Ambient)Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board28.3151.43°C/W ΘJCThermal Resistance (Junction to Case)11.415.8°C/WPRELIMINARYCY7C1051DV33AC Test Loads and Waveforms [5]AC Switching Characteristics [6] Over the Operating RangeParameterDescription–10UnitMinMaxRead Cycle t power [7]V CC (typical) to the first access 100μs t RC Read Cycle Time 10ns t AA Address to Data Valid10ns t OHA Data Hold from Address Change 3ns t ACE CE LOW to Data Valid 10ns t DOE OE LOW to Data Valid 5ns t LZOE OE LOW to Low-Z 0ns t HZOE OE HIGH to High-Z [8, 9]5ns t LZCE CE LOW to Low-Z [9]3ns t HZCE CE HIGH to High-Z [8, 9]5ns t PU CE LOW to Power Up 0ns t PD CE HIGH to Power Down 10ns t DBE Byte Enable to Data Valid 5ns t LZBE Byte Enable to Low-Z 0ns t HZBEByte Disable to High-Z6nsNotes5.AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test loadshown in Figure (c).6.Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.7.t POWER gives the minimum amount of time that the power supply should be at typical V CC values until the first memory access can be performed.8.t HZOE , t HZCE , t HZBE and t HZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads.Transition is measured when the outputs enter ahigh impedance state.9.At any given temperature and voltage condition, t HZCE is less than t LZCE , t HZOE is less than t LZOE , t HZBE is less than t LZBE , and t HZWE is less than t LZWE for anygiven device.90%10%3.0VGND90%10%ALL INPUT PULSES * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENTRise Time: 1 V/nsFall Time: 1 V/ns30 pF*OUTPUTZ = 50Ω50Ω1.5V (a)3.3V OUTPUT5 pF(c)R 317ΩR2351ΩHigh-Z Characteristics(b)PRELIMINARY CY7C1051DV33Data Retention WaveformWrite Cycle [10, 11]t WC Write Cycle Time 10ns t SCE CE LOW to Write End 7ns t AW Address Setup to Write End 7ns t HA Address Hold from Write End 0ns t SA Address Setup to Write Start 0ns t PWE WE Pulse Width 7ns t SD Data Setup to Write End 5ns t HD Data Hold from Write End 0ns t LZWE WE HIGH to Low-Z [9]3ns t HZWE WE LOW to High-Z [8, 9]5ns t BWByte Enable to End of Write7nsData Retention Characteristics Over the Operating RangeParameter DescriptionConditions [12]Min MaxUnit V DR V CC for Data Retention 2.0V I CCDR Data Retention CurrentV CC = V DR = 2.0V , CE > V CC – 0.3V , V IN > V CC – 0.3V or V IN < 0.3V20mA t CDR [4]Chip Deselect to Data Retention Time 0ns t R [13]Operation Recovery Timet RCnsAC Switching Characteristics [6] Over the Operating Range (continued)ParameterDescription–10UnitMinMax3.0V 3.0V t CDRV DR > 2VDATA RETENTION MODEt RCEV CC Notes10.The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition ofeither of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.11.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t HZWE and t SD .12.No inputs may exceed V CC + 0.3V13.Full device operation requires linear V CC ramp from V DR to V CC (min) > 50 μs or stable at V CC (min) > 50 μs.PRELIMINARY CY7C1051DV33Switching WaveformsRead Cycle No. 1[14, 15]Read Cycle No. 2 (OE Controlled)[15, 16]Notes14.Device is continuously selected. OE, CE, BHE or BHE or both= V IL .15.WE is HIGH for Read cycle.16.Address valid prior to or coincident with CE transition LOW.PREVIOUS DATA VALIDDATA VALIDt RCt AAt OHAADDRESSDATA OUT50%50%DATA VALIDt RCt ACEt DOE t LZOE t LZCE t PUHIGH IMPEDANCEt HZOEt HZBEt PDHIGHOE CEICC ISB IMPEDANCEADDRESSDATA OUT V CC SUPPLY t DBE t LZBEt HZCE BHE,BLECURRENTI CCI SBPRELIMINARY CY7C1051DV33Write Cycle No. 1 (CE Controlled)[17, 18]Write Cycle No. 2 (BLE or BHE Controlled)Notes17.Data I/O is high-impedance if OE or BHE or BLE or both = V IH .18.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.Switching Waveforms (continued)t HDt SDt SCEt SA t HAt AWt PWEt WCBWDATAI/OADDRESSCEWEBHE,BLEt t HDt SDt BWt SA t HAt AWt PWEt WCt SCEDATAI/OADDRESSBHE,BLEWECEPRELIMINARY CY7C1051DV33Write Cycle No. 3 (WE Controlled, OE LOW)Switching Waveforms (continued)t HDt SDt SCEt HAt AWt PWEt WCt BWDATA I/OADDRESSCEWEBHE,BLEt SAt LZWEt HZWETruth TableCE OE WE BLE BHE I/O 0–I/O 7I/O 8–I/O 15ModePower H X X X X High-Z High-Z Power-down Standby (I SB )L L H L L Data Out Data Out Read All Bits Active (I CC )L L H L H Data Out High-Z Read Lower Bits Only Active (I CC )L L H H L High-Z Data Out Read Upper Bits Only Active (I CC )L X L L L Data In Data In Write All Bits Active (I CC )L X L L H Data In High-Z Write Lower Bits Only Active (I CC )L X L H L High-Z Data In Write Upper Bits Only Active (I CC )LHHXXHigh-ZHigh-ZSelected, Outputs DisabledActive (I CC )Ordering InformationSpeed (ns)Ordering Code Package Diagram Package TypeOperating Range 10CY7C1051DV33-10BAXI 51-8510648-ball FBGA (Pb-Free)IndustrialCY7C1051DV33-10ZSXI51-8508744-pin TSOP II (Pb-Free)Please contact your local Cypress sales representative for availability of these parts.PRELIMINARY CY7C1051DV33 Package DiagramsPRELIMINARY CY7C1051DV33Document #: 001-00063 Rev. *C Page 10 of 11© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the All products and company names mentioned in this document may be the trademarks of their respective holders.Figure 2. 44-pin TSOP II (51-85087)Package Diagrams (continued)51-85087-*APRELIMINARY CY7C1051DV33Document #: 001-00063 Rev. *C Page 11 of 11Document History Page Document Title: CY7C1051DV33 8-Mbit (512K x 16) Static RAM Document Number: 001-00063REV.ECN NO.Issue Date Orig. of Change Description of Change **342195See ECN PCI New Data Sheet *A 380574See ECN SYT Redefined I CC values for Com’l and Ind’l temperature rangesI CC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10and 12 ns speed bins respectivelyI CC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10and 12 ns speed bins respectivelyChanged the Capacitance values from 8 pF to 10 pF on Page # 3*B 485796See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from“3901 North First Street” to “198 Champion Court”Removed -8 and -12 Speed bins from product offering,Removed Commercial Operating Range option,Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V andV CC + 0.5V to V CC + 0.3VChanged the Description of I IX from Input Load Current toInput Leakage Current.Changed t HZBE from 5 ns to 6 nsUpdated footnote #7 on High-Z parameter measurementAdded footnote #11Updated the Ordering Information table and Replaced Package Name columnwith Package Diagram.*C 866000See ECN NXRChanged ball E3 from V SS to NC in FBGA pin configuration [+] FeedbThis datasheet has been downloaded from:Free DownloadDaily Updated Database100% Free Datasheet Search Site100% Free IC Replacement Search SiteConvenient Electronic DictionaryFast Search SystemAll Datasheets Cannot Be Modified Without PermissionCopyright © Each Manufacturing Company。

UPC4574G2-E1中⽂资料The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.DATA SHEETDocument No. G15977EJ4V0DS00 (4th edition)Date Published March 2004 N CP(K) Printed in JapanThe mark shows major revised points.1987DESCRIPTIONThe µPC4574 is an ultra low noise, high slew rate quad operational amplifier specifically designed for audio, instrumentation, and communication circuits. The low noise and high frequency capabilities make it ideal for preamps and active filters for instrumentation and professional audio.FEATURESUltra low noise High slew rate Wide bandwidthInternal frequency compensationORDERING INFORMATIONPart NumberPackageµPC4574C µPC4574C(5) 14-pin plastic DIP (7.62 mm (300)) 14-pin plastic DIP (7.62 mm (300)) µPC4574G2 µPC4574G2(5) 14-pin plastic SOP (5.72 mm (225)) 14-pin plastic SOP (5.72 mm (225))EQUIVALENT CIRCUIT (1/4 Circuit)I I I NVVPIN CONFIGURATION (Top View)OUT 4I I4I N4V ?I N3I I3OUT 3OUT 1I I1I N1V +I N2I I2OUT 2PC4574C, 4574C(5), 4574G2, 4574G2(5)µData Sheet G15977EJ4V0DS2ABSOLUTE MAXIMUM RATINGS (T A = 25°C)Parameter SymbolRatings Unit Voltage between V +and V ? Note1V +V0.3 to +36VDifferential Input Voltage V ID ±30 V Input VoltageNote2V IV ??0.3 to V ++0.3 V Output VoltageNote3V OV ??0.3 to V + +0.3VC Package Note4570 mW Power Dissipation G2 PackageNote5P T 550 mW Output Short Circuit DurationNote610 sec Operating Ambient Temperature T A ?20 to +80 °C Storage TemperatureT stg55 to +125°CNotes 1. Reverse connection of supply voltage can cause destruction.2. The input voltage should be allowed to input without damage or destruction. Even during the transition periodof supply voltage, power on/off etc., this specification should be kept. The normal operation will establish when the both inputs are within the Common Mode Input Voltage Range of electrical characteristics.3. This specification is the voltage which should be allowed to supply to the output terminal from externalwithout damage or destructive. Even during the transition period of supply voltage, power on/off etc., this specification should be kept. The output voltage of normal operation will be the Output Voltage Swing of electrical characteristics.4. Thermal derating factor is –7.6 mW/°C when ambient temperature is higher than 50°C.5. Thermal derating factor is –5.5 mW/°C when ambient temperature is higher than 25°C.6. Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note 4 andNote 5.RECOMMENDED OPERATING CONDITIONSParameter Symbol MIN. TYP. MAX. UnitSupply Voltage V ± ±4 ±16 V Output Current I O±10 mASource Resistance R S 50k ?Capacitive Load (A V = +1)C L 100 pFµPC4574C, µPC4574G2±Notes 7. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.8.This current flows irrespective of the existence of use.Data Sheet G15977EJ4V0DS 3µPC4574C(5), µPC4574G2(5)±Notes 7. Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.8.This current flows irrespective of the existence of use.4Data Sheet G15977EJ4V0DSMEASUREMENT CIRCUITFig.1 Total Harmonic Distortion Measurement CircuitnFig.3 Flat Noise Measurement Circuit (FLAT+JIS A)V O = 40 dB x V n100 V n =V O40 dBData Sheet G15977EJ4V0DS 5Data Sheet G15977EJ4V0DS6TYPICAL PERFORMANCE CHARACTERISTICS (T A = 25°C, TYP.) T A - Operating Ambient Temperature - ?CPOWER DISSIPATIONP T - T o t a l P o w e r D i s s i p a t i o n - m W800600400200020*********20406080100120110010 k 1 M 1 k 10100 k 10 Mf - Frequency - HzOPEN LOOP FREQUENCY RESPONSEA V - O p e n L o o p V o l t a g e G a i n - d BV ± = ±15 V202040608021.510.50?0.5?1?1.5?2T A - Operating Ambient Temperature - ?CINPUT OFFSET VOLTAGEV I O - I n p u t O f f s e t V o l t a g e - m V= ±15 VV ±each 5 samples data806040200?20550530510490470450T A - Operating Ambient Temperature - ?CINPUT BIAS CURRENTI B - I n p u t B i a s C u r r e n t - n A= ±15 VV ±f - Frequency - HzLARGE SIGNAL FREQUENCY RESPONSE V o m - O u t p u t V o l t a g e S w i n g - V p -p 01020301001 k 10 k 100 k 1 M 10 MV = ±15 V±R L = 10 k ?I O - Output Current - mAOUTPUT CURRENT LIMITV O - O u t p u t V o l t a g e - V±±5±10±15T A - Operating Ambient Temperature - ?CSUPPLY CURRENTI C C - S u p p l y C u r r e n t - m A12963204020060800V = ±15 V±SUPPLY CURRENTI C C - S u p p l y C u r r e n t - m A12963±10±20V - Supply Voltage - V±Data Sheet G15977EJ4V0DS7COMMON MODE INPUT VOLTAGE RANGE V I C M - C o m m o n M o d e I n p u t V o l t a g e R a n g e - V 20100±10±20V - Supply Voltage - V±VOLTAGE FOLLOWER PULSE RESPONSE V O - O u t p u t V o l t a g e - V10551002468t - Time - sµV = ±15 V ±A V = 1R L = 2 k ?INPUT NOISE VOLTAGE (FLAT + JIS A)V n - I n p u t N o i s e V o l t a g e - V r .m .s .1001010.1101001 k10 k100 kR S - Source Resistance - ?V = ±15 V±µf - Frequency - HzINPUT EQUIVALENT NOISE VOLTAGE DENSITY e n - I n p u t E q u i v a l e n t N o i s e V o l t a g e D e n s i t y - n V / H z20468100 1 k10 k 100 k10±R S = 100 VTOTAL HARMONIC DISTORTIONT H D - T o t a l H a r m o n i c D i s t o r t i o n - %10.0010.010.10.000110100 1 k10 k 100 kf - Frequency - HzV = ±15 V ±V O = 3 V r.m.s.A V = 1R L = 2 k ?Data Sheet G15977EJ4V0DS8PACKAGE DRAWINGS (Unit: mm)14-PIN PLASTIC DIP (7.62 mm (300))ITEM MILLIMETERS A 19.22±0.22.14 MAX.F I J D 1.32±0.12G 3.6±0.3C B 2.54 (T.P.)0.50±0.10R 0~15°H 0.51 MIN.K 7.62 (T.P.)L 6.4±0.23.554.3±0.2N 0.25NOTES1. Each lead centerline is located within 0.25 mm ofits true position (T.P.) at maximum material condition.2. ltem "K" to center of leads when formed parallel.P14C-100-300B1-3M 0.25+0.10?0.05Data Sheet G15977EJ4V0DS9ITEM B C I 14-PIN PLASTIC SOP (5.72 mm (225))D E G H J PMILLIMETERS 1.27 (T.P.)1.42 MAX.A 10.2±0.264.4±0.10.1±0.10.426.5±0.21.49+0.08?0.071.1±0.163°+7°?3°NOTEEach lead centerline is located within 0.1 mm ofits true position (T.P.) at maximum material condition.F 1.59+0.21?0.2K L M N 0.6±0.20.170.10.10+0.08?0.07S14GM-50-225B, C-6RECOMMENDED SOLDERING CONDITIONSThe µPC4574 should be soldered and mounted under the following recommended conditions.For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative.For technical information, see the following website.Semiconductor Device Mount Manual (/doc/015a7dda76a20029bd642de6.html/pkg/en/mount/index.html)Type of Surface Mount DeviceµPC4574G2, 4574G2(5): 14-pin plastic SOP (5.72 mm (225))Process ConditionsSymbol Infrared Ray Reflow Peak temperature: 230°C or below (Package surface temperature),Reflow time: 30 seconds or less (at 210°C or higher),Maximum number of reflow processes: 1 time.IR30-00-1Vapor Phase Soldering Peak temperature: 215°C or below (Package surface temperature),Reflow time: 40 seconds or less (at 200°C or higher),Maximum number of reflow processes: 1 time.VP15-00-1Wave Soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less,Maximum number of flow processes: 1 time,Pre-heating temperature: 120°C or below (Package surface temperature).WS60-00-1Partial Heating Method Pin temperature: 300°C or below,Heat time: 3 seconds or less (Per each side of the device).–Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or thedevice will be damaged by heat stress.Type of Through-hole DeviceµPC4574C, 4574C(5): 14-pin plastic DIP (7.62 mm (300))Process ConditionsWave Soldering (only to leads) Solder temperature: 260°C or below, Flow time: 10 seconds or less.Partial Heating Method Pin temperature: 300°C or below,Heat time: 3 seconds or less (per each lead).Caution For through-hole device, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered.Data Sheet G15977EJ4V0DS10The information in this document is current as of March, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of N EC Electronics products. N ot all products and/or types are available in every country. Please check with an N EC Electronics sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. 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元器件交易网
CY7C1041DV33
Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC® Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18