CY7C4231V-15AC中文资料

EZ-USB FX2LP™ USB MicrocontrollerCY7C68013A/CY7C68014A CY7C68015A/CY7C68016A1.0Features (CY7C68013A/14A/15A/16A)•USB 2.0–USB-IF high speed certified (TID # 40440111)•Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor•Fit, form and function compatible with the FX2—Pin-compatible—Object-code-compatible—Functionally-compatible (FX2LP is a superset)•Ultra Low power: I CC no more than 85 mA in any mode —Ideal for bus and battery powered applications •Software: 8051 code runs from:—Internal RAM, which is downloaded via USB —Internal RAM, which is loaded from EEPROM —External memory device (128 pin package)•16 KBytes of on-chip Code/Data RAM•Four programmable BULK/INTERRUPT/ISOCHRO-NOUS endpoints—Buffering options: double, triple, and quad•Additional programmable (BULK/INTERRUPT) 64-byte endpoint•8- or 16-bit external data interface •Smart Media Standard ECC generation •GPIF (General Programmable Interface)—Allows direct connection to most parallel interface—Programmable waveform descriptors and configu-ration registers to define waveforms—Supports multiple Ready (RDY) inputs and Control (CTL) outputs•Integrated, industry-standard enhanced 8051—48-MHz, 24-MHz, or 12-MHz CPU operation —Four clocks per instruction cycle —Two USARTS—Three counter/timers—Expanded interrupt system —Two data pointers•3.3V operation with 5V tolerant inputs•Vectored USB interrupts and GPIF/FIFO interrupts •Separate data buffers for the Set-up and Data portions of a CONTROL transfer•Integrated I 2C controller, runs at 100 or 400 kHz •Four integrated FIFOs—Integrated glue logic and FIFOs lower system cost —Automatic conversion to and from 16-bit buses —Master or slave operation—Uses external clock or asynchronous strobes —Easy interface to ASIC and DSP ICs•Available in Commercial and Industrial temperature grade (all packages except VFBGA)A d d r e s s (16)x20PLL/0.5/1.0/2.08051 Core 12/24/48 MHz,four clocks/cycleI 2CVCC1.5kD+D–A d d r e s s (16) / D a t aB u s (8)FX2LPGPIFCY Smart USB 1.1/2.0EngineUSB 2.0XCVR16 KB RAM4 kB FIFOIntegrated full- and high-speedXCVRAdditional I/Os (24)ADDR (9)CTL (6)RDY (6)8/16D a t a (8)24 MHz Ext. XTALEnhanced USB core Simplifies 8051 code “Soft Configuration”Easy firmware changes FIFO and endpoint memory (master or slave operation)Up to 96 MBytes/s burst rateGeneralprogrammable I/F to ASIC/DSP or bus standards such as ATAPI, EPP , etc.Abundant I/Oincluding two USARTS High-performance micro using standard toolswith lower-power optionsMasterFigure 1-1. Block Diagramconnected for full speedECC1.1Features (CY7C68013A/14A only)•CY7C68014A: Ideal for battery powered applications —Suspend current: 100 µA (typ)•CY7C68013A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in five lead-free packages with up to 40 GPIOs —128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs),56-pin QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VFBGA (24 GPIOs)1.2Features (CY7C68015A/16A only)•CY7C68016A: Ideal for battery powered applications—Suspend current: 100 µA (typ)•CY7C68015A: Ideal for non-battery powered applica-tions—Suspend current: 300 µA (typ)•Available in lead-free 56-pin QFN package (26 GPIOs)—2 more GPIOs than CY7C68013A/14A enabling addi-tional features in same footprintCypress Semiconductor Corporation’s (Cypress’s) EZ-USB FX2LP™ (CY7C68013A/14A) is a low-power version of the EZ-USB FX2™ (CY7C68013), which is a highly integrated, low-power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-effective solution that provides superior time-to-market advantages with low power to enable bus powered applications.The ingenious architecture of FX2LP results in data transfer rates of over 53 Mbytes per second, the maximum-allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcon-troller in a package as small as a 56 VFBGA (5mm x 5mm). Because it incorporates the USB 2.0 transceiver, the FX2LP is more economical, providing a smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2LP, the Cypress Smart SIE handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors. The FX2LP draws considerably less current than the FX2 (CY7C68013), has double the on-chip code/data RAM and is fit, form and function compatible with the 56-, 100-, and 128-pin FX2.Five packages are defined for the family: 56VFBGA, 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.2.0 Applications•Portable video recorder•MPEG/TV conversion•DSL modems•ATA interface•Memory card readers•Legacy conversion devices•Cameras•Scanners•Home PNA•Wireless LAN•MP3 players•NetworkingThe “Reference Designs” section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Please visit for more information.3.0Functional Overview3.1USB Signaling SpeedFX2LP operates at two of the three rates defined in the USB Specification Revision 2.0, dated April 27, 2000:•Full speed, with a signaling bit rate of 12 Mbps •High speed, with a signaling bit rate of 480 Mbps.FX2LP does not support the low-speed signaling mode of 1.5Mbps.3.28051 MicroprocessorThe 8051 microprocessor embedded in the FX2LP family has 256 bytes of register RAM, an expanded interrupt system,three timer/counters, and two USARTs.3.2.18051 Clock FrequencyFX2LP has an on-chip oscillator circuit that uses an external 24-MHz (±100-ppm) crystal with the following characteristics:•Parallel resonant •Fundamental mode •500-µW drive level•12-pF (5% tolerance) load capacitors.An on-chip PLL multiplies the 24-MHz oscillator up to 480MHz, as required by the transceiver/PHY , and internal counters divide it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.The CLKOUT pin, which can be three-stated and inverted using internal control bits, outputs the 50% duty cycle 8051clock, at the selected 8051 clock frequency—48, 24, or 12MHz.3.2.2USARTSFX2LP contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are available on separate I/O pins, and are not multi-plexed with port pins.UART0 and UART1 can operate using an internal clock at 230KBaud with no more than 1% baud rate error. 230-KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)such that it always presents the correct frequency for 230-KBaud operation.[1]3.2.3Special Function RegistersCertain 8051 SFR addresses are populated to provide fast access to critical FX2LP functions. These SFR additions are shown in Table 3-1. Bold type indicates non-standard,enhanced 8051 registers. The two SFR rows that end with “0”and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2LP . Because of the faster and more efficient SFR addressing, the FX2LP I/O ports are not addressable in external RAM space (using the MOVX instruction).3.3I 2C BusFX2LP supports the I 2C bus as a master only at 100-/400-KHz.SCL and SDA pins have open-drain outputs and hysteresis inputs. These signals must be pulled up to 3.3V, even if no I 2C device is connected.3.4BusesAll packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-plexed on I/O ports B and D. 128-pin package: adds 16-bit output-only 8051 address bus, 8-bit bidirectional data bus.Figure 3-1. Crystal Configuration12 pf12 pf24 MHz20 × PLLC1C212-pF capacitor values assumes a trace capacitanceof 3 pF per side on a four-layer FR4 PCANote:1.115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.3.5USB Boot MethodsDuring the power-up sequence, internal logic checks the I2C port for the connection of an EEPROM whose first byte is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0), or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2LP enumerates using internally stored descriptors. The default ID values for FX2LP are VID/PID/DID (0x04B4, 0x8613, 0xAxxx where xxx = Chip revision).[2]3.6ReNumeration™Because the FX2LP’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.When first plugged into USB, the FX2LP enumerates automat-ically and downloads firmware and USB descriptor tables over the USB cable. Next, the FX2LP enumerates again, this time as a device defined by the downloaded information. This patented two-step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step has occurred.Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0. Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1, the firmware will.3.7Bus-powered ApplicationsThe FX2LP fully supports bus-powered designs by enumer-ating with less than 100 mA as required by the USB 2.0 speci-fication.3.8Interrupt System3.8.1INT2 Interrupt Request and Enable RegistersFX2LP implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors. See EZ-USB Technical Reference Manual (TRM) for more details.3.8.2USB-Interrupt AutovectorsThe main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required to identify the individual USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a “jump” instruction to the USB Interrupt service routine.Table 3-1. Special Function Registersx8x9x Ax Bx Cx Dx Ex Fx 0IOA IOB IOC IOD SCON1PSW ACC B 1SP EXIF INT2CLR IOE SBUF12DPL0MPAGE INT4CLR OEA3DPH0OEB4DPL1OEC5DPH1OED6DPS OEE7PCON8TCON SCON0IE IP T2CON EICON EIE EIP 9TMOD SBUF0A TL0AUTOPTRH1EP2468STAT EP01STAT RCAP2LB TL1AUTOPTRL1EP24FIFOFLGS GPIFTRIG RCAP2HC TH0reserved EP68FIFOFLGS TL2D TH1AUTOPTRH2GPIFSGLDATH TH2E CKCON AUTOPTRL2GPIFSGLDATLXF reserved AUTOPTRSET-UP GPIFSGLDATLNOXTable 3-2. Default ID Values for FX2LPDefault VID/PID/DIDVendor ID0x04B4Cypress SemiconductorProduct ID0x8613EZ-USB FX2LPDevice release0xAnnn Depends on chip revision(nnn = chip revision where firstsilicon = 001)Note:2.The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.The FX2LP jump instruction is encoded as follows.If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will direct the jump to the correct address out of the 27 addresses within the page.3.8.3FIFO/GPIF Interrupt (INT4)Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table3-4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.Table 3-3. INT2 USB InterruptsUSB INTERRUPT TABLE FOR INT2 Priority INT2VEC Value Source Notes1 00SUDAV Set-up Data Available2 04 SOF Start of Frame (or microframe)3 08SUTOK Set-up Token Received4 0C SUSPEND USB Suspend request5 10USB RESET Bus reset6 14HISPEED Enteredhigh speed operation7 18 EP0ACK FX2LP ACK’d the CONTROL Handshake8 1C reserved9 20 EP0-IN EP0-IN ready to be loaded with data10 24 EP0-OUT EP0-OUT has USB data11 28 EP1-IN EP1-IN ready to be loaded with data12 2C EP1-OUT EP1-OUT has USB data13 30 EP2 IN: buffer available. OUT: buffer has data14 34 EP4 IN: buffer available. OUT: buffer has data15 38 EP6 IN: buffer available. OUT: buffer has data16 3C EP8 IN: buffer available. OUT: buffer has data17 40 IBN IN-Bulk-NAK (any IN endpoint)18 44reserved19 48 EP0PING EP0 OUT was Pinged and it NAK’d20 4C EP1PING EP1 OUT was Pinged and it NAK’d21 50 EP2PING EP2 OUT was Pinged and it NAK’d22 54 EP4PING EP4 OUT was Pinged and it NAK’d23 58 EP6PING EP6 OUT was Pinged and it NAK’d24 5C EP8PING EP8 OUT was Pinged and it NAK’d25 60 ERRLIMIT Bus errors exceeded the programmed limit26 6427 68 reserved28 6C reserved29 70 EP2ISOERR ISO EP2 OUT PID sequence error30 74 EP4ISOERR ISO EP4 OUT PID sequence error31 78 EP6ISOERR ISO EP6 OUT PID sequence error32 7C EP8ISOERR ISO EP8 OUT PID sequence errorIf Autovectoring is enabled (AV4EN = 1 in the INTSET-UP register), the FX 2LP substitutes its INT4VEC byte. Therefore, if the high byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2LP pushes the program counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service routine.3.9Reset and Wakeup3.9.1Reset PinThe input pin, RESET#, will reset the FX2LP when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C680xxA the reset period must allow for the stabilization of the crystal and the PLL. This reset period should be approximately 5 ms after VCC has reached 3.0V. If the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 µs after VCC has reached 3.0V[3]. Figure3-2 shows a power-on reset condition and a reset applied during operation. A power-on reset is defined as the time reset is asserted while power is being applied to the circuit. A powered reset is defined to be when the FX2LP has previously been powered on and operating and the RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation and can be found on the Cypress web site. For more information on reset imple-mentation for the FX2 family of products visit the .Table 3-4. Individual FIFO/GPIF Interrupt SourcesPriority INT4VEC Value Source Notes 180EP2PF Endpoint 2 Programmable Flag2 84 EP4PF Endpoint 4 Programmable Flag388EP6PF Endpoint 6 Programmable Flag48C EP8PF Endpoint 8 Programmable Flag590EP2EF Endpoint 2 Empty Flag694EP4EF Endpoint 4 Empty Flag798EP6EF Endpoint 6 Empty Flag89C EP8EF Endpoint 8 Empty Flag9A0 EP2FF Endpoint 2 Full Flag10A4EP4FF Endpoint 4 Full Flag11 A8EP6FF Endpoint 6 Full Flag12AC EP8FF Endpoint 8 Full Flag13 B0GPIFDONE GPIF Operation Complete14 B4GPIFWF GPIF WaveformNote:3.If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 µs.3.9.2Wakeup PinsThe 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL. When WAKEUP is asserted by external logic, the oscil-lator restarts, after the PLL stabilizes, and then the 8051receives a wakeup interrupt. This applies whether or not FX2LP is connected to the USB.The FX2LP exits the power-down (USB suspend) state using one of the following methods:•USB bus activity (if D+/D– lines are left floating, noise on these lines may indicate activity to the FX2LP and initiate a wakeup).•External logic asserts the WAKEUP pin •External logic asserts the PA3/WU2 pin.The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network to be used as a periodic wakeup source. Note that WAKEUP is by default active LOW.3.10Program/Data RAM3.10.1SizeThe FX2LP has 16 KBytes of internal program/data RAM,where PSEN#/RD# signals are internally ORed to allow the 8051 to access it as both program and data memory. No USB control registers appear in this space.Two memory maps are shown in the following diagrams:Figure 3-3 Internal Code Memory, EA = 0Figure 3-4 External Code Memory, EA = 1.3.10.2Internal Code Memory, EA = 0This mode implements the internal 16-KByte block of RAM (starting at 0) as combined code and data memory. When external RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This allows the user to connect a 64-KByte memory without requiring address decodes to keep clear of internal memory spaces.Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM spaces have the following access:•USB download •USB upload •Set-up data pointer •I 2C interface boot load.3.10.3External Code Memory, EA = 1The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as data memory.Figure 3-2. Reset Timing PlotsV IL 0V3.3V 3.0VT RESETVCCRESET#Power on ResetT RESETVCCRESET#V IL Powered Reset3.3V0VTable 3-5. Reset Timing ValuesConditionT RESET Power-on Reset with crystal 5 msPower-on Reset with external clock200 µs + Clock stability timePowered Reset 200 µsFigure 3-3. Internal Code Memory, EA = 0Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populate data memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Code and Data(PSEN#,RD#,WR#)*48 KBytes External Code Memory (PSEN#)(OK to populate programmemory here—PSEN# strobe is not active)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FF E0003FFF0000DataCodeFigure 3-4. External Code Memory, EA = 1Inside FX2LPOutside FX2LP7.5 KBytes USB regs and 4K FIFO buffers (RD#,WR#)0.5 KBytes RAM Data (RD#,WR#)*(OK to populatedata memory here—RD#/WR#strobes are not active)40 KBytes External Data Memory (RD#,WR#)(Ok to populate data memory here—RD#/WR#strobes are not active)16 KBytes RAM Data(RD#,WR#)*64 KBytes External Code Memory (PSEN#)*SUDPTR, USB upload/download, I 2C interface boot accessFFFFE200E1FFE0003FFF0000DataCode3.11Register Addresses3.12Endpoint RAM3.12.1Size•3× 64 bytes (Endpoints 0 and 1)•8 × 512 bytes (Endpoints 2, 4, 6, 8)3.12.2Organization•EP0•Bidirectional endpoint zero, 64-byte buffer •EP1IN, EP1OUT•64-byte buffers, bulk or interrupt •EP2,4,6,8•Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and EP8 can be double buffered, while EP2 and 6 can be either double, triple, or quad buffered. For high-speed end-point configuration options, see Figure 3-5.3.12.3Set-up Data BufferA separate 8-byte buffer at 0xE6B8-0xE6BF holds the Set-up data from a CONTROL transfer.3.12.4Endpoint Configurations (High-speed Mode)Endpoints 0 and 1 are the same for every configuration.Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either BULK or INTERRUPT. The endpoint buffers can be configured in any 1 of the 12 configurations shown in the vertical columns. When operating in full-speed BULK mode only the first 64 bytes of each buffer are used. For example in high-speed, the max packet size is 512 bytes but in full-speed it is 64 bytes. Even though a buffer is configured to be a 512byte buffer, in full-speed only the first 64 bytes are used. The unused endpoint buffer space is not available for other opera-tions. An example endpoint configuration would be:FFFFE800E7BF E740E73F E700E6FF E500E4FF E480E47F E400E200E1FFE000E3FF EFFF2 KBytes RESERVED64 Bytes EP0 IN/OUT 64 Bytes RESERVED 8051 Addressable RegistersReserved (128)128 bytes GPIF Waveforms512 bytes 8051 xdata RAMF000(512)Reserved (512)E78064 Bytes EP1OUT E77F 64 Bytes EP1IN E7FF E7C0 4 KBytes EP2-EP8buffers(8 x 512)EP2–1024 double buffered; EP6–512 quad buffered (column 8).3.12.5Default Full-Speed Alternate Settings3.12.6Default High-Speed Alternate Settings6464645125121024102410241024102410241024512512512512512512512512512512EP0 IN&OUTEP1 IN EP1 OUTFigure 3-5. Endpoint Configuration1024102410245125125125125125125125125125125125125125125125125125125125125125125125125125125125125125121024102410241024102410245125121024102451251251251251251251251210241024512512512512512512646464646464646464646464646464646464646464646464646464646464646464123456789101112Table 3-6. Default Full-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 064 bulk 64 int 64 int ep1in 064 bulk 64 int 64 int ep2064 bulk out (2×)64 int out (2×)64 iso out (2×)ep4064 bulk out (2×)64 bulk out (2×)64 bulk out (2×)ep6064 bulk in (2×)64 int in (2×)64 iso in (2×)ep8064 bulk in (2×)64 bulk in (2×)64 bulk in (2×)Notes:4.“0” means “not implemented.”5.“2×” means “double buffered.”6.Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.Table 3-7. Default High-Speed Alternate Settings [4, 5]Alternate Setting 0123ep064646464ep1out 0512 bulk [6]64 int 64 int ep1in 0512 bulk [6]64 int64 intep20512 bulk out (2×)512 int out (2×)512 iso out (2×)ep40512 bulk out (2×)512 bulk out (2×)512 bulk out (2×)ep60512 bulk in (2×)512 int in (2×)512 iso in (2×)ep80512 bulk in (2×)512 bulk in (2×)512 bulk in (2×)3.13External FIFO Interface3.13.1ArchitectureThe FX2LP slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic. The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally controlled transfers.3.13.2Master/Slave Control SignalsThe FX2LP endpoint FIFOS are implemented as eight physi-cally distinct 256x16 RAM blocks. The 8051/SIE can switch any of the RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instantaneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same memory, no bytes are actually transferred between buffers.At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O domain. The blocks can be configured as single, double, triple, or quad buffered as previ-ously shown.The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-bit interface).In Slave (S) mode, the FX2LP accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. When using an external IFCLK, the external clock must be present before switching to the external clock with the IFCLKSRC bit. Each endpoint can individually be selected for byte or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.3.13.3GPIF and FIFO Clock RatesAn 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alter-natively, an externally supplied clock of 5 MHz–48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or externally sourced. 3.14GPIFThe GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013A/15A to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia.The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and deter-mines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed to perform the desired data move between the FX2LP and the external device.3.14.1Six Control OUT SignalsThe 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock).3.14.2Six Ready IN SignalsThe 100- and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.3.14.3Nine GPIF Address OUT SignalsNine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used.3.14.4Long Transfer ModeIn master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or GPIFTCB0) for unattended transfers of up to 232 transactions. The GPIF automatically throttles data flow to prevent under or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to represent the current status of the transaction.。

PRELIMINARY18-Mbit (512K x 36/1M x 18) PipelinedSRAM with NoBL™ ArchitectureCY7C1370D CY7C1372DFeatures•Pin-compatible and functionally equivalent to ZBT™ •Supports 250-MHz bus operations with zero wait states —Available speed grades are 250, 225, 200, and 167MHz •Internally self-timed output buffer control to eliminate the need to use asynchronous OE•Fully registered (inputs and outputs) for pipelined operation•Byte Write capability •Single 3.3V power supply •3.3V/2.5V I/O power supply •Fast clock-to-output times —2.6 ns (for 250-MHz device)—2.8 ns (for 225-MHz device)—3.0 ns (for 200-MHz device)—3.4 ns (for 167-MHz device)•Clock Enable (CEN) pin to suspend operation •Synchronous self-timed writes•Available in lead-Free 100 TQFP , 119 BGA, and 165 fBGA packages•IEEE 1149.1 JTAG Boundary Scan•Burst capability—linear or interleaved burst order •“ZZ” Sleep Mode option and Stop Clock optionFunctional DescriptionThe CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and 1Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL ™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal,which when deasserted suspends operation and extends the previous clock cycle.Write operations are controlled by the Byte Write Selects (BW a –BW d for CY7C1370D and BW a –BW b for CY7C1372D)and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.Selection GuideCY7C1370D-250 CY7C1372D-250CY7C1370D-225CY7C1372D-225CY7C1370D-200CY7C1372D-200CY7C1370D-167CY7C1372D-167UnitMaximum Access Time 2.6 2.8 3.0 3.4ns Maximum Operating Current350325300275mA Maximum CMOS Standby Current70707070mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.Pin ConfigurationsA A A A A 1A 0V S SV D DA A A A A AV DDQV SS DQb DQb DQb V SSV DDQDQb DQb V SSNCV DDDQaDQa V DDQV SSDQa DQa V SS V DDQ V DDQV SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A C E 1C E 2B W aC E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZCY7C1370D 100-pin TQFP PackagesA A A A A 1A 0V S SV D DA A A A A AA NC NC V DDQ V SS NC DQPa DQa DQa V SS V DDQ DQa DQa V SS NC V DD DQa DQa V DDQ V SS DQa DQa NC NC V SS V DDQ NC NC NCNC NC NC V DDQ V SSNC NC DQb DQbV SS V DDQ DQb DQbV DD V SS DQb DQbV DDQ V SS DQb DQb DQPbNC V SS V DDQNC NC NCA A C E 1C E 2N C N C B W b B W a C E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZ M O D E CY7C1372DB W d M O D E B W c DQc DQc DQc DQc DQPc DQd DQd DQd DQPbDQbDQa DQaDQa DQaDQPa DQbDQb(512K × 36)(1M × 18)B W b NC NC NC DQc NC E (288)E (144)E (72)E (36)E (288)E (144)E (72)E (36)DQPdA APin Configurations (continued)2345671ABCDEFGHJKLMNP R T UDQ a V DDQNCNCDQ cDQ dDQ cDQ dA A A AA V DDQCE2AV DDQV DDQV DDQV DDQNCNCADQ cDQ cDQ dDQ dTMSV DDAE(72)DQP dAAADV/LD A CE3NCV DD A A NCV SS V SSNC DQP bDQ bDQ bDQ aDQ bDQ bDQ aDQ aNCTDI TDO V DDQTCKV SSV SSV SSNCV SSV SSV SSV SSMODECE1V SSOE V SS V DDQBW c AV SSWEV DDQV DD NC V DDV SSCLKNC BW aCEN V SS V DDQV SSZZNCAAA1A0V SSV DD NCCY7C1370D (512K × 36) – BGADQP c DQ bA E(36)DQ c DQ bDQ cDQ cDQ cDQ bDQ bDQ aDQ aDQ aDQ aDQP aDQ dDQ dDQ dDQ dBW d119-ball BGA PinoutBW b234567 1A B C D E F G H J K L M N P RT UE(36)DQ a V DDQNCNCNCDQ bDQ bDQ bDQ bA A A AA V DDQCE2ANCV DDQNCV DDQV DDQV DDQNCNCNCE(72)ADQ bDQ bDQ bDQ bNCNCNCNCTMSV DDAADQP bAAADV/LD A CE3NCV DD A A NCV SS V SSNC NCDQP aDQ aDQ aDQ aDQ aDQ aDQ aDQ aNCTDI TDO V DDQTCKV SSV SSV SSNCV SSNCV SSV SSV SSMODECE1V SS NCOE V SS V DDQBW b A NC NCV SSWE NCV DDQV DD NC V DDNCV SSCLKNC NCBW aCEN V SS NC V DDQV SS NCZZNCAAAA1A0V SS NCV DD NCCY7C1372D (1M x 18) – BGAPin Configurations (continued)234567 1ABCDEFGHJKLMNP RTDOE(288)NCDQP cDQ cDQP dNCDQ dA CE1BW b CE3BW c CENA CE2DQ cDQ dDQ dMODENCDQ cDQ cDQ dDQ dDQ dE(36)E(72)V DDQBW d BW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ c V SSDQ c V SSDQ cDQ cNCV SSV SSV SSV SSNCV SSA1DQ dDQ dNCNCV DDQV SSTMS891011NCA AADV/LD NCOE A A E(144)V SS V DDQ NC DQP bV DDQV DD DQ bDQ bDQ bNCDQ bNCDQ aDQ aV DD V DDQV DD V DDQ DQ bV DDNCV DDDQ aV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ DQ aV DDQAAV SSAAADQ bDQ bDQ bZZDQ aDQ aDQP aDQ aAV DDQA2345671A B C D E F G H J K L M NP RTDOE(288)NCNCNCDQP bNCDQ bA CE1NC CE3BW b CENA CE2NCDQ bDQ bMODENCDQ bDQ bNCNCNCE(36)E(72)V DDQNC BW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ b V SSNC V SSDQ bNCNCV SSV SSV SSV SSNCV SSA1DQ bNCNCNCV DDQV SSTMS891011NCA AADV/LD AOE A A E(144)V SS V DDQ NC DQP aV DDQV DD NCDQ aDQ aNCNCNCDQ aNCV DD V DDQV DD V DDQ DQ aV DDNCV DDNCV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ NCV DDQAAV SSAAADQ aNCNCZZDQ aNCNCDQ aAV DDQACY7C1372D (1M × 18) – fBGACY7C1370D (512K × 36) – fBGA165-Ball fBGA PinoutPin DefinitionsPin Name I/O Type Pin DescriptionA0 A1 AInput-SynchronousAddress Inputs used to select one of the address locations. Sampled at the rising edge ofthe CLK.BW a BW b BW c BW dInput-SynchronousByte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.Sampled on the rising edge of CLK. BW a controls DQ a and DQP a, BW b controls DQ b and DQP b,BW c controls DQ c and DQP c, BW d controls DQ d and DQP d.WE Input-Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.ADV/LD Input-Synchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.CE1Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.CE2Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE3Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.OE Input-Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.CEN Input-Synchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.DQ S I/O-Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a–DQ d are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X I/O-Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ s. During write sequences, DQP a is controlled by BW a, DQP b is controlled by BW b, DQP c is controlled by BW c, and DQP d is controlled by BW d.MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.Pulled LOW selects the linear burst order. MODE should not change states during operation.When left floating MODE will default HIGH, to an interleaved burst order.TDO JTAG serial outputSynchronousSerial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.TDI JTAG serial inputSynchronousSerial data-In to the JTAG circuit. Sampled on the rising edge of TCK.TMS Test Mode SelectSynchronousThis pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. TCK JTAG-Clock Clock input to the JTAG circuitry.V DD Power Supply Power supply inputs to the core of the device.V DDQ I/O Power Supply Power supply for the I/O circuitry.V SS Ground Ground for the device. Should be connected to ground of the system.IntroductionFunctional OverviewThe CY7C1370D and CY7C1372D are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 2.6 ns (250-MHz device).Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW X can be used to conduct byte write operations.Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.Single Read AccessesA read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.Burst Read AccessesThe CY7C1370D and CY7C1372D have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented suffi-ciently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.Single Write AccessesWrite access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block.On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D & DQ a,b/DQP a,b for CY7C1372D) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete.The data written during the write operation is controlled by BW (BW a,b,c,d for CY7C1370D and BW a,b for CY7C1372D) signals. The CY7C1370D/CY7C1372D provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.Because the CY7C1370D and CY7C1372D are common I/O devices, data should not be driven into the device while theNC–No connects. This pin is not connected to the die.E(36,72, 144, 288)–These pins are not connected. They will be used for expansion to the 36M, 72M, 144M and 288M densities.ZZ Input-Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to V SS or left floating.Pin Definitions (continued)Pin Name I/O Type Pin Descriptionoutputs are active. The Output Enable (OE) can be deassertedHIGH before presenting data to the DQ and DQP (DQ a,b,c,d/DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DQP (DQ a,b,c,d/ DQP a,b,c,d for CY7C1370D and DQ a,b/DQP a,b for CY7C1372D) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE.Burst Write AccessesThe CY7C1370D/CY7C1372D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subse-quent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BW a,b,c,d for CY7C1370D and BW a,b for CY7C1372D) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep”mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011010011101011000111100100 Linear Burst Address Table (MODE = GND)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011011011001011000111000110ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min.Max Unit I DDZZ Sleep mode standby current ZZ > V DD − 0.2V80mA t ZZS Device operation to ZZ ZZ > V DD− 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsNotes:1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.2.X . See Write Cycle Description table for details.3.When a write cycle is detected, all I/Os are tri-stated, even during byte writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal.5.6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ s and DQP X is inactive or when the device is deselected, and DQ s = data when OE is active.8.Table only lists a partial listing of the byte write combinations. Any Combination of BW X is valid Appropriate write will be done based on which byte write is active.Truth Table [1, 2, 3, 4, 5, 6, 7]OperationAddress Used CE ZZ ADV/LDWE BW x OE CENCLK DQ Deselect CycleNone H L L X X X L L-H Three-State Continue Deselect Cycle None X L H X X X L L-H Three-State Read Cycle (Begin Burst)External L L L H X L L L-H Data Out (Q)Read Cycle (Continue Burst)Next X L H X X L L L-H Data Out (Q)NOP/Dummy Read (Begin Burst)External L L L H X H L L-H Three-State Dummy Read (Continue Burst)Next X L H X X H L L-H Three-State Write Cycle (Begin Burst)External L L L L L X L L-H Data In (D)Write Cycle (Continue Burst)Next X L H X L X L L-H Data In (D)NOP/Write Abort (Begin Burst)None L L L L H X L L-H Three-State Write Abort (Continue Burst)Next X L H X H X L L-H Three-StateIgnore Clock Edge (Stall)Current X L X X X X H L-H –Sleep ModeNoneXHXXXXX XThree-StateIEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1370D/CY7C1372D incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.The CY7C1370D/CY7C1372D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(V SS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alter-nately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.Partial Write Cycle Description[1, 2, 3, 8]Function (CY7C1370D)WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a)L H H H L Write Byte b – (DQ b and DQP b)L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and DQP c)L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQ d and DQP d)L L H H H Write Bytes d, a L L H H L Write Bytes d,b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L LFunction (CY7C1372D)WE BW b BW a Read H x x Write – No Bytes Written L H H Write Byte a – (DQ a and DQP a)L H L Write Byte b – (DQ b and DQP b)L L H Write Both Bytes L L LTAP Controller State DiagramThe 0/1 next to each state represents the value of TMS at the rising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test Mode Select (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most signif-icant bit (MSB) of any register. (See Tap Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)TAP Controller Block DiagramPerforming a TAP ResetA Reset is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.Instruction RegisterThree-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass RegisterTo save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass-register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V SS) when the BYPASS instruction is executed.Boundary Scan RegisterThe boundary scan register is connected to all the input and bidirectional balls on the SRAM.The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when。