FPGA实验六
- 格式：doc
- 大小：77.00 KB
- 文档页数：3
实验项目设计两人掷骰子比较点大小的游戏电路
A、B两人玩掷骰子的游戏，当A的点数大于B的点数时，输出H=“1”、L=E=“0”；
当A的点数小于B的点数时，输出L=“1”、H=E=“0”；
当A的点数等于B的点数时，输出E=“1”、H=L=“0”；并同时用两个数码管显示A、B两人的点数。
[源程序]
--fenpinl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpinl is
port(clk:in std_logic;
y:out std_logic);
end fenpinl;
architecture one of fenpinl is
signal q:std_logic_vector(11 downto 0); signal s:std_logic;
begin
process(clk)
begin
if clk 'event and clk='1' then
if q=3000 then
s<= not s;
q<=(others=>'0');
else
q<=q+1;
end if;
end if;
y<=s;
end process;
end;
--fenpinh.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity fenpinh is
port(clk:in std_logic;
y:out std_logic);
end fenpinh;
architecture one of fenpinh is
signal q:std_logic_vector(12 downto 0); signal s:std_logic;
begin
process(clk)
begin
if clk 'event and clk='1' then
if q=7412 then
s<= not s;
q<=(others=>'0');
else
q<=q+1;
end if;
end if;
y<=s;
end process;
end;
--jishu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu is
port(clk:in std_logic;
en:in std_logic;
y:out std_logic_vector(2 downto 0)); end jishu;
architecture one of jishu is
signal q:std_logic_vector(2 downto 0);
--signal s:std_logic;
begin
process(clk,en)
begin
if en='0' then
if clk 'event and clk='1' then
if q=6 then
q<="001";
else
q<=q+1;
end if;
end if;
end if;
y<=q;
end process;
end;
--quyu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity quyu is
port(x:in std_logic_vector(3 downto 0);
y:out std_logic_vector(3 downto 0)); end quyu;
architecture one of quyu is
signal q:std_logic_vector(3 downto 0);
begin
process(x)
begin
if x>6 then
q<=x-6;
else
q<=x;
end if; y<=q;
end process;
end;
--trans.vhd
library ieee;
use ieee.std_logic_1164.all;
entity trans is
port(x:in std_logic_vector(3 downto 0);
y:out std_logic_vector(7 downto 0)); end trans;
architecture one OF trans IS
begin
with x select
y<="00111111"when"0000", "00000110"when"0001", "01011011"when"0010", "01001111"when"0011", "01100110"when"0100", "01101101"when"0101", "01111101"when"0110", "00000111"when"0111", "01111111"when"1000", "01101111"when"1001", "01110111"when"1010", "01111100"when"1011", "00111001"when"1100", "01011110"when"1101", "01111001"when"1110", "01110001"when"1111";
end one;
-- compare.vhd
library ieee;
use ieee.std_logic_1164.all;
entity compare is
port(a,b:in std_logic_vector(3 downto 0);
y:out std_logic_vector(2 downto 0);
c:out std_logic);
end compare;
architecture one OF compare IS begin
process(a,b)
begin
c<='1';
if a>b then y<="100"; if a=b then y<="010"; if a<b then y<="001"; end if;
end if;
end if;
end process;
end;
[顶层图]
play.blf
all.blf。
