总体方案分析及选择:洗衣机电路包含有总的控制模块,洗涤控制模块,洗涤记时模块,电动机控制模块以及LCD 液晶板的动态显示模块.经过分析后,我们把前四个模块进行组合,把他们合成一个模块即:总控制模块.他们之间的逻辑联结关系，是对数电课程的一个很好总结，也是自己对新知识（LCD 液晶板的动态显示）学习理解运用能力的一个很好的提升机会。
基本功能要求:1要求设计制作一个普通功能洗衣机控制电路,使之能控制洗衣机的进水阀,排水阀,洗涤程序电机,甩干驱动装置等按预定程序工作.总体过程包括:进水浸泡洗涤排水甩干五个过程.进水从电路启动开始.其中浸泡可供选择,洗涤时间可以预置,洗涤结束时发出铃声进行提示并自动切断电源.发生故障如:缺水或进水超时排水超时甩干碰桶等时也可自动切断电源!2用中小规模集成电路芯片或CPLD/FPGA设计符合上述任务要求的电路,并制作出能实际运行的装置.3安装并调试电路,测试各部分电路功能或模型.4演示并交验硬件装置.下载实现图:局部功能模块总控模块:该模块实现了对洗衣机整个运行过程的控制,打开电源后由模块内部进行控制,按洗涤过程工致洗衣机的运转.同时在输入端还给了报警输入,当发生故障时洗衣机自动短电.复位端可以让洗衣机进入初始状态.在输入端还有10个总线输入可以人为进行置数,从而控制各个过程的时间长短.当给甩干时间一个时间,其他都置为0可以让洗衣机只进行甩干操作.VHDL文件:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity xiyiji isport(clk0, clk1, rst, alarm: in std_logic;-----clk0:控制开关脉冲.clk1:记时开关脉冲.Rst:复位端.alarm:报警输入端.------- water_inh, water_inl, im_th, im_tl, wash_th: in std_logic_vector(3 downto0);wash_tl, water_outh, water_outl, dry_th, dry_tl: in std_logic_vector(3 downto 0); -----进水,浸泡,洗涤,出水,甩干置数端高位和低位输入端-----------water_in, water_out, immersion, dry, z1, z2, voice, poweroff: out std_logic; -----进水,出水,浸泡,甩干,洗涤,响铃,断电输出端-------display_th, display_tl: out std_logic_vector(3 downto 0)-------------------输出时间显示高位低位输出端-------------);end entity xiyiji;architecture behave of xiyiji issignal js, js_ten : std_logic;signal im, im_ten : std_logic;signal wa, wa_ten : std_logic;signal wa1, wa2, pwf: std_logic;signal cs, cs_ten : std_logic;signal dr, dr_ten : std_logic;signal xl, xl_ten : std_logic;signal js_dh, js_dl: std_logic_vector(3 downto 0);signal im_dh, im_dl: std_logic_vector(3 downto 0);signal wa_dh, wa_dl: std_logic_vector(3 downto 0);signal cs_dh, cs_dl: std_logic_vector(3 downto 0);signal dr_dh, dr_dl: std_logic_vector(3 downto 0);signal xl_dh, xl_dl: std_logic_vector(3 downto 0);signal dis_th,dis_tl: std_logic_vector(3 downto 0);begin-----------------------控制:控制器件实现洗衣机的功能:进水->浸泡->洗涤->出水->甩干->响铃->断电---------------control:process(clk0, rst,alarm)variable n: integer;beginif alarm = '1' thenpwf <= '1';elseif rst = '1' thenn := 0;im_ten <= '0';js_ten <= '0';wa_ten <= '0';cs_ten <= '0';dr_ten <= '0';xl_ten <= '0';pwf <= '0';elsif clk0 = '1' and clk0 'event thenif n = 0 thenif water_inh = "0000"and water_inl = "0000"thenn := 1;elsejs_ten <= '1';if js = '1' thenn := 1;end if;end if;elsif js = '0' and n = 1 thenif im_th = "0000"and im_tl = "0000"thenn := 2;elseim_ten <= '1';if im = '1' thenn := 2;end if;end if;elsif im = '0' and n = 2 thenif wash_th = "0000"and wash_tl = "0000"thenn := 3;elsewa_ten <= '1';if wa = '1' thenn := 3;end if;end if;elsif wa = '0' and n = 3 thenif water_outh = "0000"and water_outl = "0000"thenn := 4;elsecs_ten <= '1';if cs = '1' thenn := 4;end if;end if;elsif cs = '0' and n = 4 thenif dry_th = "0000"and dry_tl = "0000"thenn := 5;elsedr_ten <= '1';if dr = '1' thenn := 5;end if;end if;elsif dr = '0' and n = 5 thenxl_ten <= '1';if xl = '1' thenn := 6;end if;elsif xl = '0' and n = 6 thenpwf <= '1';end if;end if;end if;end process;-----------------------------记时----------------------------- ------------------进水记时--------------------------js_jishiqi:process(clk1, js_ten)beginif js_ten = '0' thenjs_dh <= water_inh;js_dl <= water_inl;js <= '0';elsif clk1 = '1' and clk1 'event thenif js_dh = "0000"and js_dl = "0000"thenjs <= '0';elsejs <= '1';if js_dl = "0000"thenjs_dl <= "1001";js_dh <= js_dh - 1;elsejs_dl <= js_dl - 1;end if;end if;end if;end process;-------------浸泡记时-----------------------im_jishiqi:process(clk1, im_ten)beginif im_ten = '0' thenim_dh <= im_th;im_dl <= im_tl;im <= '0';elsif clk1 = '1' and clk1 'event thenif im_dh = "0000"and im_dl = "0000"then im <= '0';elseim <= '1';if im_dl = "0000"thenim_dl <= "1001";im_dh <= im_dh - 1;elseim_dl <= im_dl - 1;end if;end if;end if;end process;-----------------洗涤记时---------------------- wa_jishiqi:process(clk1, wa_ten)variable m: integer;beginif wa_ten = '0' thenwa_dh <= wash_th;wa_dl <= wash_tl;wa <= '0';wa1 <= '0';wa2 <= '0';m := 0;elsif clk1 = '1' and clk1 'event thenif wa_dh = "0000"and wa_dl = "0000"then wa <= '0';elsewa <= '1';if m = 0 thenwa1 <= '1';wa2 <= '1';elsif m = 10 thenwa1 <= '0';wa2 <= '1';elsif m = 13 thenwa1 <= '1';wa2 <= '0';elsif m = 23 thenwa1 <= '0';wa2 <= '0';elsif m = 26 thenm := 0;end if;m := m + 1;if wa_dl = "0000"thenwa_dl <= "1001";wa_dh <= wa_dh - 1;elsewa_dl <= wa_dl - 1;end if;end if;end if;end process;--------------出水记时--------------------------- cs_jishiqi:process(clk1, cs_ten)beginif cs_ten = '0' thencs_dh <= water_outh;cs_dl <= water_outl;cs <= '0';elsif clk1 = '1' and clk1 'event thenif cs_dh = "0000"and cs_dl = "0000"then cs <= '0';elsecs <= '1';if cs_dl = "0000"thencs_dl <= "1001";cs_dh <= cs_dh - 1;elsecs_dl <= cs_dl - 1;end if;end if;end if;end process;--------------甩干记时-----------------------dr_jishiqi:process(clk1, dr_ten)beginif dr_ten = '0' thendr_dh <= dry_th;dr_dl <= dry_tl;dr <= '0';elsif clk1 = '1' and clk1 'event thenif dr_dh = "0000"and dr_dl = "0000"then dr <= '0';elsedr <= '1';if dr_dl = "0000"thendr_dl <= "1001";dr_dh <= dr_dh - 1;elsedr_dl <= dr_dl - 1;end if;end if;end if;end process;------------------响铃记时---------------------- xl_jishiqi:process(clk1, xl_ten)beginif xl_ten = '0' thenxl_dh <= "0010";xl_dl <= "0000";xl <= '0';elsif clk1 = '1' and clk1 'event thenif xl_dh = "0000"and xl_dl = "0000"then xl <= '0';elsexl <= '1';if xl_dl = "0000"thenxl_dl <= "1001";xl_dh <= xl_dh - 1;elsexl_dl <= xl_dl - 1;end if;end if;end if;end process;----------------------------显示时间--------------------------xianshishijian: process(clk1, js_ten, im_ten, wa_ten)beginif js_ten = '1' and im_ten = '0' and wa_ten = '0' and cs_ten = '0' and dr_ten = '0' and xl_ten = '0' thenif clk1 = '1' and clk1 'event thendis_th <= js_dh;dis_tl <= js_dl;end if;elsif im_ten= '1' and wa_ten= '0' and cs_ten= '0' and dr_ten= '0' and xl_ten = '0' thenif clk1 = '1' and clk1 'event thendis_th <= im_dh;dis_tl <= im_dl;end if;elsif wa_ten = '1' and cs_ten = '0' and dr_ten = '0' and xl_ten = '0' then if clk1 = '1' and clk1 'event thendis_th <= wa_dh;dis_tl <= wa_dl;end if;elsif cs_ten = '1' and dr_ten = '0' and xl_ten = '0' thenif clk1 = '1' and clk1 'event thendis_th <= cs_dh;dis_tl <= cs_dl;end if;elsif dr_ten = '1' and xl_ten = '0' thenif clk1 = '1' and clk1 'event thendis_th <= dr_dh;dis_tl <= dr_dl;end if;elsif xl_ten = '1' thenif clk1 = '1' and clk1 'event thendis_th <= xl_dh;dis_tl <= xl_dl;end if;end if;end process;----------------------------输出-----------------------------output:process(dis_th, dis_tl, im, js, cs, dr, wa1, wa2, xl, pwf)begindisplay_th <= dis_th;display_tl <= dis_tl;immersion <= im;water_in <= js;water_out <= cs;dry <= dr;z1 <= wa1;z2 <= wa2;voice <= xl;poweroff <= pwf;end process;end behave;测试文件:-------------------------------------------------------------- VHDL Testbench for xiyiji-- 2009 9 25 11 16 3-- Created by "EditVHDL"-- "Copyright (c) 2002 Altium Limited"------------------------------------------------------------Library IEEE;Use IEEE.std_logic_1164.all;Use IEEE.std_logic_textio.all;Use STD.textio.all;------------------------------------------------------------------------------------------------------------------------entity Testxiyiji isend Testxiyiji;------------------------------------------------------------------------------------------------------------------------architecture stimulus of Testxiyiji isfile RESULTS: TEXT open WRITE_MODE is"results.txt";procedure WRITE_RESULTS(alarm: std_logic;clk0: std_logic;clk1: std_logic;display_th: std_logic_vector(3 downto 0);display_tl: std_logic_vector(3 downto 0);dry: std_logic;dry_th: std_logic_vector(3 downto 0);dry_tl: std_logic_vector(3 downto 0);im_th: std_logic_vector(3 downto 0);im_tl: std_logic_vector(3 downto 0);immersion: std_logic;poweroff: std_logic;rst: std_logic;voice: std_logic;wash_th: std_logic_vector(3 downto 0);wash_tl: std_logic_vector(3 downto 0);water_in: std_logic;water_inh: std_logic_vector(3 downto 0);water_inl: std_logic_vector(3 downto 0);water_out: std_logic;water_outh: std_logic_vector(3 downto 0);water_outl: std_logic_vector(3 downto 0);z1: std_logic;z2: std_logic) isvariable l_out : line;beginwrite(l_out, now, right, 15);write(l_out, alarm, right, 2);write(l_out, clk0, right, 2);write(l_out, clk1, right, 2);write(l_out, display_th, right, 5);write(l_out, display_tl, right, 5);write(l_out, dry, right, 2);write(l_out, dry_th, right, 5);write(l_out, dry_tl, right, 5);write(l_out, im_th, right, 5);write(l_out, im_tl, right, 5);write(l_out, immersion, right, 2);write(l_out, poweroff, right, 2);write(l_out, rst, right, 2);write(l_out, voice, right, 2);write(l_out, wash_th, right, 5);write(l_out, wash_tl, right, 5);write(l_out, water_in, right, 2);write(l_out, water_inh, right, 5);write(l_out, water_inl, right, 5);write(l_out, water_out, right, 2);write(l_out, water_outh, right, 5);write(l_out, water_outl, right, 5);write(l_out, z1, right, 2);write(l_out, z2, right, 2);writeline(RESULTS, l_out);end procedure;component xiyijiport (alarm: in std_logic;clk0: in std_logic;clk1: in std_logic;display_th: out std_logic_vector(3 downto 0);display_tl: out std_logic_vector(3 downto 0);dry: out std_logic;dry_th: in std_logic_vector(3 downto 0);dry_tl: in std_logic_vector(3 downto 0);im_th: in std_logic_vector(3 downto 0);im_tl: in std_logic_vector(3 downto 0);immersion: out std_logic;poweroff: out std_logic;rst: in std_logic;voice: out std_logic;wash_th: in std_logic_vector(3 downto 0);wash_tl: in std_logic_vector(3 downto 0);water_in: out std_logic;water_inh: in std_logic_vector(3 downto 0);water_inl: in std_logic_vector(3 downto 0);water_out: out std_logic;water_outh: in std_logic_vector(3 downto 0);water_outl: in std_logic_vector(3 downto 0);z1: out std_logic;z2: out std_logic);end component;signal alarm: std_logic;signal clk0: std_logic;signal clk1: std_logic;signal display_th: std_logic_vector(3 downto 0);signal display_tl: std_logic_vector(3 downto 0);signal dry: std_logic;signal dry_th: std_logic_vector(3 downto 0);signal dry_tl: std_logic_vector(3 downto 0);signal im_th: std_logic_vector(3 downto 0);signal im_tl: std_logic_vector(3 downto 0);signal immersion: std_logic;signal poweroff: std_logic;signal rst: std_logic;signal voice: std_logic;signal wash_th: std_logic_vector(3 downto 0);signal wash_tl: std_logic_vector(3 downto 0);signal water_in: std_logic;signal water_inh: std_logic_vector(3 downto 0);signal water_inl: std_logic_vector(3 downto 0);signal water_out: std_logic;signal water_outh: std_logic_vector(3 downto 0);signal water_outl: std_logic_vector(3 downto 0);signal z1: std_logic;signal z2: std_logic;beginDUT:xiyiji port map (alarm => alarm,clk0 => clk0,clk1 => clk1,display_th => display_th,display_tl => display_tl,dry => dry,dry_th => dry_th,dry_tl => dry_tl,im_th => im_th,im_tl => im_tl,immersion => immersion,poweroff => poweroff,rst => rst,voice => voice,wash_th => wash_th,wash_tl => wash_tl,water_in => water_in,water_inh => water_inh,water_inl => water_inl,water_out => water_out,water_outh => water_outh,water_outl => water_outl,z1 => z1,);STIMULUS0:processbeginalarm <= '0';dry_th <= "1000";dry_tl<= "0000";im_th <= "0000";im_tl <= "0000";wash_th <= "0000";wash_tl <= "0000";water_inh <= "0000";water_inl <= "0000";water_outh <= "0000";water_outl <= "0000";rst <= '1';wait for 10ns;rst <= '0';wait for 1000ns;alarm <= '1';wait;end process;processbeginclk0 <= '1';clk1 <= '1';wait for 1ns;clk0 <= '0';clk1 <= '0';wait for 1ns;end process;WRITE_RESULTS(alarm,clk0,clk1,display_th,display_tl,dry,dry_th,dry_tl,im_th,im_tl,immersion,poweroff,rst,voice,wash_th,wash_tl,water_in,water_inh,water_inl,water_outh,water_outl,z1,z2);end architecture; 波形图:显示模块:此模块实现将由控制器件产生的时间显示的BCD码与地址选择信号同步的转化成可供LCD显示的ASCII码并同时显示字母WELCOME的功能!VHDL文件:LIBRARY IEEE;USE IEEE.std_Logic_1164.ALL;ENTITY OUTPUT ISPORT(R, CP, BUSY :IN Std_Logic;-----使能输入端,脉冲输入端,输入信号忙输入端--------LINE_OUT,STROBE,RST:OUT STD_LOGIC;------行选择输出端,输入数据使能输出端,复位输出端--- TIME_IN :IN STD_LOGIC_VECTOR(7 DOWNTO 0);--------输入时间-----------ADDR_OUT :OUT Std_Logic_Vector( 3DOWNTO 0);--------地址输出端----------DATA_OUT : OUT Std_Logic_Vector(7 DOWNTO 0));-----数据输出端---------END OUTPUT;ARCHITECTURE XS OF OUTPUT ISTYPE State_type IS(S0,S1,S2,S3,S4);SIGNAL S :State_Type;SIGNAL LCDPT:INTEGER RANGE 0 TO 9;BEGINPROCESS(CP,R)BEGINIF R='1' THENS<=S0;LCDPT<=0;RST<='1';ELSIF CP='1' AND CP 'EVENT THENCASE S ISWHEN S0=> S<=S1;LCDPT<=0;RST<='1';WHEN S1=> RST<='0';STROBE<='0';IF BUSY='0' THENLCDPT<=LCDPT+1;IF LCDPT=8 THENS<=S3;ELSES<=S2;END IF;END IF;WHEN S2=> S<=S1;STROBE<='1';WHEN S3=> STROBE<='0';IF BUSY='0' THENIF LCDPT=9 THENLCDPT<=8;LCDPT<=LCDPT+1;END IF;S<=S4;END IF;WHEN S4=> STROBE<='1';S<=S3;WHEN OTHERS=> NULL;END CASE;END IF;END PROCESS;PROCESS (LCDPT)BEGINCASE LCDPT ISWHEN 0 => NULL;WHEN 1 => DATA_OUT<="01010111" ; ADDR_OUT<="0011"; LINE_OUT<='0';WHEN 2 => DATA_OUT<="01000101" ; ADDR_OUT<="0100"; LINE_OUT<='0';WHEN 3 => DATA_OUT<="01001100" ; ADDR_OUT<="0101"; LINE_OUT<='0';WHEN 4 => DATA_OUT<="01000011" ; ADDR_OUT<="0110"; LINE_OUT<='0';WHEN 5 => DATA_OUT<="01001111" ; ADDR_OUT<="0111"; LINE_OUT<='0';WHEN 6 => DATA_OUT<="01001101" ; ADDR_OUT<="1000"; LINE_OUT<='0';WHEN 7 => DATA_OUT<="01000101" ; ADDR_OUT<="1001"; LINE_OUT<='0';WHEN 8 => DATA_OUT<="0011"&TIME_IN(7 DOWNTO4);ADDR_OUT<="0101";LINE_OUT<='1';WHEN 9 => DATA_OUT<="0011"&TIME_IN(3 DOWNTO0);ADDR_OUT<="0110";LINE_OUT<='1';END CASE;END PROCESS;END ARCHITECTURE;-------1,2,3,4,5,6,7输入字母WELCOME,8,9输入时间变化----------TEST文件:-- VHDL Testbench for output-- 2009 9 23 16 13 33-- Created by "EditVHDL"-- "Copyright (c) 2002 Altium Limited"------------------------------------------------------------Library IEEE;Use IEEE.std_logic_1164.all;Use IEEE.std_logic_textio.all;Use STD.textio.all;------------------------------------------------------------------------------------------------------------------------entity Testoutput isend Testoutput;------------------------------------------------------------------------------------------------------------------------architecture stimulus of Testoutput isfile RESULTS: TEXT open WRITE_MODE is"results.txt";procedure WRITE_RESULTS(ADDR_OUT: std_logic_vector(3 downto 0);CP: std_logic;DATA_OUT: std_logic_vector(7 downto 0);LINE_OUT: std_logic;Reset: std_logic;RST: std_logic;STROBE: std_logic) isvariable l_out : line;beginwrite(l_out, now, right, 15);write(l_out, ADDR_OUT, right, 5);write(l_out, BUSY, right, 2);write(l_out, CP, right, 2);write(l_out, DATA_OUT, right, 9);write(l_out, LINE_OUT, right, 2);write(l_out, Reset, right, 2);write(l_out, RST, right, 2);write(l_out, STROBE, right, 2);writeline(RESULTS, l_out);end procedure;component outputport (ADDR_OUT: out std_logic_vector(3 downto 0);BUSY: in std_logic;CP: in std_logic;DATA_OUT: out std_logic_vector(7 downto 0);LINE_OUT: out std_logic;Reset: in std_logic;RST: out std_logic;STROBE: out std_logic);end component;signal ADDR_OUT: std_logic_vector(3 downto 0);signal BUSY: std_logic;signal CP: std_logic;signal DATA_OUT: std_logic_vector(7 downto 0);signal LINE_OUT: std_logic;signal Reset: std_logic;signal RST: std_logic;signal STROBE: std_logic;beginDUT:output port map (ADDR_OUT => ADDR_OUT,BUSY => BUSY,CP => CP,DATA_OUT => DATA_OUT,LINE_OUT => LINE_OUT,Reset => Reset,RST => RST,STROBE => STROBE);STIMULUS0:processbeginRESET<='1';BUSY <= '0';WAIT FOR 2NS;RESET<='0';WAIT FOR 100NS ;RESET <= '1';WAIT FOR 100NS;wait;end process;PROCESSBEGINCP<='0';WAIT FOR 1NS ;CP<='1';WAIT FOR 1NS;END PROCESS;WRITE_RESULTS(ADDR_OUT,BUSY,CP,DATA_OUT,LINE_OUT,Reset,RST,STROBE);end architecture; 波形图:模块运用了器件库里的LCD显示器件:1、模块运用AD6现有资源，由晶振产生的10MHZ的基准时钟和分频器CDIV可将基准时钟分频，即后续模块所需要的不同频率脉冲及LCD(CLK0)控制器时钟.心得体会本次课程设计是一个很好的锻炼机会。
