-+-VSUCC28950 SLUSA16A–MARCH2010–REVISED JULY2010 Green Phase-Shifted Full-Bridge Controller With Synchronous RectificationCheck for Samples:UCC28950FEATURES APPLICATIONS•Phase-Shifted Full-Bridge Converters •Enhanced Wide Range Resonant Zero VoltageSwitching(ZVS)Capability•Server,Telecom Power Supplies•Industrial Power Systems•Direct Synchronous Rectifier(SR)Control•High-Density Power Architectures•Light-Load Efficiency Management Including•Solar Inverters,and Electric Vehicles –Burst Mode Operation–Discontinuous Conduction Mode(DCM),DESCRIPTIONDynamic SR On/Off Control withProgrammable Threshold The UCC28950enhanced phase-shifted controllerbuilds upon Texas Instrument’s industry standard –Programmable Adaptive DelayUCCx895phase-shifted controller family with •Average or Peak Current Mode Control with enhancements that offer best in class efficiency in Programmable Slope Compensation and today’s high performance power systems.The Voltage Mode Control UCC28950implements advanced control of thefull-bridge along with active control of the •Closed Loop Soft Start and Enable Functionsynchronous rectifier output stage.•Programmable Switching Frequency up to1MHz with Bi-Directional Synchronization The primary-side signals allow programmable delaysto ensure ZVS operation over wide-load current and •(+/-3%)Cycle-by-Cycle Current Limitinput voltage range,while the load current naturally Protection with Hiccup Mode Supporttunes the secondary-side synchronous rectifiers •150-µA Start-Up Current switching delays,maximizing overall system •V DD Under Voltage Lockout efficiency.•Wide Temperature Range-40°C to125°CUCC28950Typical ApplicationPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.UCC28950SLUSA16A–MARCH2010–REVISED DESCRIPTION(CONT.)The UCC28950also offers multiple light-load management features including burst mode and dynamic SR on/off control when transitioning in and out of Discontinuous Current Mode(DCM)operation,ensuring ZVS operation is extended down to much lighter loads.In addition,the UCC28950includes support for peak current along with voltage mode control,programmable switching frequency up to1MHz and a wide set of protection features including cycle-by-cycle current limit, UVLO and thermal shutdown.A90-degree phase-shifted interleaved synchronized operation can be easily arranged between two converters.The UCC28950is available in TSSOP-24package.ORDERING INFORMATIONTEMPERATURE RANGE,T A=PACKAGE TAPE AND REEL QTY.PART NUMBER T J250UCC28950PW -40°C to125°C Plastic24-pin TSSOP(PW)2000UCC28950PWRABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)(2)PARAMETER VALUE UNITInput supply voltage range,V DD(3)-0.4to20.0OUTA,OUTB,OUTC,OUTD,OUTE,OUTF-0.4to VDD+0.4Inputs voltages on DELAB,DELCD,DELEF,SS/EN,DCM,TMIN,RT,SYNC,RSUM,EA+,EA-,-0.4to VREF+COMP,CS,ADEL,ADELEF0.4VOutput voltage on VREF-0.4to5.6ESD rating,HBM2kESD rating,CDM500Continuous total power dissipation See dissipation rating table Operating virtual junction temperature range,T J-40to150Operating ambient temperature range,T A-40to125°C Storage temperature,T stg-65to150Lead temperature(soldering,10sec.)300(1)Stresses beyond those listed under“absolute maximum ratings”may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)These devices are sensitive to electrostatic discharge;follow proper device handling procedures.(3)All voltages are with respect to GND unless otherwise noted.Currents are positive into,negative out of the specified terminal.SeePackaging Section of the datasheet for thermal limitations and considerations of packages.DISSIPATION RATINGS(1)DERATINGPOWER RATINGFACTORR q JC R q JAPACKAGE(°C/W)(°C/W)ABOVE TA =T A<25°C T A=70°C T A=85°C25°CPW18.589.311.2mW/°C 1.12W0.615W0.448W (1)These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of differentpackages.The cooling condition and thermal impedance R q JA of practical design is specific.2Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):UCC28950UCC28950 SLUSA16A–MARCH2010–REVISED JULY2010RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN TYP MAX UNIT Supply voltage range,V DD81217V Operating junction temperature range-40125°C Converter switching frequency setting range,F SW(nom)501000kHz Programmable delay range between OUTA,OUTB and OUTC,OUTD set by301000resistors DELAB and DELCD and parameter K A(1)ns Programmable delay range between OUTA,OUTF and OUTB,OUTE set by301400resistor DELEF,and parameter K EF(1)Programmable DCM range as percentage of voltage at CS(1)5%30% Programmable T MIN range100800ns(1)Verified during characterization only.ELECTRICAL CHARACTERISTICS(1)V DD=12V,T A=T J=-40°C to125°C,C VDD=1µF,C REF=1µF,R AB=22.6kΩ,R CD=22.6kΩ,R EF=13.3kΩ,RSUM=124 kΩ,RMIN=88.7kΩ,RT=59kΩconnected between RT pin and5-V voltage supply to set F SW=100kHz(F OSC=200kHz) (unless otherwise noted).All component designations are from the Typical Application Diagram.PARAMETER TEST CONDITION MIN TYP MAX UNITS Under Voltage Lockout(UVLO)UVLO_RStart threshold 6.757.37.9THUVLO_F Minimum operating voltage6.15 6.77.2VTH after startUVLO_HHysteresis0.530.60.75YSTSupply CurrentsI DD(off)Startup current V DD is5.2V150270µAI DD Operating supply current510mA VREF Output VoltageV REF VREF total output range0≤IR≤20mA;V DD=from8V to17V 4.9255 5.075V ISCC Short circuit current VREF=0V-53-23mA Switching Frequency(½of internal oscillator frequency F OSC)F SW(nom)Total range92100108KHzD MAX Maximum duty cycle95%97% SynchronizationRT=59kΩbetween RT and GND;Input pulsesPH SYNC Total range859095°PH200kHz,D=0.5at SYNCRT=59kΩbetween RT and5V;-40°C≤T J≤F SYNC Total range180200220kHz125°CT PW Pulse width 2.2 2.5 2.8µs (1)Typical values for T A=25°CCopyright©2010,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):UCC28950UCC28950SLUSA16A–MARCH2010–REVISED ELECTRICAL CHARACTERISTICS(1)(continued)V DD=12V,T A=T J=-40°C to125°C,C VDD=1µF,C REF=1µF,R AB=22.6kΩ,R CD=22.6kΩ,R EF=13.3kΩ,RSUM=124 kΩ,RMIN=88.7kΩ,RT=59kΩconnected between RT pin and5-V voltage supply to set F SW=100kHz(F OSC=200kHz) (unless otherwise noted).All component designations are from the Typical Application Diagram.PARAMETER TEST CONDITION MIN TYP MAX UNITS Error AmplifierV ICM range ensures parameters,the functionalityCommon mode input voltageV ICM ensured for3.6V<V ICM<VREF+0.4V,and-0.40.5 3.6V rangeV<V ICM<0.5VV IO Offset voltage-77mVI BIAS Input bias current-11µAEA HIGH High-level output voltage(EA+)-(EA-)=500mV,I EAOUT=-0.5mA 3.9 4.25VEA LOW Low-level output voltage(EA+)-(EA-)=-500mV,I EAOUT=0.5mA0.250.35I SOURCE Error amplifier source current-8-3.75-0.5mAI SINK Error amplifier sink current 2.7 4.6 5.75I VOL Open-loop dc gain100dB GBW Unity gain bandwidth(2)3MHz Cycle-by-Cycle Current LimitCS pin cycle-by-cycleV CS_LIM 1.942 2.06V thresholdPropagation delay from CS to Input pulse between CS and GND from zero to2.5T CS100ns OUTC and OUTD outputs VInternal Hiccup Mode SettingsDischarge current to setI DS cycle-by-cycle current limit CS=2.5V,VSS=4V152025µAdurationV HCC Hiccup OFF Time threshold 3.2 3.6 4.2VDischarge current to setI HCC 1.90 2.55 3.2µAHiccup Mode OFF TimeSoft Start/EnableI SS Charge current V SS=0V202530µAShutdown/restart/resetV SS_STD0.250.500.70 thresholdVV SS_PU Pull up threshold 3.3 3.7 4.3V SS_CL Clamp voltage 4.20 4.65 4.95(2)Verified during characterization only.4Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):UCC28950UCC28950 SLUSA16A–MARCH2010–REVISED JULY2010ELECTRICAL CHARACTERISTICS(1)(continued)V DD=12V,T A=T J=-40°C to125°C,C VDD=1µF,C REF=1µF,R AB=22.6kΩ,R CD=22.6kΩ,R EF=13.3kΩ,RSUM=124 kΩ,RMIN=88.7kΩ,RT=59kΩconnected between RT pin and5-V voltage supply to set F SW=100kHz(F OSC=200kHz) (unless otherwise noted).All component designations are from the Typical Application Diagram.PARAMETER TEST CONDITION MIN TYP MAX UNITS Programmable Delay Time Set Accuracy and Range(3)(4)(5)(6)(7)Short delay time set accuracyT ABSET1CS=ADEL=ADELEF=1.8V324556 between OUTA and OUTBLong delay time set accuracyT ABSET2CS=ADEL=ADELEF=0.2V216270325 between OUTA and OUTBShort delay time set accuracyT CDSET1CS=ADEL=ADELEF=1.8V324556 between OUTC and OUTDLong delay time set accuracyT CDSET2CS=ADEL=ADELEF=0.2V216270325 between OUTC and OUTDShort delay time set accuracyT AFSET1CS=ADEL=ADELEF=0.2V223548 between falling OUTA,OUTFLong delay time set accuracyT AFSET2CS=ADEL=ADELEF=1.8V190240290 between falling OUTA,OUTFShort delay time set accuracyT BESET1CS=ADEL=ADELEF=0.2V223548 between falling OUTB,OUTE nsLong delay time set accuracyT BESET2CS=ADEL=ADELEF=1.8V190240290 between falling OUTB,OUTEPulse matching betweenΔT ADBC OUTA rise,OUTD fall and CS=ADEL=ADELEF=1.8V,COMP=2V-50050 OUTB rise,OUTC fallHalf cycle matching betweenΔT ABBA OUTA rise,OUTB rise and CS=ADEL=ADELEF=1.8V,COMP=2V-50050 OUTB rise,OUTA risePulse matching betweenΔT EEFF OUTE fall,OUTE rise and CS=ADEL=ADELEF=0.2V,COMP=2V-60060 OUTF fall,OUTF risePulse matching betweenΔT EFFE OUTE fall,OUTF rise and CS=ADEL=ADELEF=0.2V,COMP=2V-60060 OUTF fall,OUTE rise(3)See Figure3for timing diagram and T ABSET1,T ABSET2,T CDSET1,T CDSET2definitions.(4)See Figure6for timing diagram and T AFSET1,T AFSET2,T BESET1,T BESET2definitions.(5)Pair of outputs OUTC,OUTE and OUTD,OUTF always going high simultaneously.(6)Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.(7)All delay settings are measured relatively50%of pulse amplitude.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):UCC28950UCC28950SLUSA16A–MARCH2010–REVISED ELECTRICAL CHARACTERISTICS(1)(continued)V DD=12V,T A=T J=-40°C to125°C,C VDD=1µF,C REF=1µF,R AB=22.6kΩ,R CD=22.6kΩ,R EF=13.3kΩ,RSUM=124 kΩ,RMIN=88.7kΩ,RT=59kΩconnected between RT pin and5-V voltage supply to set F SW=100kHz(F OSC=200kHz) (unless otherwise noted).All component designations are from the Typical Application Diagram.PARAMETER TEST CONDITION MIN TYP MAX UNITS Light Load Efficiency CircuitV DCM=0.4V,Sweep CS confirm there are OUTEDCM threshold,T=25°C0.370.390.41and OUTF pulsesDCM threshold,T=0°C to V DCM=0.4V,Sweep CS,confirm there are OUTEV DCM0.3640.3900.416V 85°C(8)and OUTF pulsesDCM threshold,T=-40°C to V DCM=0.4V,Sweep CS,confirm there are OUTE0.350.390.43125°C(8)and OUTF pulsesI DCM,SRC DCM Sourcing Current CS<DCM threshold142026µAT MIN Total range R TMIN=88.7kΩ425525625ns OUTPUTS OUTA,OUTB,OUTC,OUTD,OUTE,OUTFI SINK/SRC Sink/Source peak current(8)0.2AT R Rise time C LOAD=100pF925nsT F Fall time C LOAD=100pF725R SRC Output source resistance I OUT=20mA102035ΩR SINK Output sink resistance I OUT=20mA51030 THERMAL SHUTDOWNRising threshold(8)160Falling threshold(8)140°CHysteresis20(8)Verified during characterization only.6Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):UCC28950UCC28950 SLUSA16A–MARCH2010–REVISED JULY2010DEVICE INFORMATIONTERMINAL FUNCTIONSTERMINALI/O FUNCTIONNUMBER NAME1VREF O5-V,±1.5%,20-mA reference voltage output.2EA+I Error amplifier non-inverting input.3EA-I Error amplifier inverting input.4COMP I/O Error amplifier output and input to the PWM comparator.5SS/EN I Soft-start programming,device enable and hiccup mode protection circuit.6DELAB I Dead-time delay programming between OUTA and OUTB.7DELCD I Dead-time delay programming between OUTC and OUTD.8DELEF I Delay-time programming between OUTA to OUTF,and OUTB to OUTE.9TMIN I Minimum duty cycle programming in burst mode.10RT I Oscillator frequency set.Master or slave mode setting.11RSUM I Slope compensation programming.Voltage mode or peak current mode setting.12DCM I DCM threshold setting.Delay-time programming between primary side and secondary side switches,T AFSET 13ADELEF Iand T BESET.Dead-time programming for the primary switches over CS voltage range,T ABSET and 14ADEL IT CDSET.15CS I Current sense for cycle-by-cycle over-current protection and adaptive delay functions.16SYNC I/O Synchronization out from Master controller to input of slave controller.17OUTF O0.2-A sink/source synchronous switching output.18OUTE O0.2-A sink/source synchronous switching output.19OUTD O0.2-A sink/source primary switching output.20OUTC O0.2-A sink/source primary switching output.21OUTB O0.2-A sink/source primary switching output.22OUTA O0.2-A sink/source primary switching output.23VDD I Bias supply input.24GND Ground.All signals are referenced to this node.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):UCC28950VDD VREFOUTADELABOUTBADEL OUTCDELCDOUTDOUTEDELEFOUTFADELEFSS/ENCOMP EA-EA+RT RSUM CS SYNCGNDDCMTMIN-V S UCC28950SLUSA16A –MARCH 2010–REVISED JULY 2010Functional Block DiagramTypical Application Diagram8Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):UCC28950UCC28950 SLUSA16A–MARCH2010–REVISED JULY2010Startup Timing DiagramNo output delay shown,COMP-to-RAMP offset not included.Figure1.UCC28950Timing DiagramNOTEThere is no pulse on OUTE during burst mode at startup.Two falling edge PWM pulsesare required before enabling the synchronous rectifier outputs.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):UCC28950UCC28950SLUSA16A–MARCH2010–REVISED Steady State/Shutdown Timing DiagramNo output delay shown,COMP-to-RAMP offset not included.Figure2.UCC28950Timing Diagram10Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):UCC28950DETAILED PIN DESCRIPTION AND PARAMETER SETTINGSStart-Up Protection LogicBefore the UCC28950controller will start up,the following conditions must be met:•VDD voltage exceeds rising UVLO threshold7.3V typical.•The5-V reference voltage is available.•Junction temperature is below the thermal shutdown threshold of140°C.•The voltage on the soft-start capacitor is not below0.55V typical.If all those conditions are met,an internal enable signal EN is generated that initiates the soft start process.The duty cycle during the soft start is defined by the voltage at the SS pin,and cannot be lower than the duty cycle set by TMIN,or by cycle-by-cycle current limit circuit depending on load conditions.Voltage Reference(VREF)The accurate(±1.5%)5-V reference voltage regulator with the short circuit protection circuit supplies internal circuitry and provides up to20-mA external output current for setting DC/DC converter parameters.Place low ESR and ESL,preferably ceramic decoupling capacitor C REF in1µF to2.2µF range from this pin to GND as close to the related pins as possible for best performance.The only condition where the reference regulator is shut down internally is during under voltage lockout.Error Amplifier(EA+,EA-,COMP)The error amplifier has two uncommitted inputs,EA+and EA-,with a3-MHz unity bandwidth,which allows flexibility in closing the feedback loop.The EA+is a non-inverting input,the EA-is an inverting input and the COMP is the output of the error amplifier.The input voltage common mode range,where the parameters of error amplifier are guaranteed,is from0.5V to3.6V.The output of the error amplifier is connected internally to the non-inverting input of the PWM comparator.The range of the error amplifier output of0.25V to4.25V far exceeds the PWM comparator input ramp-signal range,which is from0.8V to2.8V.The soft-start signal serves as an additional non-inverting input of the error amplifier.The lower of the two non-inverting inputs of the error amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared with the internal ramp at the inputs of the PWM comparator.()SS SS(master )T 25A C VNI 0.55´m =+SSSS(slave)T C 20.6825K Ln 20.6VNI 0.55=æö´ç÷--èøSoft Start and Enable (SS/EN)The soft-start pin SS/EN is a multi-function pin used for the following operations:•Closed loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady state duty cycle required by the regulated output voltage.•Setting hiccup mode conditions during cycle-by-cycle over current limit.•On/off control for the converter.During soft start,one of the voltages at the SS/EN or EA+pins,whichever is lower (SS/EN -0.55V)or EA+voltage (see Block Diagram),sets the reference voltage for a closed feedback loop.Both SS/EN and EA+signals are non-inverting inputs of the error amplifier with the COMP pin being its output.Thus the soft start always goes under the closed feedback loop and the voltage at COMP pin sets the duty cycle.The duty cycle defined by COMP voltage can not be shorter than TMIN pulse set by the user.However,if the shortest duty cycle is set by the cycle-by-cycle current limit circuit,then it becomes dominant over the duty cycle defined by COMP voltage or by TMIN block.The soft-start duration is defined by an external capacitor C SS ,connected between SS/EN pin and ground,and the internal charge current that has typical value of 25µA.Pulling the soft-start pin externally below 0.55V shuts down the controller.The release of the soft-start pin enables the controller to start,and if there is no current limit condition,the duty cycle applied to the output inductor gradually increases until it reaches the steady state duty cycle defined by the regulated output voltage of the converter.This happens when the voltage at the SS/EN pin reaches and then exceeds the voltage at EA+pin defined as VNI by 0.55V.Thus for the given soft-start time T SS ,the C SS value can be defined by Equation 1or Equation 2:(1)(2)For example,in Equation 1,if the soft-start time T SS is selected to be 10ms,and the VNI is 2.5V,then the soft-start capacitor C SS is equal to 82-nF.NOTEIf the converter is configured in Slave Mode,make sure you place an 825-k Ωresistor from SS pin to ground.Light-Load Power Saving ModeThe UCD28950offers four different light-load management techniques for improving the efficiency of a power converter over a wide load current range.1.Adaptive Delay,(a)ADEL,which sets and optimizes the dead-time control for the primary switches over wide load currentrange.(b)ADELEF,which sets and optimizes the delay-time control between the primary side switches and thesecondary side switches.2.TMIN,sets the minimum duty cycle as long as the part is not in current limit mode.3.Dynamic synchronous rectifier on/off control in DCM Mode,For increased efficiency at loads.The DCM Mode starts when the voltage at CS pin is lower than the threshold set by the user.In DCM Mode,the synchronous output drive signals OUTE and OUTF are brought down low.4.Burst Mode,for maximum efficiency at very light loads or no load.Burst Mode has an even number of PWM TMIN pulses followed by off time.Transition to the Burst Mode is defined by the TMIN duration set by the user.Adaptive Delay,(Delay between OUTA and OUTB,OUTC and OUTD(DELAB,DELCD,ADEL)) The resistor R AB from the DELAB pin,DELAB to GND,along with the resistor divider R AHI from CS pin to ADEL pin and R A from ADEL pin to GND sets the delay T ABSET between one of outputs OUTA or OUTB going low and another output going high Figure3.Figure3.Delay definitions between OUTA and OUTB,OUTC and OUTDThis delay gradually increases as a function of the CS signal from T ABSET1,which is measured at V CS=1.8V,to T ABSET2,which is measured at the V CS=0.2V.This approach ensures there will be no shoot-through current during the high-side and low-side MOSFET switching and optimizes the delay for ZVS condition over a wide load current range.Depending on the resistor divider R AHI and R A,the proportional ratio between longest and shortest delay is set.The max ratio is achieved by tying the CS and ADEL pins together.If ADEL is connected to GND, then the delay is fixed,defined only by the resistor R AB from DELAB to GND.The delay T CDSET1and T CDSET2 settings and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB.The difference is that resistor R CD connected between DELCD pin and GND sets the delay T CDSET. Delays for outputs OUTC and OUTD share with the outputs OUTA and OUTB the same CS voltage dependence pin ADEL.ABABSET A 5R T ns 5ns0.15V CS K 1.46æö´=+ç÷+´´èøCDCDSET A 5R T ns 5ns0.15V CS K 1.46æö´=+ç÷+´´èøAA A AHIR K R R =+The delay time T ABSET is defined by the following Equation 3.(3)The same equation is used to define the delay time T CDSET in another leg except R AB is replaced by R CD .(4)In these equations R AB and R CD are in k Ωand CS,the voltage at pin CS,is in volts and K A is a numerical coefficient in the range from 0to 1.The delay time T ABSET and T CDSET are in ns.These equations are empirical and they are approximated from measured data.Thus,there is no unit agreement in the equations.As an example,assume R AB =15k Ω,CS =1V and K A =0.5.Then the T ABSET is going to be 90.25ns.In both Equation 3and Equation 4,K A is the same and is defined as:(5)K A sets how the delay is sensitive to CS voltage variation.If K A =0(ADEL shorted to GND),the delay is fixed.If K A =1(ADEL is tied to CS),the delay is maximum at CS =0.2V and gradually decreases when CS goes up to 1.8V.The ratio between the maximum and minimum delay can be up to 6:1.It is recommended to start by setting K A =0and set T ABSET and T CDSET relatively large using equations or plots in the data sheet to avoid hard switching or even shoot through current.The delay between outputs A,B and C,D set by resistors R AB and R CS accordingly.Program the optimal delays at light load first.Then by changing K A set the optimal delay for the outputs A,B at maximum current.K A for outputs C,D is the same as for A,ually outputs C,D always have ZVS if sufficient delay is provided.NOTEThe allowed resistor range on DELAB and DELCD,R AB and R CD are 13k Ωto 90k Ω.0.02.0CS Voltage -V350 1.0T A B S E T ,T C D S E T -T i m e D e l a y -n sTIME DELAY (R AB =R CD =13k W )vsCS VOLTAGE3001005250150502000.20.40.60.81.21.41.61.8K A =0.0K A =0.1K A =0.25K A =0.50K A =0.75K A =1.00.02.0CS Voltage -V2000 1.0T A B S E T ,T C D S E T -T i m e D e l a y -n sTIME DELAY (R AB =R CD =90k W )vsCS VOLTAGE180060001600100020012000.20.40.60.81.21.41.61.8K A =0.0K A =0.1K A =0.25K A =0.50K A =0.75K A =1.01400800400R A and R AHI define the portion of voltage at pin CS applied to the pin ADEL (See Typical Application Diagram).K A defines how significantly the delay time depends on CS voltage.Ka varies from 0,where ADEL pin is shorted to ground (R A =0)and the delay does not depend on CS voltage,to 1,where ADEL is tied to CS (R AH =0).Setting K A ,R AB and R CD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the voltage at CS pin includes reflected load current to primary side through the current sensing circuit.The plots in Figure 4and Figure 5show the delay time settings as a function of CS voltage and K A for two different conditions:R AB =R CD =13k Ω(Figure 4)and R AB =R CD =90k Ω(Figure 5).Figure 4.Delay Time Set T ABSET and T CDSET(Over CS voltage variation and selected K A for R AB and R CD equal 13k Ω)Figure 5.Delay time set T ABSET and T CDSET(Over CS voltage variation and selected K A for R AB and R CD equal 90k Ω)EFAFSET EF 5R T ns 4ns 2.65V CS K 1.32æöæö´=+ç÷ç÷ç÷-´´èøèøAEFEF AEF AEF(hi)R K R R =+Adaptive Delay (Delay between OUTA and OUTF,OUTB and OUTE (DELEF,ADELEF ))The resistor R EF from the DELEF pin to GND along with the resistor divider R AEFHI from CS pin to ADELEF pin and R AEF from ADELEF pin to GND sets equal delays T AFSET and T BESET between outputs OUTA or OUTB going low and related output OUTF or OUTE going low Figure 6.Figure 6.Delay Definitions Between OUTA and OUTF,OUTB and OUTEThese delays gradually increase as function of CS signal from T AFSET1,which is measured at V CS =0.2V,to T AFSET2,which is measured at V CS =1.8V.Opposite to the DELAB and DELCD behaviour,this delay is longest (T AFSET2)when the signal at CS pin is maximized and shortest (T AFSET1)when the CS signal is minimized.This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide load current range thus improving efficiency and reducing diode recovery time.Depending on the resistor divider R AEFHI and R AEF ,the proportional ratio between longest and shortest delay is set.If CS and ADELEF are tied,the ratio is maximized.If ADELEF is connected to GND,then the delay is fixed,defined only by resistor R EF from DELEF to GND.The delay time T AFSET is defined by the following Equation 6.The same defines the delay time T BESET .(6)In this equation R EF is in k Ω,the CS,which is the voltage at pin CS,is in volts and K EF is a numerical gain factorof CS voltage from 0to 1.The delay time T AFSET is in ns.This equation is empirical approximation of measured data,thus,there is no unit agreement in it.As an example of calculation,assume R EF =15k Ω,CS =1V and K EF =0.5.Then the T AFSET is going to be 41.7ns.K EF is defined as:(7)R AEF and R AEFHI define the portion of voltage at pin CS applied to the pin ADELEF (See Typical Application Diagram ).K EF defines how significantly the delay time depends on CS voltage.K EF varies from 0,where ADELEF pin is shorted to ground (R AEF =0)and the delay does not depend on CS voltage,to 1,where ADELEF is tied to CS (R AEFHI =0).NOTEThe allowed resistor range on DELEF,R EF is 13k Ωto 90k Ω.。
