下载文档原格式
扫码注册平头哥OCC 官网观看各类视频及课程阿里云开发者“藏经阁”海量电子手册免费下载平头哥芯片开放社区交流群扫码关注获取更多信息平头哥RISC-V 系列课程培训扫码登录在线学习目录RISC-V处理器架构 (5)1.RISC-V架构起源 (5)2.RISC-V架构发展 (5)3.RISC-V架构与X86、ARM在商业模式上的区别 (6)4.RISC-V架构现状和未来 (7)5.RISC-V处理器课程学习 (9)平头哥玄铁CPU IP (10)1.概述 (10)2.面向低功耗领域CPU (10)3.面向中高端服务器CPU (16)4.面向高性能领域CPU (23)5.玄铁CPU课程学习 (26)无剑平台 (27)1.无剑100开源SoC平台 (27)2.无剑600SoC平台 (28)平头哥RISC-V工具链 (34)1.RISC-V工具链简介 (34)2.剑池CDK开发工具 (37)3.玄铁CPU调试系统 (44)4.HHB (51)5.剑池CDK开发工具课程学习 (54)平头哥玄铁CPU系统 (55)1.YoC (55)2.Linux (56)3.Android (62)RISC-V玄铁系列开发板实践 (67)1.基于玄铁C906处理器的D1Dock Pro开发实践 (67)2.基于玄铁E906处理器的RVB2601开发实践 (82)RISC-V应用领域开发示例 (100)1.基于D1Dock Pro应用开发示例 (100)2.基于RVB2601应用开发示例 (106)RISC-V未来探索 (116)1.平头哥开源RISC-V系统处理器 (116)2.平头哥对RISC-V基金会贡献 (117)3.高校合作 (117)RISC-V处理器架构1.RISC-V架构起源RISC-V架构是一种开源的指令集架构。
最早是由美国伯克利大学的Krest教授及其研究团队提出的，当时提出的初衷是为了计算机/电子类方向的学生做课程实践服务的。
MIPS32™ Architecture For Programmers Volume I: Introduction to the MIPS32™ArchitectureDocument Number: MD00082Revision 2.00June 8, 2003MIPS Technologies, Inc.1225 Charleston RoadMountain View, CA 94043-1353Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Copyright ©2001-2003 MIPS Technologies, Inc. All rights reserved.Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.This document contains information that is proprietary to MIPS Technologies, Inc. ("MIPS Technologies"). Any copying,reproducing,modifying or use of this information(in whole or in part)that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited. At a minimum, this information is protected under unfair competition and copyright laws. Violations thereof may result in criminal penalties and fines.Any document provided in source format(i.e.,in a modifiable form such as in FrameMaker or Microsoft Word format) is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions. UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES, INC.MIPS Technologies reserves the right to change the information contained in this document to improve function,design or otherwise.MIPS Technologies does not assume any liability arising out of the application or use of this information, or of any error or omission in such information. Any warranties, whether express, statutory, implied or otherwise, including but not limited to the implied warranties of merchantability orfitness for a particular purpose,are excluded. Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party,the furnishing of this document does not give recipient any license to any intellectual property rights,including any patent rights, that cover the information in this document.The information contained in this document shall not be exported or transferred for the purpose of reexporting in violation of any U.S. or non-U.S. regulation, treaty, Executive Order, law, statute, amendment or supplement thereto. The information contained in this document constitutes one or more of the following: commercial computer software, commercial computer software documentation or other commercial items.If the user of this information,or any related documentation of any kind,including related technical data or manuals,is an agency,department,or other entity of the United States government ("Government"), the use, duplication, reproduction, release, modification, disclosure, or transfer of this information, or any related documentation of any kind, is restricted in accordance with Federal Acquisition Regulation12.212for civilian agencies and Defense Federal Acquisition Regulation Supplement227.7202 for military agencies.The use of this information by the Government is further restricted in accordance with the terms of the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party.MIPS,R3000,R4000,R5000and R10000are among the registered trademarks of MIPS Technologies,Inc.in the United States and other countries,and MIPS16,MIPS16e,MIPS32,MIPS64,MIPS-3D,MIPS-based,MIPS I,MIPS II,MIPS III,MIPS IV,MIPS V,MIPSsim,SmartMIPS,MIPS Technologies logo,4K,4Kc,4Km,4Kp,4KE,4KEc,4KEm,4KEp, 4KS, 4KSc, 4KSd, M4K, 5K, 5Kc, 5Kf, 20Kc, 25Kf, ASMACRO, ATLAS, At the Core of the User Experience., BusBridge, CoreFPGA, CoreLV, EC, JALGO, MALTA, MDMX, MGB, PDtrace, Pipeline, Pro, Pro Series, SEAD, SEAD-2, SOC-it and YAMON are among the trademarks of MIPS Technologies, Inc.All other trademarks referred to herein are the property of their respective owners.Template: B1.08, Built with tags: 2B ARCH MIPS32MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table of ContentsChapter 1 About This Book (1)1.1 Typographical Conventions (1)1.1.1 Italic Text (1)1.1.2 Bold Text (1)1.1.3 Courier Text (1)1.2 UNPREDICTABLE and UNDEFINED (2)1.2.1 UNPREDICTABLE (2)1.2.2 UNDEFINED (2)1.3 Special Symbols in Pseudocode Notation (2)1.4 For More Information (4)Chapter 2 The MIPS Architecture: An Introduction (7)2.1 MIPS32 and MIPS64 Overview (7)2.1.1 Historical Perspective (7)2.1.2 Architectural Evolution (7)2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures (9)2.2 Compliance and Subsetting (9)2.3 Components of the MIPS Architecture (10)2.3.1 MIPS Instruction Set Architecture (ISA) (10)2.3.2 MIPS Privileged Resource Architecture (PRA) (10)2.3.3 MIPS Application Specific Extensions (ASEs) (10)2.3.4 MIPS User Defined Instructions (UDIs) (11)2.4 Architecture Versus Implementation (11)2.5 Relationship between the MIPS32 and MIPS64 Architectures (11)2.6 Instructions, Sorted by ISA (12)2.6.1 List of MIPS32 Instructions (12)2.6.2 List of MIPS64 Instructions (13)2.7 Pipeline Architecture (13)2.7.1 Pipeline Stages and Execution Rates (13)2.7.2 Parallel Pipeline (14)2.7.3 Superpipeline (14)2.7.4 Superscalar Pipeline (14)2.8 Load/Store Architecture (15)2.9 Programming Model (15)2.9.1 CPU Data Formats (16)2.9.2 FPU Data Formats (16)2.9.3 Coprocessors (CP0-CP3) (16)2.9.4 CPU Registers (16)2.9.5 FPU Registers (18)2.9.6 Byte Ordering and Endianness (21)2.9.7 Memory Access Types (25)2.9.8 Implementation-Specific Access Types (26)2.9.9 Cache Coherence Algorithms and Access Types (26)2.9.10 Mixing Access Types (26)Chapter 3 Application Specific Extensions (27)3.1 Description of ASEs (27)3.2 List of Application Specific Instructions (28)3.2.1 The MIPS16e Application Specific Extension to the MIPS32Architecture (28)3.2.2 The MDMX Application Specific Extension to the MIPS64 Architecture (28)3.2.3 The MIPS-3D Application Specific Extension to the MIPS64 Architecture (28)MIPS32™ Architecture For Programmers Volume I, Revision 2.00i Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.3.2.4 The SmartMIPS Application Specific Extension to the MIPS32 Architecture (28)Chapter 4 Overview of the CPU Instruction Set (29)4.1 CPU Instructions, Grouped By Function (29)4.1.1 CPU Load and Store Instructions (29)4.1.2 Computational Instructions (32)4.1.3 Jump and Branch Instructions (35)4.1.4 Miscellaneous Instructions (37)4.1.5 Coprocessor Instructions (40)4.2 CPU Instruction Formats (41)Chapter 5 Overview of the FPU Instruction Set (43)5.1 Binary Compatibility (43)5.2 Enabling the Floating Point Coprocessor (44)5.3 IEEE Standard 754 (44)5.4 FPU Data Types (44)5.4.1 Floating Point Formats (44)5.4.2 Fixed Point Formats (48)5.5 Floating Point Register Types (48)5.5.1 FPU Register Models (49)5.5.2 Binary Data Transfers (32-Bit and 64-Bit) (49)5.5.3 FPRs and Formatted Operand Layout (50)5.6 Floating Point Control Registers (FCRs) (50)5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0) (51)5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31) (53)5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25) (55)5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26) (56)5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28) (56)5.7 Formats of Values Used in FP Registers (57)5.8 FPU Exceptions (58)5.8.1 Exception Conditions (59)5.9 FPU Instructions (62)5.9.1 Data Transfer Instructions (62)5.9.2 Arithmetic Instructions (63)5.9.3 Conversion Instructions (65)5.9.4 Formatted Operand-Value Move Instructions (66)5.9.5 Conditional Branch Instructions (67)5.9.6 Miscellaneous Instructions (68)5.10 Valid Operands for FPU Instructions (68)5.11 FPU Instruction Formats (70)5.11.1 Implementation Note (71)Appendix A Instruction Bit Encodings (75)A.1 Instruction Encodings and Instruction Classes (75)A.2 Instruction Bit Encoding Tables (75)A.3 Floating Point Unit Instruction Format Encodings (82)Appendix B Revision History (85)ii MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Figure 2-1: Relationship between the MIPS32 and MIPS64 Architectures (11)Figure 2-2: One-Deep Single-Completion Instruction Pipeline (13)Figure 2-3: Four-Deep Single-Completion Pipeline (14)Figure 2-4: Four-Deep Superpipeline (14)Figure 2-5: Four-Way Superscalar Pipeline (15)Figure 2-6: CPU Registers (18)Figure 2-7: FPU Registers for a 32-bit FPU (20)Figure 2-8: FPU Registers for a 64-bit FPU if Status FR is 1 (21)Figure 2-9: FPU Registers for a 64-bit FPU if Status FR is 0 (22)Figure 2-10: Big-Endian Byte Ordering (23)Figure 2-11: Little-Endian Byte Ordering (23)Figure 2-12: Big-Endian Data in Doubleword Format (24)Figure 2-13: Little-Endian Data in Doubleword Format (24)Figure 2-14: Big-Endian Misaligned Word Addressing (25)Figure 2-15: Little-Endian Misaligned Word Addressing (25)Figure 3-1: MIPS ISAs and ASEs (27)Figure 3-2: User-Mode MIPS ISAs and Optional ASEs (27)Figure 4-1: Immediate (I-Type) CPU Instruction Format (42)Figure 4-2: Jump (J-Type) CPU Instruction Format (42)Figure 4-3: Register (R-Type) CPU Instruction Format (42)Figure 5-1: Single-Precisions Floating Point Format (S) (45)Figure 5-2: Double-Precisions Floating Point Format (D) (45)Figure 5-3: Paired Single Floating Point Format (PS) (46)Figure 5-4: Word Fixed Point Format (W) (48)Figure 5-5: Longword Fixed Point Format (L) (48)Figure 5-6: FPU Word Load and Move-to Operations (49)Figure 5-7: FPU Doubleword Load and Move-to Operations (50)Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR (50)Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR (50)Figure 5-10: Paired-Single Floating Point Operand in an FPR (50)Figure 5-11: FIR Register Format (51)Figure 5-12: FCSR Register Format (53)Figure 5-13: FCCR Register Format (55)Figure 5-14: FEXR Register Format (56)Figure 5-15: FENR Register Format (56)Figure 5-16: Effect of FPU Operations on the Format of Values Held in FPRs (58)Figure 5-17: I-Type (Immediate) FPU Instruction Format (71)Figure 5-18: R-Type (Register) FPU Instruction Format (71)Figure 5-19: Register-Immediate FPU Instruction Format (71)Figure 5-20: Condition Code, Immediate FPU Instruction Format (71)Figure 5-21: Formatted FPU Compare Instruction Format (71)Figure 5-22: FP RegisterMove, Conditional Instruction Format (71)Figure 5-23: Four-Register Formatted Arithmetic FPU Instruction Format (72)Figure 5-24: Register Index FPU Instruction Format (72)Figure 5-25: Register Index Hint FPU Instruction Format (72)Figure 5-26: Condition Code, Register Integer FPU Instruction Format (72)Figure A-1: Sample Bit Encoding Table (76)MIPS32™ Architecture For Programmers Volume I, Revision 2.00iii Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 1-1: Symbols Used in Instruction Operation Statements (2)Table 2-1: MIPS32 Instructions (12)Table 2-2: MIPS64 Instructions (13)Table 2-3: Unaligned Load and Store Instructions (24)Table 4-1: Load and Store Operations Using Register + Offset Addressing Mode (30)Table 4-2: Aligned CPU Load/Store Instructions (30)Table 4-3: Unaligned CPU Load and Store Instructions (31)Table 4-4: Atomic Update CPU Load and Store Instructions (31)Table 4-5: Coprocessor Load and Store Instructions (31)Table 4-6: FPU Load and Store Instructions Using Register+Register Addressing (32)Table 4-7: ALU Instructions With an Immediate Operand (33)Table 4-8: Three-Operand ALU Instructions (33)Table 4-9: Two-Operand ALU Instructions (34)Table 4-10: Shift Instructions (34)Table 4-11: Multiply/Divide Instructions (35)Table 4-12: Unconditional Jump Within a 256 Megabyte Region (36)Table 4-13: PC-Relative Conditional Branch Instructions Comparing Two Registers (36)Table 4-14: PC-Relative Conditional Branch Instructions Comparing With Zero (37)Table 4-15: Deprecated Branch Likely Instructions (37)Table 4-16: Serialization Instruction (38)Table 4-17: System Call and Breakpoint Instructions (38)Table 4-18: Trap-on-Condition Instructions Comparing Two Registers (38)Table 4-19: Trap-on-Condition Instructions Comparing an Immediate Value (38)Table 4-20: CPU Conditional Move Instructions (39)Table 4-21: Prefetch Instructions (39)Table 4-22: NOP Instructions (40)Table 4-23: Coprocessor Definition and Use in the MIPS Architecture (40)Table 4-24: CPU Instruction Format Fields (42)Table 5-1: Parameters of Floating Point Data Types (45)Table 5-2: Value of Single or Double Floating Point DataType Encoding (46)Table 5-3: Value Supplied When a New Quiet NaN Is Created (47)Table 5-4: FIR Register Field Descriptions (51)Table 5-5: FCSR Register Field Descriptions (53)Table 5-6: Cause, Enable, and Flag Bit Definitions (55)Table 5-7: Rounding Mode Definitions (55)Table 5-8: FCCR Register Field Descriptions (56)Table 5-9: FEXR Register Field Descriptions (56)Table 5-10: FENR Register Field Descriptions (57)Table 5-11: Default Result for IEEE Exceptions Not Trapped Precisely (60)Table 5-12: FPU Data Transfer Instructions (62)Table 5-13: FPU Loads and Stores Using Register+Offset Address Mode (63)Table 5-14: FPU Loads and Using Register+Register Address Mode (63)Table 5-15: FPU Move To and From Instructions (63)Table 5-16: FPU IEEE Arithmetic Operations (64)Table 5-17: FPU-Approximate Arithmetic Operations (64)Table 5-18: FPU Multiply-Accumulate Arithmetic Operations (65)Table 5-19: FPU Conversion Operations Using the FCSR Rounding Mode (65)Table 5-20: FPU Conversion Operations Using a Directed Rounding Mode (65)Table 5-21: FPU Formatted Operand Move Instructions (66)Table 5-22: FPU Conditional Move on True/False Instructions (66)iv MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Table 5-23: FPU Conditional Move on Zero/Nonzero Instructions (67)Table 5-24: FPU Conditional Branch Instructions (67)Table 5-25: Deprecated FPU Conditional Branch Likely Instructions (67)Table 5-26: CPU Conditional Move on FPU True/False Instructions (68)Table 5-27: FPU Operand Format Field (fmt, fmt3) Encoding (68)Table 5-28: Valid Formats for FPU Operations (69)Table 5-29: FPU Instruction Format Fields (72)Table A-1: Symbols Used in the Instruction Encoding Tables (76)Table A-2: MIPS32 Encoding of the Opcode Field (77)Table A-3: MIPS32 SPECIAL Opcode Encoding of Function Field (78)Table A-4: MIPS32 REGIMM Encoding of rt Field (78)Table A-5: MIPS32 SPECIAL2 Encoding of Function Field (78)Table A-6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture (78)Table A-7: MIPS32 MOVCI Encoding of tf Bit (79)Table A-8: MIPS32 SRL Encoding of Shift/Rotate (79)Table A-9: MIPS32 SRLV Encoding of Shift/Rotate (79)Table A-10: MIPS32 BSHFL Encoding of sa Field (79)Table A-11: MIPS32 COP0 Encoding of rs Field (79)Table A-12: MIPS32 COP0 Encoding of Function Field When rs=CO (80)Table A-13: MIPS32 COP1 Encoding of rs Field (80)Table A-14: MIPS32 COP1 Encoding of Function Field When rs=S (80)Table A-15: MIPS32 COP1 Encoding of Function Field When rs=D (81)Table A-16: MIPS32 COP1 Encoding of Function Field When rs=W or L (81)Table A-17: MIPS64 COP1 Encoding of Function Field When rs=PS (81)Table A-18: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS, Function=MOVCF (81)Table A-19: MIPS32 COP2 Encoding of rs Field (82)Table A-20: MIPS64 COP1X Encoding of Function Field (82)Table A-21: Floating Point Unit Instruction Format Encodings (82)MIPS32™ Architecture For Programmers Volume I, Revision 2.00v Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.vi MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1About This BookThe MIPS32™ Architecture For Programmers V olume I comes as a multi-volume set.•V olume I describes conventions used throughout the document set, and provides an introduction to the MIPS32™Architecture•V olume II provides detailed descriptions of each instruction in the MIPS32™ instruction set•V olume III describes the MIPS32™Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32™ processor implementation•V olume IV-a describes the MIPS16e™ Application-Specific Extension to the MIPS32™ Architecture•V olume IV-b describes the MDMX™ Application-Specific Extension to the MIPS32™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-c describes the MIPS-3D™ Application-Specific Extension to the MIPS64™ Architecture and is notapplicable to the MIPS32™ document set•V olume IV-d describes the SmartMIPS™Application-Specific Extension to the MIPS32™ Architecture1.1Typographical ConventionsThis section describes the use of italic,bold and courier fonts in this book.1.1.1Italic Text•is used for emphasis•is used for bits,fields,registers, that are important from a software perspective (for instance, address bits used bysoftware,and programmablefields and registers),and variousfloating point instruction formats,such as S,D,and PS •is used for the memory access types, such as cached and uncached1.1.2Bold Text•represents a term that is being defined•is used for bits andfields that are important from a hardware perspective (for instance,register bits, which are not programmable but accessible only to hardware)•is used for ranges of numbers; the range is indicated by an ellipsis. For instance,5..1indicates numbers 5 through 1•is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below.1.1.3Courier TextCourier fixed-width font is used for text that is displayed on the screen, and for examples of code and instruction pseudocode.MIPS32™ Architecture For Programmers Volume I, Revision 2.001 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.Chapter 1 About This Book1.2UNPREDICTABLE and UNDEFINEDThe terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of theprocessor in certain cases.UNDEFINED behavior or operations can occur only as the result of executing instructions in a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register).Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged andunprivileged software can cause UNPREDICTABLE results or operations.1.2.1UNPREDICTABLEUNPREDICTABLE results may vary from processor implementation to implementation,instruction to instruction,or as a function of time on the same implementation or instruction. Software can never depend on results that areUNPREDICTABLE.UNPREDICTABLE operations may cause a result to be generated or not.If a result is generated, it is UNPREDICTABLE.UNPREDICTABLE operations may cause arbitrary exceptions.UNPREDICTABLE results or operations have several implementation restrictions:•Implementations of operations generating UNPREDICTABLE results must not depend on any data source(memory or internal state) which is inaccessible in the current processor mode•UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state which is inaccessible in the current processor mode. For example,UNPREDICTABLE operations executed in user modemust not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or in another process •UNPREDICTABLE operations must not halt or hang the processor1.2.2UNDEFINEDUNDEFINED operations or behavior may vary from processor implementation to implementation, instruction toinstruction, or as a function of time on the same implementation or instruction.UNDEFINED operations or behavior may vary from nothing to creating an environment in which execution can no longer continue.UNDEFINED operations or behavior may cause data loss.UNDEFINED operations or behavior has one implementation restriction:•UNDEFINED operations or behavior must not cause the processor to hang(that is,enter a state from which there is no exit other than powering down the processor).The assertion of any of the reset signals must restore the processor to an operational state1.3Special Symbols in Pseudocode NotationIn this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notation resembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1-1.Table 1-1 Symbols Used in Instruction Operation StatementsSymbol Meaning←Assignment=, ≠Tests for equality and inequality||Bit string concatenationx y A y-bit string formed by y copies of the single-bit value x2MIPS32™ Architecture For Programmers Volume I, Revision 2.00 Copyright © 2001-2003 MIPS Technologies Inc. All rights reserved.1.3Special Symbols in Pseudocode Notationb#n A constant value n in base b.For instance10#100represents the decimal value100,2#100represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#" prefix is omitted, the default base is 10.x y..z Selection of bits y through z of bit string x.Little-endian bit notation(rightmost bit is0)is used.If y is less than z, this expression is an empty (zero length) bit string.+, −2’s complement or floating point arithmetic: addition, subtraction∗, ×2’s complement or floating point multiplication (both used for either)div2’s complement integer divisionmod2’s complement modulo/Floating point division<2’s complement less-than comparison>2’s complement greater-than comparison≤2’s complement less-than or equal comparison≥2’s complement greater-than or equal comparisonnor Bitwise logical NORxor Bitwise logical XORand Bitwise logical ANDor Bitwise logical ORGPRLEN The length in bits (32 or 64) of the CPU general-purpose registersGPR[x]CPU general-purpose register x. The content of GPR[0] is always zero.SGPR[s,x]In Release 2 of the Architecture, multiple copies of the CPU general-purpose registers may be implemented.SGPR[s,x] refers to GPR set s, register x. GPR[x] is a short-hand notation for SGPR[ SRSCtl CSS, x].FPR[x]Floating Point operand register xFCC[CC]Floating Point condition code CC.FCC[0] has the same value as COC[1].FPR[x]Floating Point (Coprocessor unit 1), general register xCPR[z,x,s]Coprocessor unit z, general register x,select sCP2CPR[x]Coprocessor unit 2, general register xCCR[z,x]Coprocessor unit z, control register xCP2CCR[x]Coprocessor unit 2, control register xCOC[z]Coprocessor unit z condition signalXlat[x]Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR numberBigEndianMem Endian mode as configured at chip reset (0→Little-Endian, 1→ Big-Endian). Specifies the endianness of the memory interface(see LoadMemory and StoreMemory pseudocode function descriptions),and the endianness of Kernel and Supervisor mode execution.BigEndianCPU The endianness for load and store instructions (0→ Little-Endian, 1→ Big-Endian). In User mode, this endianness may be switched by setting the RE bit in the Status register.Thus,BigEndianCPU may be computed as (BigEndianMem XOR ReverseEndian).Table 1-1 Symbols Used in Instruction Operation StatementsSymbol MeaningChapter 1 About This Book1.4For More InformationVarious MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPS URL:ReverseEndianSignal to reverse the endianness of load and store instructions.This feature is available in User mode only,and is implemented by setting the RE bit of the Status register.Thus,ReverseEndian may be computed as (SR RE and User mode).LLbitBit of virtual state used to specify operation for instructions that provide atomic read-modify-write.LLbit is set when a linked load occurs; it is tested and cleared by the conditional store. It is cleared, during other CPU operation,when a store to the location would no longer be atomic.In particular,it is cleared by exception return instructions.I :,I+n :,I-n :This occurs as a prefix to Operation description lines and functions as a label. It indicates the instruction time during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the currentinstruction appear to occur during the instruction time of the current instruction.No label is equivalent to a time label of I . Sometimes effects of an instruction appear to occur either earlier or later — that is, during theinstruction time of another instruction.When this happens,the instruction operation is written in sections labeled with the instruction time,relative to the current instruction I ,in which the effect of that pseudocode appears to occur.For example,an instruction may have a result that is not available until after the next instruction.Such an instruction has the portion of the instruction operation description that writes the result register in a section labeled I +1.The effect of pseudocode statements for the current instruction labelled I +1appears to occur “at the same time”as the effect of pseudocode statements labeled I for the following instruction.Within one pseudocode sequence,the effects of the statements take place in order. However, between sequences of statements for differentinstructions that occur “at the same time,” there is no defined order. Programs must not depend on a particular order of evaluation between such sections.PCThe Program Counter value.During the instruction time of an instruction,this is the address of the instruction word. The address of the instruction that occurs during the next instruction time is determined by assigning a value to PC during an instruction time. If no value is assigned to PC during an instruction time by anypseudocode statement,it is automatically incremented by either 2(in the case of a 16-bit MIPS16e instruction)or 4before the next instruction time.A taken branch assigns the target address to the PC during the instruction time of the instruction in the branch delay slot.PABITSThe number of physical address bits implemented is represented by the symbol PABITS.As such,if 36physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.FP32RegistersModeIndicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs).In MIPS32,the FPU has 3232-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs.In MIPS64,the FPU has 3264-bit FPRs in which 64-bit data types are stored in any FPR.In MIPS32implementations,FP32RegistersMode is always a 0.MIPS64implementations have a compatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. In such a caseFP32RegisterMode is computed from the FR bit in the Status register.If this bit is a 0,the processor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.The value of FP32RegistersMode is computed from the FR bit in the Status register.InstructionInBranchDelaySlotIndicates whether the instruction at the Program Counter address was executed in the delay slot of a branch or jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value is false if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but which is not executed in the delay slot of a branch or jump.SignalException(exce ption, argument)Causes an exception to be signaled, using the exception parameter as the type of exception and the argument parameter as an exception-specific argument). Control does not return from this pseudocode function - the exception is signaled at the point of the call.Table 1-1 Symbols Used in Instruction Operation StatementsSymbolMeaning。
刀片之争——四款刀片服务器测评作者：清水编译来源：《计算机世界》2010年第31期今年3月,英特尔32纳米的至强处理器5600系列正式推出,它主要用于双路服务器和工作站系统,可带来更加出色的计算性能及能效。
美国《InfoWorld》近期对基于该处理器的戴尔PowerEdge M1000e、惠普BladeSystem c7000和IBM BladeCenter H等数款刀片服务器系统进行了测试。
英特尔至强处理器5600系列(研发代号为Westmere-EP)是英特尔新一代智能服务器处理器,与上一年英特尔推出的至强5500系列相比,在技术上有了很大进步。
它采用更为先进的32纳米制程工艺,成为英特尔服务器和工作站处理器中首批采用该工艺且最多集成了六个内核的芯片产品。
另外,它采用英特尔第二代高K金属栅极晶体管技术,实现了处理器计算速度的提升和能耗降低,使至强5600 系列在性能上比基于45纳米的至强5500系列提升最高达60%。
基于这一性能表现,数据中心用户完全可以用1台基于至强5600系列的服务器来替换15台基于单核处理器的旧服务器,并最短在5个月内收回新服务器的采购成本。
在英特尔官方发布至强5600(Westmere)处理器之前,戴尔、惠普和IBM采用这款最新处理器的刀片服务器送到了《Infoworld》在夏威夷大学的测评中心。
之后进行的基准测试表明,Westmere把刀片推向了新的高度。
我们在测评中还添加了经济型的Supermicro刀片机箱。
带4块刀片的戴尔、惠普或IBM机箱起价都超过4万美元,而Supermicro解决方案的成本只是它们的零头,虽然它与这三大刀片系统不是一个级别的,但对可能不需要最新功能或最高性能的公司来说却是个值得关注的选择。
因此,我们也对它进行了同样的测试。
所有测试工作都在夏威夷大学的高级网络计算实验室(ANCL)进行。
测试介绍这次测试我们没有使用HPC基准测试,而是选择了一套定制的VMware测试和一系列实际性能指标的测试。
主板有哪些重要参数很多人在第一次选购主板时候，不知道应该看哪些参数，容易买到劣质的产品，那么主板上哪些参数需要我们注意呢?主板选择主要看哪些参数呢?具体见下文。
主板参数都有哪些?主板重要参数：主芯片组：Intel Z87CPU插槽：LGA 1150CPU类型：Core i7/Core i5/Core i3/Pentium/Celeron内存类型：DDR3集成芯片：声卡/网卡显示芯片：CPU内置显示芯片(需要CPU支持)主板板型：ATX板型USB接口：8×USB2.0接口(6内置+2背板);6×USB3.0接口(2内置+4背板)SATA接口：6×SATA III接口PCI插槽：2×PCI插槽显卡插槽：PCI-E 3.0标准网卡芯片：板载Realtek RTL8111GR千兆网卡主板芯片集成芯片：声卡/网卡芯片厂商：Intel主芯片组：Intel Z87芯片组描述：采用Intel Z87芯片组显示芯片：CPU内置显示芯片(需要CPU支持)音频芯片：集成Realtek ALC892 8声道音效芯片网卡芯片：板载Realtek RTL8111GR千兆网卡处理器规格CPU平台：IntelCPU类型：Core i7/Core i5/Core i3/Pentium/CeleronCPU插槽：LGA 1150CPU描述：支持Intel 22nm处理器支持CPU数量：1颗内存规格内存类型：DDR3内存插槽：4×DDR3 DIMM最大内存容量：32GB内存描述：支持双通道DDR3 3000(超频)/2933(超频)/2800(超频)/2666(超频)/2600(超频)/2500(超频)/2400(超频)/2200(超频)/2133(超频)/1866(超频)/1800(超频)/1600/1333MHz内存扩展插槽显卡插槽：PCI-E 3.0标准PCI-E插槽：3×PCI-E X16显卡插槽2×PCI-E X1插槽PCI插槽：2×PCI插槽SATA接口：6×SATA III接口I/O接口USB接口：8×USB2.0接口(6内置+2背板);6×USB3.0接口(2内置+4背板)HDMI接口：1×HDMI接口外接端口：1×DVI接口、1×VGA接口、1×mini Display Port 接口PS/2接口：PS/2键鼠通用接口其它接口：1×RJ45网络接口、1×光纤接口、音频接口板型主板板型：ATX板型外形尺寸：30.5×22.35cm相关阅读：常见主板故障实例分析1.故障分析：出现这种现象的可能原因是：主板内存插槽，性能较差，内存条上的金手指与插槽簧片接触不良;也有可能是内存条上的金手指，表面的镀金效果不好，在长时间工作中，镀金表面出现了很厚的氧化层，从而导致内存条接触不好;还有一种可能是，内存条生产工艺不标准，看上有点儿薄，这样内存条与插槽始终有一些缝隙，稍微有点震动，就可能导致内存接触不好，从而引发报警现象。
主流服务器的品牌和配置1.当前服务器主流的品牌：HP、联想、浪潮、华为、思科2.每个服务器品牌查两到三台服务器的型号3.每个型号的配置⽹卡 cpu 内部等等HP：惠普（HP） DL20 Gen9 1U机架式服务器主机 I3 7100（冷插拔） 8G内存+1T硬盘机箱：1U机架式（H*W*D：38.2mm*432mm*435mm）；约重8kg处理器：奔腾 G4560（双核四线程，基本频率：3.5GHz，缓存：3M）;酷睿 I3-7100（双核四线程，基本频率：3.9GHz，缓存：3M）;⾄强 E3-1220 v6（四核四线程，基本频率：3.0GHz，缓存：8M）;⾄强 E3-1230 v6（四核⼋线程，基本频率：3.5GHz，缓存：8M）;⾄强 E3-1240 v6（四核⼋线程，基本频率：3.7GHz，缓存：8M）内存：8GB DDR4 ECC UDIMM内存，可扩展⾄64GB硬盘：⽀持2块3.5英⼨热插拔/⾮热插拔硬盘(⽆硬盘配置均不带硬盘托架)阵列卡：动态智能阵列 B140i,⽀持RAID0/1显卡：集成显卡⽹卡：1Gb 332i以太⽹适配器，双端⼝控制器光驱：标配⽆光驱，可选配DVD-ROM/DVD-RW电源：标配290W单电源扩展：1*pci-e x8接⼝，1*pci-e x16插槽；3个USB3.0接⼝（后置2个，内置1个）；2个USB2.0接⼝（前置置）；1个VGA接⼝；2个千兆⽹⼝惠普（HP）DL388Gen9型号：根据配置结构：2U机架式服务器CPU（根据配置）：⾄强E5-2603v4/6核/1.7G/6线程；⾄强E5-2609v4/8核/1.7G/8线程；⾄强E5-2620v4/8核/2.1G/16线程；⾄强E5-2630v4/10核/2.2G/20线程；CPU个数：可⽀持2个扩展槽：3个PCle(可选增加第⼆个PCle扩展笼）芯⽚组：Intel C600芯⽚组嵌⼊式⽹络控制器：1Gb 361i以太⽹适配器，双端⼝控制器内存描述：类型：DDR4-2400 按需配置内存插槽数：24个硬盘描述：标配⽆硬盘⽀持SAS/SATA内部硬盘位数：可⽀持8个2.5英⼨SFF磁盘阵列卡: 1个智能阵列P440ar带2GB FBWC光驱：标配⽆光驱⽹络控制器：Broadcomm5720 四端⼝控制器电源：1个500W通⽤插槽热插拔电源尺⼨：8.73cm*44.55cm*67.94cm重量：14.8kg-23.6kg(按实际配置)联想联想System x3850 X6CPU类型：CPU型号：Xeon E7-4809 v2CPU频率：1.9GHz扩展槽：7×半长PCI-E内存类型：DDR3内存容量：内存描述：32GB(4×8GB)1600MHz DDR3最⼤内存容量：1536GB硬盘描述：8个2.5"SAS热插拔硬盘槽位⽹络控制器：板载ML2四端⼝千兆以太⽹卡，可选双⼝万兆夹层卡散热系统：散热系统系统管理：Alert on LAN 2，服务器⾃动重启，IBM Systems Director，IBM ServerGuide，集成管理模块（IMM），光通路诊断（单独供电），适⽤于硬盘驱动器/处理器/VRM/风扇/内存的Predictive Failure Analysis，Wake on LAN，动态系统分析，QPI Faildown，单点故障转移系统⽀持：Windows Server 2008（Standard，Enterprise 和 Data Center Edition，32位和64位）32位和64位 Red Hat Enterprise LinuxSUSE Enterprise Linux（Server 和 Advanced Server）VMware ESX Server/ESXi 4.0联想ThinkSystem SR550CPU类型：Intel ⾄强铂⾦CPU型号：Xeon 铂⾦最⼤CPU数量：2颗扩展槽：6×PCIe 3.0内存类型：DDR4内存描述：64GB DIMM，2666MHz TruDDR4硬盘接⼝类型：SATA/SAS内部硬盘架数：最⼤⽀持16块2.5英⼨热插拔SAS/SATA硬盘，8个热插拔/易插拔3.5英⼨SAS/SATA硬盘，最多2个内置M.2盘RAID模式：标配RAID软件（多达8个端⼝）；多达16个端⼝HBA/或硬件RAID，含闪存缓存标准接⼝：2个1GbE端⼝+1个专⽤1GbE管理端⼝（标配），可选1个10GbE LOM系统管理：XClarity Controller 嵌⼊式管理、XClarity Administrator 集中基础架构交付、XClarity Integrator 插件、XClarity Energy Manager 集中服务器电源管理系统⽀持：Windows Server、SLES、RHELVMware vSphere电源类型: 热插拔/冗余电源，80 Plus铂⾦电源或80 Plus钛⾦电源电源功率: 550/750/1100/1600W联想System x3650 M5CPU类型: Intel ⾄强E5-2600 v3CPU型号: Xeon E5-2603 v3CPU频率: 1.6GHzCPU:核⼼六核（Haswell）CPU:线程数六线程内存类型: DDR4内存容量:硬盘接⼝类型: SAS硬盘描述: 8个2.5英⼨SAS硬盘内部硬盘架数M5210外部驱动器架数多达24个前端和2个后端2.5英⼨ HDD/SSD标准接⼝4×1GbE1×IMM前端：1×USB 3.0、2×USB 2.0后端：2×USB 3.0、2×USB 2.01×USB 3.0系统管理: IBM IMM2.1；⼀个IMM专⽤插槽和⼀个共享插槽；可选的远程在线；预测性故障分析；LED；可选的下⼀代光通路诊断⾯板系统⽀持Microsoft Windows ServerRed Hat Enterprise LinuxSUSE Linux Enterprise ServerVMware vSphere电源功率: 550WDELL：浪潮：浪潮英信NF5270M4CPU类型：Intel ⾄强E5-2600 v3CPU型号：Xeon E5-2609 v3主板芯⽚组：Intel C610扩展槽：6×PCI-E 3.0硬盘接⼝类型：SATA/SAS硬盘描述：可⽀持7200转 3.5⼨ SAS及SATA硬盘内部硬盘架数：8个硬盘⽀架磁盘控制器：硬盘⼩于等于4块时，系统默认标配⼀个4⼝背板；超过4块硬盘时，带两个4⼝背板⽹络控制器：双千兆⽹卡标准接⼝：1×USB 3.0接⼝，1×VGN接⼝（前置）2×USB 3.0接⼝，1×VGA接⼝（后置）2×USB 3.0接⼝兼容2.0（内置）系统⽀持：Microsoft Windows Server 2008 SP1 32/64bitMicrosoft Windows Server 2008 R2Red Hat Enterprise Linux6 32/64bitSuSE Linux Enterprise Server 11 32/64bit电源类型：单电源电源电压：AC 100-240V产品尺⼨：87×447×720mm浪潮英信NX8480M4CPU类型：Intel ⾄强E7-E7-4800/8800 v3/v4主板芯⽚组：Intel C610扩展槽: 1×PCI-E 3.0 x8 Raid⼦卡插槽4×PCI-E 3.0 x16扩展⼦卡插槽4×PCI-E 3.0 x8扩展⼦卡插槽（可通过专⽤线缆选择链接IO Box⽀持4个标准PCIe扩展卡，半⾼半长规格，使⽤IO Box时内部4个PCIe 3.0 x8扩展⼦卡插槽不可⽤）内存类型: DDR4最⼤内存容量:6TB硬盘接⼝类型: SATA/SAS/SSD硬盘描述: 最⼤⽀持8个热插拔2.5⼨SATA/SAS接⼝硬盘或SSD可⽀持4个NVMe SSD盘，可以同时配置为SAS+NVMe磁盘控制器: 标配SAS 12Gb磁盘控制器⼦卡，可选2G、4G缓存磁盘控制器RAID模式: SAS磁盘控制器⽀持RAID 0/1/5/6/10/50/60等⽹络控制器: 集成⾼性能双⼝千兆以太⽹卡，⽀持虚拟化加速、⽹络加速、负载均衡、冗余等⾼级功能标准接⼝: 1×UVC（可转出2×USB 2.0接⼝，1×VGA接⼝，1×COM⼝）1×Power按键1×Reset按键1×UID状态指⽰灯产品尺⼨: 110×430×524mm华为：华为FusionServer 2288H V5CPU类型: Intel ⾄强铜牌CPU型号: Xeon Bronze 3106CPU频率: 1.7GHz标配CPU数量:1颗主板芯⽚组：Intel C622扩展槽：最多10个PCIe扩展槽位：4个全⾼全长的PCIe3.0 x16标准卡(信号为x8)，3个全⾼半长的PCIe3.0 x16标准卡(信号为x8)，1个全⾼半长的PCIe3.0 x8标准卡(信号为x8)，1个RAID控制卡槽位，1个灵活LOM插卡内存类型：DDR4内存容量：内存描述：1*16GB DDR4硬盘接⼝类型：SATA/SAS内部硬盘架数：12个3.5英⼨SAS/SATA硬盘⽹络控制器：板载⽹卡：2个10GE接⼝与2个GE接⼝散热系统：4个热拔插对旋风扇，⽀持N+1冗余系统管理: 基于华为iBMC芯⽚，提供全⾯的故障诊断、⾃动化运维、硬件安全加固等管理特性；⽀持Redfish、SNMP、IPMI2.0等主流标准接⼝，易于被集成；提供基于HTML5/VNC KVM的远程管理界⾯；⽀持免CD部署、Agentless等特性简化管理复杂度电源功率:550W产品尺⼨：86.1×436×748mm华为FusionServer RH5885 V3CPU类型：Intel ⾄强E7 v4CPU型号：Xeon E7-4809 v4CPU频率: 2.1GHz扩展槽: 最多8×PCI-E扩展插槽（含1个RAID专⽤）内存类型: DDR4内存容量：内存描述：2*16GB DDR4内存内存插槽数量：48硬盘接⼝类型：SAS硬盘描述: 1块600GB 2.5英⼨SAS硬盘内部硬盘架数: 8个2.5英⼨SAS/SATA/SSD硬盘磁盘控制器: SR430C 1G CacheRAID模式: RAID 0，1，5⽹络控制器: 4×GE接⼝散热系统: 5个热插拔对旋风扇，⽀持N+1冗余系统管理: 独⽴接⼝，⽀持SNMP、IPMI，提供GUI⽤户管理界⾯、虚拟KVM、虚拟媒体、SOL、远程控制、硬件监控、智能电源等管理特性⽀持华为eSight管理软件，⽀持被VMWare vCenter、微软SystemCenter、Nagios等第三⽅管理系统集成系统⽀持: Microsoft Windows Sever、Red Hat Enterprise Linux、SUSE Linux Enterprise Server、Citrix XenServer、VMware ESXi、Huawei FusionSphere等电源电压: 110V/220V AC或-48V DC输⼊产品尺⼨: 447×790×175mm华为FusionServer RH2288 V3CPU类型: Intel ⾄强E5-2600 v4CPU型号: Xeon E5-2609 v4CPU频率: 1.7GHz扩展槽: 最多⽀持6个PCIe扩展插内存类型: DDR4内存容量:16GB内存插槽数量: 16内部硬盘架数: 12个3.5英⼨SAS/SATA硬盘⽹络控制器: 2×GE接⼝散热系统: 热插拔风扇模组，⽀持N+1冗余系统管理: 采⽤华为Hi1710管理芯⽚，独⽴接⼝，⽀持SNMP、IPMI，提供GUI、虚拟KVM、虚拟媒体、SOL，深度预故障检测（PFA）、智能电源、远程控制、硬件监控等特性，集成触控式LCD诊断⾯板⽀持华为eSight管理软件，⽀持被VMWare vCenter、微软SystemCenter、Nagios等第三⽅管理系统集成系统⽀持: Microsoft Windows Sever、Red Hat Enterprise Linux、SUSE Linux Enterprise Server、CentOS、Citrix、XenServer、Vmware ESXi产品尺⼨: 447×748×86.1mm思科：CISCO UCS C240 M3CPU类型Intel ⾄强E5-2600标配CPU数量1颗/2颗主板芯⽚组Intel C600扩展槽5×PCI-E 3.0内存类型DDR3硬盘接⼝类型SATA/SAS/SSD最⼤硬盘容量24块2.5英⼨硬盘硬盘描述24块2.5英⼨SATA/SAS/SSD硬盘⽹络控制器1个千兆管理⽹卡⼝，四端⼝千兆⽹卡⼝标准接⼝5×RJ45⽹络接⼝2×USB 2.0接⼝1×VGA接⼝电源类型650W/1200W双冗余电源CISCO UCS C220 M3CPU类型：Intel ⾄强E5-2600标配CPU数量：1颗/2颗主板芯⽚组：Intel C600扩展槽：2×PCI-E 3.0内存类型：DDR3内存插槽数量：16硬盘接⼝类型：SATA/SAS/SSD最⼤硬盘容量：8块2.5英⼨SATA/SAS/SSD硬盘描述：2.5英⼨SATA/SAS/SSD硬盘热插拔盘位：⽀持热插拔RAID模式：RAID 0，1，10，5⽹络控制器：⼀个千兆管理⼝，双千兆⽹卡⼝标准接⼝：1×RJ45⽹络接⼝2×USB 2.0接⼝1×VGA接⼝电源类型：450W/650W双冗余电源。
支持内存传输标准支持内存最大容量内存插槽DDR 400/333/26616GB /16GB/32GB8 DDR2 533/66716GB6 DDR2 533/66716GB6 DDR2 533/66724GB6DDR2 400/5334GB4 DDR2 533/6678GB4DDR2 533/66716GB4533/66732GB8 533/667 FB-DIMM16GB6 266/333/40012GB6800/6678GB4 800/6678GB4 667/5334GB2 533/66724GB6 533/66724GB6 667/8008GB4PCI插槽最大数量网卡others2 (x16) PCI-Express,2 (x4 using x8 slot)(nVidia SLI TechnologySupported)PCI-Express,3 32-bit 33MHz PCI板载双千兆AC97 6声道1 (x8) & 1 (x4) in (x8) PCI-Express,2x 64-bit 133/100MHz PCI-X,2x 32-bit 33MHz PCI板载双千兆82563EB ES1000显卡16M1 Universal Slot Supporting:1 (x8) PCI-Express OR1x 64-bit 133MHz PCI-X,1x 64-bit 133MHz PCI-X,1x 32-bit 33MHz PCI板载双千兆82563EB XGI Z71 (x16) & 1 (x4 in x16) PCI-Express,2x 64-bit 133/100MHz PCI-X,2x 32-bit PCI 33MHz1x UIO Slot 板载双千兆82563EBAC97 Audio1 PCI2 PCI-X / 100 MHz1 PCI Express x8板载双千兆82541PI Intel GMA 900 One PCI Express* x 1One PCI Express* x 4 One PCI Express* x 8 Two PCI 32-bit/33 MHz 板载双千兆ATI* ES1000 with 16 MBmemory2 x PCI Express* x4 (x8Connectors)2 x PCI-X 64-bit/133 MHz1 x PCI 32-bit/33 MHz板载双千兆ATI* ES1000 with 16MB2 x PCI Express* x82 x PCI Express x4 (x8Connectors)1 x PCI-X 100/133 MHz1 x PCI-X 100 MHz Dual Intel® GigabitEthernet connections82563EBATI* with 16MB memory• 1 个 32-bit/33MHz PCI 插槽• 2 个 100MHz PCI-X 插槽 (绿色的适用于 ZCR)• 1 个 PCI-Express x8 插槽• 1 个 PCI-Express x4 插槽板载双千兆 Intel 82563EB XGI Volari Z7 16M · 1 16x PCI-Express· 1 64-bit 133MHz PCI-X· 2 64-bit 100MHz PCI-X · 2 32-bit 33MHz PCI-X 单Broadcom 5721 GbE 千兆以太网卡ATI9000专业图形显示卡1 * PCI-E x16（x8 link）插槽,2 * PCI 32bit/33MHz插槽,2 * PCI-X插槽1 * PCI 32bit/33 MHz,1 * PCI 32bit/33 MHz,1 * PCI 32bit/33 MHz,1 * PCI-E x16（x8 link）1 * PCI-E x16 ,1 * PCI-E x1,2* PCI 33 MHz / 32-bit / 5V 1 * PCI插槽,1 * PCI-X 133/100MHz,1 * PCI-X 133/100 MHz1 * PCI-E x8插槽（x8 link）,1 * PCI-E x8插槽（x4 link）,1 * PCI插槽,1 * PCI-X 133/100 MHz 插槽1：1 * PCI 32bit/33 MHz,插槽2：1 * PCI 32bit/33 MHz,插槽3：1 * PCI 32bit/33 MHz,插槽4：1 * PCI-E x8（x4 link）,插槽6：1 * PCI-E x16（x8 link）尺寸硬盘插口/RAID支持类型/芯片组12*13.058个SATAII接口，支持RAID 0、1、10/nvidia RAID 12*106个SATAII接口，支持Raid 0、1、5、10/ESB2 12*106个SATAII接口,支持RAID0/1/5/10/ESB212*106个SATA接口，支持RAID 0, 1, 5, 10/ESB212*10Four SATA 150 connectors, RAID 0, 1, and 10ATX 12" x 9.6"4个 SATA接口,RAID 0,RAID 0+1,RAID 1RAID5可选/LSI或者Intel® Integrated RAID12*136个SATA 支持RAID 0, 1, 10 with optional AXXRAKSW5 forRAID 512*134-Port LSI* 1064e SAS controller with Intel® Embedded RAID Technology II providing RAID 0, 1, 10 andoptional AXXRAKSW5 for RAID 512” X 10.5”LSI Logic SAS1068- 8-port 控制器RAID 0, RAID 1, 与 RAID 1E 6 个 SATAII12" x 13.05"Adaptec AIC-7902 双通道 Ultra320 SCSI 2SATA8个SAS接口，支持RAID 0、1、1E（支持扩展ZCR卡）4 * SATA2 300MB/s接口, 支持RAID 0、1和101 IDE,4 SATA26 * SATA2 300MB/s接口, 支持RAID 0、1、10和56 * SATA2 300MB/s接口，支持RAID 0、1、10和54 * SATA2 300MB/s接口,英特尔® Matrix Storage（仅支持Windows）,（支持软件RAID 0、1、10和5）。
