微波仿真理论基础

Basic BJT CircuitFigure 1 below shows the simplied ‘Pi’ model of a BJT.cVinVoutZinVoutBCΒ.ib ibFigure 1 Transistor symbol and simplified ‘Pi’ modelWe can see that output consists of a current source –gm.Vbe to get the output voltage we multiply by the load resistance Rce ie Vout = -gm.Vbe.Rce (the negative sign denotes signal inversion).The input resistance of the circuit is given by:e temperatur room at (23.5mV)0.0235V ely approximat is and voltage thermal the as known is V (mS)ctance Transcondu gm Kelvin in e Temperatur T 1.6022x10 charge Electron q 1.3807x10 constant Boltzmansk where q k.T V ; V I gm where gmβR T 19-123-T T CQ IN =========−CJKThe output resistance is given by:ge(V)EarlyVolta V Where I Vrce R A CQA OUT ===The voltage gain (Av) is given by:TA CQ A T CQ be be IN OUT V V VI V .V I rce . V rce .V . V V A ==−=−==gm gmThe current gain (Ai) is given by:β- i β.i - I I A bbIN OUT i ===The MOS TransistorThese devices are known as FET’s (Field effect transistors), which consist of three regions source, drain and gate. The resistance path between the drain and source is, controlled by applying a voltage to the gate. This varies the depletion layer under the gate and thusreduces or increases the conductance path. The FET input impedance (unlike the BJT which is a few K Ω) is very high (~M Ω’s) and as a result the gate current can be considered as zero.As per the BJT the FET is best described by it’s Output I-V DC characteristics (N-typeenhancement characteristics shown below), however things are complicated by the fact there are two types of FET depletion and enhancement that are both available as N-type or P-type devices. For low frequencies the enhancement devices is more commonly used (Depletion mode types will be described when discussing microwave devices).0 = 0V123Triode Region Or Linear RegionGST GS DS V V V −=(1) Cut-Off Region – In this region the gate voltage is less than the pinch-off voltage Vp and therefore very little current flows.(2) Triode Region – In this mode the device is operating below pinch-off and is effectively a variable resistor. R OUT is ~ linear but only over a small range of V DS .(3) Saturation Region – This is the main operating region for the device. The drain voltage has to be greater than the gate voltage less the pinch-off voltage – this sets the minimumsupply voltage. The curves in the saturation region can be extrapolated to a point 1/λ, where λ is known as the ‘Channel length modulation parameter, (units V -1), - this is analogous to the BJT Early voltage.Referring to the saturation region we can assume the response is approximately linear such that the:-resistance high e,conductanc small ie λ.I G λ1I λ1V I V 1if then0.01 to 0.001 region the in typically is λλ1V I G therefore 1I .G1- VDS then c mx - y form the of line straight a assume we If G e conductanc output Device curve of slope R resistance output Device curveof slope 1D O DDS D DS DS D O D OOO≈−−=⎟⎠⎞⎜⎝⎛−−>>⎟⎠⎞⎜⎝⎛−−=+⎟⎟⎠⎞⎜⎜⎝⎛=+===λλTo complete the model for the FET we need to add the term for the linear region which, is dependant on the device mobility and gate dimensions.I ()DS DS DS DS DS DSO DQ DQ D λ.V 1.I .V λ.I I .V G I I I +=++∆+=DS DS T GS OX O V .2-V -V .L .C .⎥⎦⎤⎢⎣⎟⎠⎜⎝µ()()parametermodulation length Channel voltagethreshold Device VT ratio aspect the as Known W/L length channel Effective L widthchannel Effective W oxidegate of area unit per e capacitanc tC device of mobility Surface Where onlyregion /linear saturation -non .V 1V .2V -V -V .L W .C . ID OXOX OX O DS DS DS T GS OX O ========+⎥⎦⎤⎢⎣⎡⎟⎠⎞⎜⎝⎛=λεµλµFor saturation region ie V DS > (V GS -V T )[]()[]()parameterctance transcondu Intrinsic the as Known .C µ K Where λ.V 1V -V 2L W .KI aswritten -re Sometimes parameter ctance transcondu the as Known 2L W .C µβ Where λ.V 1V -V β I OX O P DS 2T GS P D OX O DS 2T GS D =+⎦⎤⎢⎣⎡=⎥⎦⎤⎢⎣⎡=+=Usually λ.V DS << 1 so[]2T GS D V -V β I ≈The following page shows some typical values of the above parameters for use with a level 1 MOS model. The ADS version of this model is also shownTypical MOS Spice Parametersn-Well CMOS Level 1 SPICE Model parametersLevel 1 SPICE Parameter n-channelMOSFETp-channelMOSFETUnitsGate oxide thicknessTOX150 150 Angstrom TransconductanceParameter KP50 x 10-625 x 10-6Amp/V2 Threshold Voltage VT0 1.0 -1.0 VoltsChannel-length modulation parameter LAMBDA 0.1/LL in micron0.1/LL in micronV-1Bulk ThresholdParameter GAMMA0.6 0.6 V1/2Surface Potential PHI 0.8 0.8 VGate-drain overlapcapacitance CGDO5 x 10-10 5 x 10-10F/mGate-source overlapcapacitance CGSO5 x 10-10 5 x 10-10F/mZero-bias planar bulkdepeletioncapacitance CJ10-4 3 x 10-4F/m2Zero-bias sidewall bulkdepletion capacitanceCJSW5 x 10-10 3.5 x 10-10 F/mBulk junction potentialPB0.95 0.95 V Planar bulk junctiongrading coefficient MJ0.5 0.5 None Sidewall bulk junctiongrading coefficientMJSW0.33 0.33 NoneVAR VAR2LAMBDA=0.1/LL=0.5W=100MOSFET_NMOS MOSFET1Mode=nonlinearTemp=Region=Mult=Nrs=Nrd=Ps=Pd=As=Ad=Width=W um Length=L um Model=MOSFETM1LEVEL1_Model MOSFETM1AllParams=Imax=Ffe=Tt=N=Tnom=Rds=Rg=Fc=Af=Kf=Gdsnoi=1Nlev=Uo=Ld=Tpg=Nss=Nsub=Tox=150e-10Js=Mjsw=0.33Cjsw=5e-10Mj=0.5Cj=1e-4Rsh=Cgbo=Cgdo=5e-10Cgso=5e-10Pb=0.95Is=Cbs=Cbd=Rs=Rd=Lambda=LAMBDA Phi=0.8Gamma=0.6Kp=50e-6Vto=1PMOS=no NMOS=yesAs with the BJT it is possible to simulate a device under ADS to produce the device Output I-V curve trace for a typical N-type MOS 3.3V 0.25um process enhancement device. The Spice data for the MOSFET model is called up from the spice file ‘tsmc_’.spiceInclude SPICE1File="tsmc_"NetlistDebugMode=0VAR VAR1VDS=0VGS=0DC1SweepVar="VDS"Start=0Stop=3.3Step=.1Other=OutVar="MOSFET1.Gm"Sweep1SweepVar="VGS"SimInstanceName[1]="DC1"SimInstanceName[2]=SimInstanceName[3]=SimInstanceName[4]=SimInstanceName[5]=SimInstanceName[6]=Start=0Stop=2Step=0.2The resulting plot0.00.51.01.52.0 2.53.0 3.5-55 1015 20 25 30 35 40 45 VgsVDSIDS.i, mAThe device will also have a transconductance Curve ie V GS vs I DS . The ADS simulation below sweeps the gate voltage and measures the resulting drain current.DC1Other=OutVar="MOSFET1.Gm"Step=.1Stop=3Start=0SweepVar="VGS"VAR VAR1VDS=3.3VGS=0spiceInclude SPICE1File="tsmc_"NetlistDebugMode=0Resulting transconductance curve, slope is the G M of the device.0.00.20.40.60.81.0 1.2 1.4 1.6 1.82.0 2.2 2.4 2.62.83.00.0000.0050.0100.0150.0200.0250.0300.0350.0400.0450.0500.0550.0600.0650.0700.0750.0800.085VGSIDS.iSlope of curve = gmIDS (A)Pinch-off voltage = 0.6VAnd for the P-type deviceInput transconductance traceMOSFET_PMOS MOSFET1Mode=nonlinearTemp=Region=Mult=2Nrs=Nrd=Ps=Pd=As=Ad=Width=100 um Length=0.5 um Model=MODpch3_1DC1Other=OutVar="MOSFET1.Gm"Step=-.1Stop=-5Start=0SweepVar="VGS"VAR VAR1VDS=-3.3VGS=0spiceInclude SPICE1File="tsmc_"NetlistDebugMode=0Resulting trace-5-4-3-2-1-0.07-0.06-0.05-0.04-0.03-0.02-0.010.00VGSIDS.ispiceInclude SPICE1File="tsmc_"NetlistDebugMode=0MM9_NMOS MOSFET1Mode=nonlinearMult=2Temp=Lg=Ls=Ab=Width=100 um Length=0.5 um Model=MODnch3_1ParamSweep Sweep1Step=1Stop=5Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DC1"SweepVar="VGS"DC1Other=OutVar="MOSFET1.Gm"Step=.1Stop=3Start=0SweepVar="VDS"VAR VAR1VDS=3.3VGS=0Output characteristic trace-5-4-3-2-1-0.07-0.06 -0.05 -0.04 -0.03 -0.02-0.01 0.00 0.01 VDSIDS.iBody EffectThe FET body or ‘Bulk’ is known either as the substrate, back gate or more commonly the Body. It is normally connected to the lowest voltage potential of the circuit (usually thesource). However if is left unconnected its effect on the DC characteristics of the device must be taken into account. If we include the bulk effect the value of the threshold voltage V T will increase with increasing bulk voltage.()source) the to connected bulk (ie 0 V for V V normally Therefore,(Volts)potential source Bulk V (Volts) potential level Fermi .F (Volts)parameter hold Bulk thres γ.F 2..F 2.V -γ V V BS T TO BS BS TO T ====Φ=Φ−Φ++=If the device was biased without the bulk node connected then a change in operating point could take the device out of its saturation region and significantly change the circuitperformance. The bulk voltage is thus a very important parameter in circuit applications and therefore it is best to connect the bulk to the device source connection.The circuit is drawn as follows:-The simulation below shows how varying the bulk voltage will vary the pinch-off voltage of the device.VAR VAR1VBS=0VGS=0Sweep1Step=0.1Stop=1Start=0SimInstanceName[6]=SimInstanceName[5]=SimInstanceName[4]=SimInstanceName[3]=SimInstanceName[2]=SimInstanceName[1]="DC1"SweepVar="VGS"DC1Other=OutVar="MOSFET1.Gm"Step=0.5Stop=3Start=0SweepVar="VBS"V_DC SRC4Vdc=VBSspiceInclude SPICE1File="tsmc_"NetlistDebugMode=0Resulting plot showing that the pinch-off voltage increases with increasing bulk voltage0.00.20.40.60.8 1.00.0000.0010.0020.0030.0040.0050.0060.0070.008IDS.iIncreasing pinch-off voltageFrom the last section we found that the drain current in the saturation region =[]2T GS D V -V β I ≈Transconductance[][][][][]D 5.0D 0.50.5-5.0D 1D DT GS 2T GS D T GS GST GS D GS 2T GS D GSD M I .β2 I .2β βI .2β βI 2βGM (1) into sub βIV -V then V -V β I rearrange we If(1) - V -V 2β GM V .V -V 2β I V wrt ate differenti therefore V -V β I curvetransfer of slope ie V IG =======∆=∆=∆∆=Output Conductance()()()()λ.I G V I V λ..I I (2)into sub V -V βI above From (2) - V λ..V -V β I V wrt ate Differenti λ.V 1V -V βI sticcharacteri output of slope ie ∆V ∆I G D O DSDDS D D 2T GS D DS 2T GS D S D DS 2T GS D DSDO ==∆∆=∆=∆=∆=∆+==Voltage Gain AL .W K .I 2.λ1 .I .L .2.W .K .λ2 I 1.2L .W K .λ2 2L .W K β and I β.λ2 A .λI .2.β .λ.I I .2.β λ.I β.I 2 G G e Conductanc Output ctance transconduA P D 0.5-D 0.5-0.5-0.50.5P 1-1D P P D10.5-D 0.511D 0.5D 0.5DD O M ==========−−−Common-Base/Gate CircuitsCommon-Base BJT circuitThe figure below shows the simplied ‘Pi’ model of a common-base BJT.r ceVinZinV I e wher gm 1r 1)(βi 1).r (βi I V R TCQ be b be b IN IN IN ===++==gm)r gm1(as V V I V .V I r r 1)r (βr .β 1)r (βi r .i .β V V A ce T A CQ A T CQ be ce be ce be b ce b IN OUT V ===≈+=+==()1 1ββ)1βi β.i I I A b b IN OUT i ≈+=+==r ceTo determine the Output impedance of the circuit we can connect a voltage source (V s + R s ) to the base and ground the input ie the emitter. We then have to resistances in parallel connected to the current source β.i b .()equationabove into sub R r R i i Also r .i r i .i V i VR sbe sT b be b ce b T OUT TOUTOUT +=++==βsbe be s s be s ce ce T OUT OUT be s ce sT ce s be s T TOUT R r r.R R r R r .r i V R r .R r R i r R r R i .i V ++++==++⎟⎟⎠⎞⎜⎜⎝⎛++=ββ()ce ce ce OUT s ceOUT s r .1 1r .r R then large R If r R then 0 R If +=++====ββCommon-Gate MOSFET Circuitgr dsVoutVinI INVoltage Gain A v()R r .R r gm A //R r gmVsg V Vsg V V VA L dgL dg V L dg O IN INOV ⎟⎟⎠⎞⎜⎜⎝⎛+====Input ResistanceλI gm1 gmVgs Vgs I VR D IN IN IN ====Output ResistanceAs the source is low impedance ie close to ground for R OUT – r ds appears to be connected across r ds to ground.ds dg OO OUT //r r I VR ==Current Gain A iA i = 1Common-Emitter/Source CircuitsCommon-emitter BJT circuitThe figure below shows the simplied ‘Pi’ model of a common-emitter BJT.VoutEBCΒ.ib ibVinVoutZin(mS)ctance Transcondu Kelvinin e Temperatur T 1.6022x10charge Electron q 1.3807x10 constant Boltzmans k whereq k.T V ; V I where R 19-123-T TCQ IN =========−gm C JK gm gm βge(V)EarlyVolta V Where I Vrce R A CQA OUT ===TA CQ A T CQ be be IN OUT V V VI V .V I rce . V rce .V . V V A ==−=−==gm gmββ- i .i - I I A b bIN OUT i ===Common-Source MOS FET CircuitdrainVoutsd IoVoltage Gain A v()R r .R r gm - A //R r gmV - V V VA L dsL ds L ds IN O INO V ⎟⎟⎠⎞⎜⎜⎝⎛+=== Input ResistanceR IN = ∞Output ResistanceL ds OOOUT //R r I VR ==Current Gain A iA i = ∞Common-Collector/Drain CircuitsCommon-Collector Drain BJT CircuitFigure 1 below shows the simplied ‘Pi’ model of a common-collector BJT.B Cβ.i bi bVinZinLLLLLLggoR1rce1'R1Rrcerce.R'R+=+=+='.R)1('RrII).1('RI.rIVVIVRLLbebbLbbeINRLbeINININβββ≈++=++=+==rceRthenrceRifRrcee.Rr'R1).i('R.1).i(IVROUTLLLLbLbOUTOUTOUT≈<<+==++==cββ1)(bybottom&topdivide)1('Rr)1('RI).1('RI.rI).1('RVVALbeLbLbbebLINOUTV++++=+++==βββββLLLLVbeLbeLVggo'R1abovefrom'R)1(.'RAgmr'R)1('RA+=++=∴=++=ββββgm1)1(.ggo1ggobybottom&topMultiplyggo1)1(.ggoggo1ALLLLLV+++=++++++=ββββgm gmδαδββα.11A gm g go let and 1Let V L +=+=+=()()βββ 1 i i .1I IA b b INOUT i ≈+=+==Common-Drain MOS FET CircuitdrainVoutVindVoltage Gain A v()()()()()()1A 1AAv Therefore, //R r gm Av //R r gm 1//R r gm Av by Vgsbottom & top divide //R r gmVgs Vgs //R r gmVgsAv //R r gmV Vo V V VV VAv L ds L ds L ds L ds L ds L ds gs Ogs OIN o ≈+==+=+==+==Input ResistanceR IN = ∞Output Resistancegm1I V R O O OUT ==Current Gain A iA i = ∞Common-Emitter Circuit with emitter degenerationThe figure below shows the simplied ‘Pi’ model of a common-emitter BJT with emitter de-generation.VinBCβ.ib ibVinVoutZinZoutLce L ce L EL E L E be L E b be b L b IN OUT V R r .R ris 'R Where R 'R - R 'R .- 1)R (βr 'β.R - 1)R (βi .r i 'R ..βi - V V A +=≈≈++=++==αE E be bEb be b IN IN IN 1)R (β 1)R (βr i 1)R (βi .r i I V R +≈++=++==ββ i .i I IA bbIN OUT i ===VoutTo determine the Output impedance of the circuit, we ground the base and the emitter. We then have two resistances in parallel connected to the current source β.i b .()()equation above into sub r //R i V Also V r gmV i Vi VR be E T be bece be T OUT TOUT OUT +=++==()()()()()()()()()()⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛++==⎟⎟⎟⎟⎠⎞⎜⎜⎜⎜⎝⎛++=⎟⎟⎠⎞⎜⎜⎝⎛++=−++==++=++=1βgm.R R .gm 1r R βgm r 1 and 1r R R .gm 1r r by bottom and top divide r R r .R .gm 1r R ignored be can and small is term This r //R r //R r //R gm 1r i V R r //R i r //R gm 1.i r r //R i r r //R i .gm i V EE ce OUT be be E E ce be be E be E ce OUTbe E be E be E ce TOUTOUT be E T be E T ce be E T ce be E T T OUT)gmR (1r R gmR if E ce OUT E +=<<βGenerallyThe de-generated CE circuit provides DC regulation but the load andemitter resistors may have similar values and hence the voltage gain will be low. This however, can be overcome by RF bypassing RE, with a smaller RE, resulting in high voltage gain while maintaining the correct DC bias conditions.The circuits below illustrate the problem and solution.Say we require an amplifier with a voltage gain of 15, a C-E voltage of 5V with an Ic current of 5mA to give us best noise performance. If we equally apportion the voltage we get the following circuit:-V INThe voltage gain of this circuit will be ~ – 700/700 = ~ -1, but we can bypass the emitter resistor as shown below:-V INFor DC the capacitor is open circuit and we have the emitter resistor back to 700 Ω. However at high frequencies the capacitor shorts out the 650Ω so that R E is now effectively 46Ω.The gain is now – (700/46) = -15. (-ve because it is inverting).De-generated MOS FET CircuitThe de-generated MOSFET circuit is an extension of the common-drain circuit except in this case we have a load on the drain as well as the source as shown in Figure 1. The resulting gain will be a ratio of R S/R D and the output resistance will ~ R D. The resistance looking into VX will increase and therefore will make this circuit useful as a current sink especially on the differential amplifier tail device where high R improves the CMMR.dI SVXROUT’Figure 1 Schematic and small signal model of the de-generated MOSFET circuit. Output ResistanceFirstly consider in the increase in the output resistance due to R OUT prime.If we apply a current source on V OUT of value I T current will try to flow to ground via the device current source as source resistor. If we tried to force current to flow we would find the voltage would greatly increase as a result of the high resistance R OUT prime.Therefore, referring to figure 2 we can show this circuit.dAs the gate has been grounded then vg = 0,Therefore, Vgs = Vg - Vs = 0 - R S.I TVgs = Vs = -R S.I TThe current source in the device gives rise to a currentI T = gm.Vgs, so theVoltage Vs = -gm.Vgs.RsThe voltage drop across RS adds current to the output ie.The total current at the output will be I T and the current from the current source connected to Rs.()()()()gm.Rs Rds. R then small is Rs as )gmRs Rds(1Rs I )gmRs Rds(1Rs I I VR Now )gmRs Rds(1Rs I Vget to factorise R I .I Rds.gm.R Rds.I ie out multiply R I .I gm.R I Rds V 1equation in Sub R I Rds.Ids Vs Vds V (1)- gm.Rs.I I Ids OUT TT T T OUT T T S T T S T S T T S T T S T T T T ≈++=++==++=++++=+=+=+=This circuit exhibits negative feedback which gives rise to the increased resistance.Voltage Gain (Av)From the above equations we now easily calculate the voltage gain of the degenerated MOSFET circuit ie())gmRs Rds(1Rs I V V and .RsI Vs Vgs V work previous the from V VAv T T OUT T IN INOUT++======()()S IN OUT SIN OUT S T T T IN OUT T T OUT T IN R Rds V V to reduces this so Rds than is term Rds.gm the R Rds.gmRds 1V V R )gmRs Rds(1Rs give to cancel I .Rs I )gmRs Rds(1Rs I V V therefore)gmRs Rds(1Rs I V V and .RsI Vs Vgs V =<<++=∴++++=++=====Input resistanceThe input resistance of the circuit will be very, very high.The ADS simulation of figure 3 shows a simple common-source circuit. However, there is an ideal bias supply to the drain ie supplies only DC and is an open-circuit to AC/RF. There is also a DC decoupled S-parameter termination connected to Vout and set to a very highimpedance. This allows measurement of the resistance looking into the Vout port, setting the termination value very high ensures it doesn’t interfere with the already high impedance caused by Rd.Note for the first plot if figure 4 the value of RS (R3) was set at 0 ohms.The ADS simulation was modified but the value of RS was increased to 2500ohms (there needed to be a slight alteration to the gate bias to restore the drain current back to 10uA).The second simulation plot is shown in figure 5 and shows how the resistance has increased from 9.5M Ω to 13M Ω. S_Param SP1Stop=10 MHzStart=1 MHz S-PARAMETERSDCACW=10EqnVar V_DC SRC1Vdc=5 VFigure 3 ADS simulation set-up for a simple common-source amplifier. ROUT will effectively be defined by Rd of the FET. The S-parameter DC decoupled terminal and simulation box allow the measurement of R OUT .Sheet5 of 5freq, MHzreal(Z(1,1))Figure 4 Simulation of the circuit shown in figure 3 with the source resistor RS (R3) set to 0 ohms (ie the circuit is configured as common-source). Output resistance is 9.5M ohms.real(Z(1,1))freq, MHzFigure 5 Simulation of the circuit shown in figure 3 with the source resistor RS (R3) set to 2500 ohms (ie the circuit is configured common-source with de-generation). Output resistance has now 13M ohms. NOTE there was a slight alteration to the gate bias to restore the drain current back to 10uA.。