A processor extension for cycle-accurate real-time software

SPECIFICA TIONSNI sbRIO-9637Single-Board RIO OEM DevicesThis document lists the specifications for the NI sbRIO-9637. The following specifications are typical for the -40 °C to +85 °C operating temperature range unless otherwise noted.Caution Do not operate the sbRIO-9637 in a manner not specified in thisdocument. Product misuse can result in a hazard. You can compromise the safetyprotection built into the product if the product is damaged in any way. If the productis damaged, return it to NI for repair.ProcessorType Xilinx Zynq-7000,XC7Z020 All Programmable SoC Architecture ARM Cortex-A9Speed667 MHzCores2Operating system NI Linux Real-Time (32 bit)Nonvolatile memory1512 MBV olatile memory (DRAM)512 MBReal-time clock, accuracy 5 ppmFlash reboot endurance2100,000 cyclesNote For information about the life span of the nonvolatile memory and about bestpractices for using nonvolatile memory, visit /info and enter the Info CodeSSDBP.1Formatted nonvolatile memory may be slightly less than this value.2You can increase the flash reboot endurance value by performing field maintenance on the device.If you expect that your application may exceed the maximum cycle count listed in this document, contact NI support for information about how to increase the reboot endurance value.Operating SystemNote For minimum software support information, visit /info and enter theInfo Code swsupport.Supported operating system NI Linux Real-Time (32-bit)Minimum software requirementsApplication softwareLabVIEW LabVIEW 2015,LabVIEW 2015 Real-Time Module,LabVIEW 2015 FPGA ModuleEclipse Edition 2014C/C++ Development Tools forNI Linux Real-Time3Driver software NI CompactRIO Device Drivers August 2015 Reconfigurable FPGAType Xilinx Zynq-7000,XC7Z020 All Programmable SoCNumber of logic cells85,000Number of flip-flops106,400Number of 6-input LUTs53,200220Number of DSP slices(18 x 25 multipliers)Available block RAM560 KBNumber of DMA channels16Number of logical interrupts32Network/Ethernet PortNumber of interfacesFront Panel Ethernet 1 (Eth0)3C/C++ Development Tools for NI Linux Real-Time is an optional interface for C/C++programming of the sbRIO-9637 processor. Visit /info and enter Info Code RIOCdev for more information about the C/C++ Development Tools for NI Linux Real-Time.2| | NI sbRIO-9637 SpecificationsNetwork interface10Base-T, 100Base-TX, and1000Base-T Ethernet4Compatibility IEEE 802.3Communication rates10 Mbps, 100 Mbps,1000 Mbps auto-negotiated, half-/full-duplex Maximum cabling distance100 m/segmentRS-232 (DTE) Serial PortNumber of interfacesOnboard RS-232 2 (Serial1, Serial2)Baud rate support ArbitraryMaximum baud rate230,400 bpsData bits5, 6, 7, 8Stop bits1, 2Parity Odd, Even, Mark, SpaceFlow control RTS/CTS, XON/XOFF, DTR/DSR, NoneRS-485 Serial PortNumber of interfacesOnboard RS-485 1 (Serial3)Maximum baud rate460,800 bpsData bits5, 6, 7, 8Stop bits1, 1.5, 2Parity Odd, Even, Mark, SpaceFlow control XON/XOFFWire mode4-wire, 2-wire, 2-wire autoIsolation voltage, port to earth ground None4For revision D and earlier, 1000Base-T Ethernet link and communication is not guaranteed for the Ethernet port below -20 °C. If you expect ambient temperatures below -20 °C, NI recommendsusing a 10/100 network infrastructure or assigning 10/100Mbps communication speeds to theEthernet Adapter in NI Measurement & Automation Explorer (MAX).NI sbRIO-9637 Specifications| © National Instruments| 3Embedded CANNumber of interfacesOnboard CAN 1 (CAN0)Onboard CAN transceiver NXP PCA82C251TMaximum baud rate 1 MbpsMinimum baud rate10 kbpsUSB PortNumber of interfacesFront Panel USB Host 1 (USB0)Compatibility USB 2.0, Hi-SpeedMaximum data rate480 Mb/sMaximum front panel USB current900 mASD Card SlotNumber of interfacesFront Panel SD 1 (SDIO0)Supported Standards SD, SDHC5Front Panel SD ThroughputRead12.0 MB/s maximumWrite9.0 MB/s maximum3.3 V Digital I/O on 50-Pin IDC Connector Number of DIO channels28Maximum tested current per channel±3 mAInput logic levelsInput low voltage, V IL-0.3 V minimum; 0.8 V maximum Input high voltage, V IH 2.0 V minimum; 5.25 V maximum5Both standard SD and microSD interfaces are supported.4| | NI sbRIO-9637 SpecificationsOutput logic levelsOutput high voltage, V OH2.4 V minimum;3.45 V maximumwhen sourcing 3 mA0.0 V minimum; 0.4 V maximumOutput low voltage, V OLwhen sinking 3 mAAnalog Input CharacteristicsNumber of channels16 single-ended or 8 differentialADC resolution16 bitsMaximum aggregate sampling rate200 kS/sInput range±10 V, ±5 V, ±2 V, ±1 VMaximum working voltage (signal + common mode)10 V range±11 V5 V range±10.5 V2 V range±9 V1 V range±8.5 VInput impedancePowered on> 1 GΩ in parallel with 100 pFPowered off/overload 2.3 kΩ minimumOvervoltage protectionPowered on±25 V, for up to 2 AI pinsPowered off±15VAI accuracyNI sbRIO-9637 Specifications| © National Instruments| 5Gain drift 12 ppm of reading/°C Offset drift 4 ppm of range/°C AI noise10 V range 200 μVrms 5 V range 105 μVrms 2 V range 45 μVrms 1 V range 30 μVrmsINL ±64 ppm of range, maximum DNLNo missing codes guaranteed CMRR, DC to 60 Hz -80 dB Input bandwidth (-3 dB)540 kHz, typical Settling error (multichannel scanning)±60 ppm step size, typical Crosstalk (10 kHz)-70 dBTypical performanceFigure 1. Common Mode Rejection Ratio versus FrequencyC M R R (d B )Frequency (Hz)6 | | NI sbRIO-9637 SpecificationsFigure 2. Normalized Signal Amplitude versus Frequency–8–7–6–5–4–3–2–101N o r m a l i z e d S i g n a l A m p l i t u d e (d B )Frequency (Hz)Figure 3. Settling Error versus Source ImpedanceE r r o r (p p m o f S t e p S i z e )Source Impedance (Ω)10010001000010000010000010000100010010Analog Output CharacteristicsNumber of channels 4DAC resolution16 bitsNI sbRIO-9637 Specifications | © National Instruments | 7Maximum update rate6336 kS/sRange±10 VOverrange operating voltageMinimum10.3 VTypical10.6 VMaximum10.9 VOutput impedance0.4 Ω typicalCurrent drive±3 mA/channel maximumProtection Short-circuit to groundPower-on state70 VAO accuracyGain drift23 ppm of reading/°COffset drift 5.4 ppm of range/°CINL±194 ppm of range, maximumDNL±16 ppm of range, maximumCapacitive drive 1.5 nF, typicalSlew rate 3.7 V / μsec, typicalSettling time (100 pF load to 320 μV)FS step50 μs2 V step12 μs0.2 V step9 μs6This is the maximum update rate when running one AO channel in a loop with the FPGA top-level clock set to 40 MHz.7When the analog output initializes, a voltage glitch occurs for about 20 μs, peaking at 1.3 V,typical.8Range is 5 V.8| | NI sbRIO-9637 SpecificationsCMOS BatteryNote The battery is user-replaceable. The NI sbRIO device ships with a BR1225coin cell battery from RAYOV AC, which is industrial-rated. Ensure that powerremains connected to the NI sbRIO device while you replace the battery so thattime-keeping is not disrupted. Refer to the Battery Replacement and Disposalsection for information about replacing the battery.10 yearsTypical battery life with power applied topower connectorTypical battery life in storage at 55 °C 2.5 years9Power Outputs on 50-Pin IDC ConnectorCaution This output is protected by a fuse. Exceeding the power limits may causethis fuse to open.+5 V power outputOutput voltage 5 V ±5%Maximum current 1.5 AMaximum ripple and noise50 mVPower RequirementsThe NI sbRIO device requires a power supply connected to the power connector. Refer to the Powering On the NI sbRIO Device section in the NI sbRIO-9637 Getting Started Guide on /manuals for information about connecting the power supply.Caution Exceeding the power limits may cause unpredictable device behavior.Recommended power supply55 W, 30 VDC maximumPower supply voltage range9 VDC to 30 VDCReversed-voltage protection30 VDCPower consumption26 W maximum9Battery life may drop dramatically in extreme temperatures.NI sbRIO-9637 Specifications| © National Instruments| 9EnvironmentalCaution Clean the sbRIO-9637 with a soft, nonmetallic brush. Make sure that thedevice is completely dry and free from contaminants before returning it to service.-40 °C to 85 °C10Local ambient operating temperature neardevice (IEC 60068-2-1, IEC 60068-2-2)Maximum reported onboard sensor temperatureCPU/FPGA temperature98 °CPrimary System temperature85 °CSecondary System temperature85 °CTable 1. Component Maximum Case TemperatureThe sbRIO-9637 includes three onboard temperature monitoring sensors to simplify validation of a thermal solution by indicating thermal performance during validation and deployment. The sensors measure the CPU/FPGA junction temperature and printed circuit board temperatures that can be used to approximate the primary and secondary side local ambient temperatures. This approach is called digital validation. Alternatively, the traditional analog approach using thermocouples can be used to validate thermal performance. The digital approach is more accurate for determining the performance of the CPU/FPGA but is more conservative for determining the local ambient temperatures. NI recommends using digital validation.For digital validation, ensure that the reported CPU/FPGA, reported Primary System, and reported Secondary System temperatures do not exceed any of the maximum temperatures listed in this document. Thermal validation is complete if the reported temperatures are within10If you expect ambient temperatures below -20 °C, NI recommends using a 10/100 network infrastructure or assigning 10/100Mbps communication speeds to the Ethernet Adapter in NI MAX.Refer to the Network/Ethernet Port section of this document for more information.11Use digital approach to ensure the on-chip temperature reading is below 98°C.10| | NI sbRIO-9637 Specificationsspecifications. For more information about how to access the onboard sensors, visit / info and enter the Info Code sbriosensors. If the reported Primary System temperature or reported Secondary System temperature exceed the maximum temperatures listed in this document then analog validation may be used for further verification.For analog validation, measure the local ambient temperature by placing thermocouples on both sides of the PCB, 5 mm (0.2 in.) from the board surface. Avoid placing thermocouples next to hot components such as the CPU/FPGA or near board edges, which can cause inaccurate temperature measurements. In addition to the local ambient temperature, the case temperature of the components should not exceed the recommended maximum case temperature.Note Some systems may require a heat sink or air flow to remain within themaximum allowed temperature ranges. You can mount the Thermal Kit forNI sbRIO-9607/9627/9637 (153901-02) heat spreader on the NI sbRIO device.Note The NI sbRIO device thermal performance is greatly influenced by severalfactors, including resource utilization, mounting, and adjacent power dissipation.These factors can substantially affect the achievable external ambient temperature atwhich the maximum local and reported temperatures are reached. NI recommendsadditional thermal design to remain within the maximum allowed temperatureranges. For information about and examples of environmental and design factors thatcan affect the thermal performance of NI sbRIO systems, visit /info and enterthe Info Code sbriocooling. For device-specific guidelines about enablingproper thermal design, refer to the NI sbRIO-9637 User Manual on /manuals.-40 °C to 85 °CStorage temperature(IEC 60068-2-1, IEC 60068-2-2)Operating humidity (IEC 60068-2-78)10% RH to 90% RH, noncondensing Storage humidity (IEC 60068-2-78)5% RH to 95% RH, noncondensing Maximum altitude5,000 mPollution Degree (IEC 60664)2The NI sbRIO device is intended for indoor use only.Physical CharacteristicsWeight128.7 g (4.540 oz)NI sbRIO-9637 Specifications| © National Instruments| 11Safety VoltagesConnect only voltages that are below these limits.V terminal to C terminal30 VDC maximum, Measurement Category I Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage. MAINS is a hazardous live electrical supply system that powers equipment. This category is for measurements of voltages from specially protected secondary circuits. Such voltage measurements include signal levels, special equipment, limited-energy parts of equipment, circuits powered by regulated low-voltage sources, and electronics.Caution Do not connect the sbRIO-9637 to signals or use for measurements withinMeasurement Categories II, III, or IV.Environmental ManagementNI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.For additional environmental information, refer to the Minimize Our Environmental Impact web page at /environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.Waste Electrical and Electronic Equipment (WEEE)EU Customers At the end of the product life cycle, all NI products must bedisposed of according to local laws and regulations. For more information abouthow to recycle NI products in your region, visit /environment/weee.Battery Replacement and DisposalBattery Directive This device contains a long-life coin cell battery. If you need toreplace it, use the Return Material Authorization (RMA) process or contact anauthorized National Instruments service representative. For more information aboutcompliance with the EU Battery Directive 2006/66/EC about Batteries andAccumulators and Waste Batteries and Accumulators, visit /environment/batterydirective.12| | NI sbRIO-9637 Specifications电子信息产品污染控制管理办法（中国RoHS）中国客户National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。

Intel® System Debugger 2019Intel® Debug Extensions for WinDbg* 2019 Installation Guide and Release NotesInstallation Guide and Release Notes for Windows* host9 July 2018Contents1Introduction (3)1.1Technical Support and Documentation (3)1.2Product Contents (3)2What's New for the Intel® Debug Extension for WinDbg* 2019 Beta (4)3System Requirements (4)3.1Host System Requirements (4)3.2Target System Requirements (4)4Installation (4)4.1Pre-Installation Steps (4)4.2Product Installation (4)5Some Usages of Intel® Debug Extensions for WinDbg* (5)5.1Event-based debugging using breakpoints (5)5.2Collecting BSOD information by get_bsod_info (5)6Known Limitations (6)7Troubleshooting (6)7.1Error message “Unable to read debugger data block header” in WinDBG* (6)8Change History (7)8.1Intel® System Debugger 2018 Update 1 (7)8.2Intel® System Debugger 2018 Initial Release (7)8.3Intel® Debug Extension for WinDbg* 2018 Beta (7)8.4Intel® Debug Extension for WinDbg* 2017 Update 3 (7)Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 18.5Intel® Debug Extension for WinDbg* 2017 Update 2 (7)8.6Intel® Debug Extension for WinDbg* 2017 (Update 1) (7)8.7Intel® Debug Extension for WinDbg* 2017 (Initial Release) (7)9Attributions (8)10Disclaimer and Legal Information (10)Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 21 IntroductionThe Intel® Debug Extensions for WinDbg* 2019 is a component of the Intel® System Debugger 2019 and is an add-on to the Microsoft WinDbg* debugger to support Intel® Processor Trace. The extension allows for easy setup of Intel® Processor Trace (Intel® PT) by abstracting hardware configuration and then reconstructing and displaying execution flow from the collected trace data. It integrates with other WinDbg* features like symbolization and high-level source display.Intel® Processor Trace is a new technology for low-overhead execution tracing. It facilitates debugging a program by exposing an accurate and detailed trace of the program’s activity, and its trigg ering and filtering capabilities help identifying and isolating the relevant program executions.1.1Technical Support and DocumentationThe default installation directory of the Intel® System Studio including the Intel® System Debugger, in the following also called <INSTALLDIR>, isC:\Program Files (x86)\IntelSWTools\This installation directory can be specified by the user with a 'Custom' installation. The product however is being installed in a fixed directory structure below <INSTALLDIR>.All information about the Intel® Debug Extensions for WinDbg* can be found under <INSTALLDIR>\documentation_2019\en\debugger\system_studio_2019\windbg-ext\If you did not register your System Studio license yet, please do so at the Intel® Software Development Products Registration Center. Registration entitles you to free technical support,product updates and upgrades for the duration of the support term.To submit issues related to this product please visit the Online Service Center webpage and submit issues under the product Intel® System Studio.Additionally you may submit questions and browse issues in the Intel® System Studio User Forum.For information about how to find Technical Support, product documentation and samples, please visit /en-us/intel-system-studio.Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.1.2Product Contents∙Intel® System Debugger 2019 including∙Intel® Debug Extensions for WinDbg* for Intel® Processor TraceIntel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 32 What's New for the Intel® Debug Extension for WinDbg* 2019 Beta∙Users can configure and decode timestamps for the instruction trace.3 System Requirements3.1Host System RequirementsMicrosoft* Windows* 7, 8 and 10 64-bit host system.Windows* Driver Kit* (WDK) 10*, available under the download link:https:///en-us/windows/hardware/dn913721.aspx3.2Target System Requirements∙The Intel® Debug Extensions for WinDbg* for Intel® Processor Trace feature requires a 6th generation Intel® Core Processor (Skylake)∙The Intel® Debug Extensions for WinDbg* for IA JTAG debugging feature is tested on 6th generation Intel® Core Processor (Skylake) and Intel® Atom™ Processor Z36xx, Z37xx - 2 cores (Baytrail / MinnowBoard MAX) (see chapter 5 for details). The feature should work on any supported platform running windows but these are the platforms where functionality is verified.∙The Intel® Debug Extensions for WinDbg* for IA JTAG debugging feature is supported on Intel® Atom™Processors N4200, N3350, x7-E3950, x5-39xx (Apollo Lake), Intel® Xeon™ Scalable Processor (Skylake-SP) / Intel C620 Series Chipset (Lewisburg) and 7th generation Intel® Core™Processor as well.4 Installation4.1Pre-Installation StepsIntel® Debug Extensions for WinDbg* for IA JTAG debugging feature requires the Microsoft Windows* Software Development Kit* - Windows 10* to operate properly (see "System Requirements”).4.2Product InstallationThe Intel® Debug Extensions for WinDbg* 2019 on Windows* host is included in the Intel® System Studio 2019 package.Double-click on the executable file system_studio_2019.0.xxx_windows_target.exe or system_studio_2019.0.xxx_windows_target_online.exe to begin installation and follow the on-screen instructions.The default installation directory of the WinDbg Extension component is:Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 4<INSTALLDIR>\system_debugger_2019\windbg-ext\5 Some Usages of Intel® Debug Extensions for WinDbg*5.1Event-based debugging using breakpointsIntel® Debug Extensions for WinDbg* doesn't have an agent-based solution and cannot be notified from OS Windows that messages got sent. In order to capture this omission, we introduce the event-based debugging using breakpoints. The user could set conditional breakpoints on kernel function and print required fields using the command line like: bp ACPI!ACPIInterruptServiceRoutine ".echo ACPI Interrupt!; g".∙bp ACPI!ACPIInterruptServiceRoutine is for setting a breakpoint at the ACPI interrupt function and the process will be paused when the function is invoked. This function is for dealing with the ACPI interrupts. That’s why we call it as the event-base debugging.∙".echo ACPI Interrupt!; g" combines two actions which will be executed when the process breaks at the function ACPIInterruptServiceRoutine(). The command ".echo ACPI Interrupt!" to output a message “ACPI Interrupt!” in the kernel debug view on WinDbg* and the command ".echo ACPI Interrupt!" and the command "g" is to make the process go back running.We can also get the raw data of registers by the command like: bp nt!DbgPrintEx "da r8; g".∙bp nt!DbgPrintEx is for setting a breakpoint to halt the CPU when the Windows function DbgPrintEx() is invoked.∙"da r8; g"is also for displaying the content of register r8 by da when the nt!DbgPrintEx gets hit5.2Collecting BSOD information by get_bsod_infoA smart script get_bsod_info is developed for helping users to collect useful data based on what error code it gets from Windows BSOD. When BSOD happens, the user just need to launch Intel® Debug Extensions for WinDbg* and type in the command forensic.get_bsod_info(r“<filename>”)#. Then the script will help to do the corresponding commands and output the data into the designated file for analysis. For example:Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 5In this case, the script detects the error code belong to DRIVER_IRQL_NOT_LESS_OR_EQUAL (bug check 0xD1). So, it helps to run the commands “!analyze -v” and “!thread” for collecting necessary data. Once it’s done, the user can read the log file for analysis like6 Known LimitationsThe following limitations apply only to the Intel® Debug Extensions for WinDbg* for IA JTAG debugging feature.∙ A data breakpoint can be set on the first thread only.∙If connection to target fails, process “dllhost” is not killed automatically. The process must be killed manually to be able to try connection again.∙Breakpoint skip count is not supported.∙Execution HW breakpoints is not supported.∙Feature has been tested ono Intel® Atom™ Processor Z36xx, Z37xx - 2 cores (Baytrail / MinnowBoard MAX) under 32- and 64-bit Windows Embedded* 8.1o6th Gen Intel® Core™ Processor based system and 64-bit Windows 10 preview7 Troubleshooting7.1Error message “Unable to read debugger data block header” in WinDBG*The error message “Unable to read debugger data block header” indicates that on the target the kernel debugging is not activated.Activate kernel debugging by executing the command “bcdedit /debug on” on the target in a command prompt.Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 68 Change HistoryBelow are features listed for older versions of the Intel® System Debugger releases.8.1Intel® System Debugger 2018 Update 1∙Support event-based breakpoints to debug ACPI Machine Language (AML)∙Collect BSOD information with the get_bsod_info script8.2Intel® System Debugger 2018 Initial ReleaseNo changes8.3Intel® Debug Extension for WinDbg* 2018 Beta∙WinDbg* support Windows Driver Kit (WDK) version 1703. Added support for a new eXDI callback (DBGENG_EXDI_IOCTL_V3_GET_NT_BASE_ADDRESS_VALUE) to locate windows key structure KdVersionBlock.∙Extended Intel® Debug Extensions for WinDbg* for Intel® Processor Trace plugin to support Windows public symbol information.∙Extended Intel® Debug Extensions for WinDbg* for Intel® Processor Trace plugin to support ring3 tracing.∙Extended Intel® Debug Extensions for WinDbg* for Intel® Processor Trace plugin to support decoding Intel® Processor Trace data from crash dump.8.4Intel® Debug Extension for WinDbg* 2017 Update 3No change8.5Intel® Debug Extension for WinDbg* 2017 Update 2∙Installation improvements especially regarding Python* setup∙Added a WinDBG* theme∙I mproved error messaging and reduced number of verbose messages during start.∙Print a warning if Kernel Debug on the target is not enabled.∙Add checks is Windows running for Windows debug use cases∙Deleting breakpoints works again for all targets.∙Improved error handling∙New Intel® Debug Extensions for WinDbg* welcome banner∙Updated user guide8.6Intel® Debug Extension for WinDbg* 2017 (Update 1)No changes8.7Intel® Debug Extension for WinDbg* 2017 (Initial Release)∙Installation improvements especially regarding Python* setup∙Added a WinDBG* theme∙Fixed issues regarding debugging with Intel® Processor Trace∙The Intel® Debug Extensions for WinDbg* comprise the following features:∙Intel® Debug Extensions for WinDbg* for IA JTAG debuggingIntel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 7The Intel® Debug Extensions for WinDbg* for IA JTAG debugging (IA JTAG) enables theconnection of WinDbg* to a target over the Joint Test Action Group (JTAG). The server actsas a mediator and forwards the calls from WindDbg* to the IPC interface and back.Intel® Debug Extensions for WinDbg* for Intel® Processor TraceThe Intel® Debug Extensions for WinDbg* for Intel® Processor Trace (Intel® PT) is designed to help WinDbg* users by extending their debugging tool set with execution tracing. Theextension allows for easy setup of Intel® PT by abstracting hardware configuration and thenreconstructing and displaying execution flow from the collected trace data. It will integratewith other WinDbg* features like symbolization and high-level source display.9 AttributionsPortions of this software were originally based on the following:- software copyright (c) 1999, IBM Corporation., .- software copyright (c) 1999, Sun Microsystems., .- the W3C consortium () ,- the SAX project ()- voluntary contributions made by Paul Eng on behalf of theApache Software Foundation that were originally developed at iClick, Inc.,software copyright (c) 1999.This product includes updcrc macro,Satchell Evaluations and Chuck Forsberg.Copyright (C) 1986 Stephen Satchell.This product includes software developed by the MX4J project().This product includes ICU 1.8.1 and later.Copyright (c) 1995-2006 International Business Machines Corporation and others.Portions copyright (c) 1997-2007 Cypress Semiconductor Corporation.All rights reserved.This product includes XORP.Copyright (c) 2001-2004 International Computer Science InstituteThis product includes software from the book"Linux Device Drivers" by Alessandro Rubini and Jonathan Corbet,published by O'Reilly & Associates.Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 8This product includes hashtab.c.Bob Jenkins, 1996.Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 910 Disclaimer and Legal InformationNo license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps.The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request.Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at , or from the OEM or retailer.Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting /design/literature.htm.Intel, the Intel logo, Xeon, and Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries.Optimization Notice: Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.Notice Revision #20110804*Other names and brands may be claimed as the property of others© 2017 Intel Corporation.Intel® System Debugger 2019 – Intel® Debug Extensions for WinDbg* Release Notes 10。

realtime pcr操作流程英文回答：Real-time PCR, also known as quantitative PCR (qPCR), is a widely used technique in molecular biology to detect and quantify DNA or RNA molecules. It is a sensitive and accurate method that allows researchers to measure gene expression levels, identify genetic variations, and detect pathogens.The general workflow of a real-time PCR experiment involves several steps:1. Sample preparation: This step involves extracting DNA or RNA from the sample of interest. Various methods can be used for sample preparation, such as phenol-chloroform extraction, column-based purification kits, or automated extraction systems. The quality and purity of the extracted nucleic acids are crucial for the success of the PCR reaction.2. Primer design: Primers are short DNA sequences that specifically bind to the target DNA or RNA region of interest. They are designed using bioinformatics tools and should have high specificity and minimal secondary structures. The forward and reverse primers are designed to flank the target sequence, and ideally, they should have similar melting temperatures.3. Reaction setup: The PCR reaction mixture is prepared by combining the extracted nucleic acids, primers, a DNA polymerase enzyme, and a fluorescent dye or probe. The reaction mixture is typically prepared in a PCR tube or plate. It is important to maintain proper aseptic techniques to prevent contamination.4. Thermal cycling: The PCR reaction goes through a series of temperature cycles in a thermal cycler machine. These cycles typically include denaturation, annealing, and extension steps. The denaturation step separates the DNA double strands, the annealing step allows the primers to bind to the target sequence, and the extension stepsynthesizes new DNA strands using the primers as templates. The number of cycles depends on the initial amount oftarget nucleic acid and the desired level of amplification.5. Data collection and analysis: Real-time PCR instruments monitor the fluorescence emitted by the fluorescent dye or probe during each cycle. The fluorescence signal increases proportionally to the amount of amplified DNA or RNA. The data can be plotted in a graph called the amplification curve, which shows the exponential growth of the target sequence. The threshold cycle (Ct) value, which represents the cycle number at which the fluorescence signal crosses a predetermined threshold, is used to quantify the initial amount of target nucleic acid.Real-time PCR is a versatile technique that can be adapted to various applications, including gene expression analysis, pathogen detection, and genetic testing. Itoffers high sensitivity, specificity, and quantification accuracy, making it an essential tool in molecular biology research and diagnostic laboratories.中文回答：实时荧光定量PCR（real-time PCR），也被称为定量PCR （qPCR），是分子生物学中广泛使用的一种技术，用于检测和定量DNA或RNA分子。

Quantitative real-time rapidPCR qTOWER | Quantitative real-time rapidPCRCombination of rapidPCR with real-time fluorescence detection Ideal for daily routine diagnosticsSimple and fast result analysis integrated into control softwareqTOWER | New, faster and easier quantitative real-time PCR New, faster and easier quantitative real-time PCR The qTOWER for routine real-time diagnostics is based on a novel fiber optical system patented by Analytik Jena. Furthermore it combines the advantages of exceptionally fast rapidPCR with ramping rates up to 12 °C/sec and a considerably sample consumption down to 5 µl per reaction. The test principle is build on robust homogeneous exonuclease assay or simple intercalating dyes, like SybrGreen. The detection of fluorescence signals takes place during each cycle, user-defined either during denaturation, annealing or elongation. Thereby the device is also suitable for easiest multi-component analysis.Subject to changes in design and scope of delivery as well as further technical development!March 2010, Analytik Jena AGAnalytik Jena AG Life ScienceKonrad-Zuse-Strasse 107745 Jena / Germany*****************************Phone +49 (0) 36 41 77 - 94 00Fax +49 (0) 36 41 77 - 76 77 76qPCRsoft – simple and clearBasis for the final analysis of the real-time PCR curves is the integrated software qPCRsoft. With this software the analytical evaluation of measured fluorescence signals referring to methods like absolute or relative quantification, delta-delta ct, allele discrimination or PCR efficiencies takes place. This control and analysis software allows the accurate determi-nation of concentrations or available allele conditions as well as ratios of expressions. Furthermore the complete system is extreme fast and permits the measurement by means of observing qPCR curves including analysis of up to 96 samples in parallel within less than 60 minutes. Thus the qTOWER in combination with qPCRsoft software represents an excellent, highly flexible and really fast real-time PCR device.Intuitive, fast and easy operation are hallmarks of the qTOWER software. It not only controls the rapidPCR reaction and recording of fluorescence signals per cycle, it also enables the final data analysis by a wide choice of different qPCR methods. Prepared for the futureTo meet different demands of applications, the qTOWER can be equipped with up to 4 different color modules for excitation and emission. Thereby the qTOWER can be customized, as a choice of the user out of 9 different available color modules. This keeps the system open for individually adaptations or changes. Therefore the instrument is ideally suited for multiplex applications and covers most currently available dyestuffs.9 different color modules available, including 4 FRET filters Open for individually adaptations or changesRead-out of 96 wells within 4 seconds, independent of the number of dyesIntegrated control and analysis software qPCRsoftReal-time PCR and analysis of 96 samples in parallel within less than 60 minutesVariety of methods for data analysis Absolute and relative quantificationPCR efficiency and delta-delta ct methodDiscrimination of allele conditions and determination of expression ratiosQuantitative real-time fluorescence detectionCombines advantages of rapidPCR with enormous sample consumptionHeating rates of up to 12 °C/sec and cooling rates of up to 8 °C/secSample consumption down to 5 µlAdditionally Analytik Jena’s SPS SPS ( (S S ample-P rotection-rotection-S S ystems) ensures best protection of the samples inside the thermal block, by cooling down to 20 °C during heat up of the slided lid, prior to start of the PCR. Thereby the maximum set temperature of 120 °C and the automatic, high contact pressure ensure best sample recovery without any conden-sation, even in case of small reaction volumes. Integrated 96 well LPR thermal block for rapidPCR using qTOWERAvailable color and FRET modulesExcitation (nm)Emission (nm)Detected Dyes (Examples)Color module 1470520FAM, SybrGreen, Alexa488Color module 2515545JOE, HEX, VIC, YakimaYellow Color module 3535580TAMRA, DFO, Alexa546, NED Color module 4565605ROX, TexasRed, Cy3.5Color module 5630670Cy5, Alexa633, Quasar670FRET 1470580FAM (donor) / / TAMRA (acceptor)FRET 2470670FAM (donor) / / Cy5 (acceptor)FRET 3470705FAM (donor) / / Cy5.5 (acceptor)FRET 4515670JOE (donor) / / Cy5 (acceptor)This is a Licensed Real-Time Thermal Cycler(s) or Licensed Real-Time Temperature Cycling Instrument(s) under ABI’s United States Patent No. 6,814,934 and corresponding claims in non-U.S. counterparts thereof, for use in research and for all other applied fields except human in vitro diagnostics. No right is conveyed expressly, by implication or by estoppel under any other patent claim.。

High Resolution 22” Wide LCD Monitor provides Superior Image Quality in Live View and Playback Built-in Pentaplex Digital Video Recorder, 8 Camera-Capable, with Advanced Real Time Recording (240FPS)Internet Remote Monitoring* (Software included), Web Browser access and E-mail alerts High Resolution Weather Proof ** Cameras included with up to 50ft (15m) Night Vision range***Large Capacity Security Certified Hard Drive pre-installed expandable up to 1000GB**** USB ports for back up and convenient transferring of critical data Mouse Driven Navigation (mouse included) and Graphical User Interface Installer Friendly - Easy Quick Start Guide and installation video on the system with Toll Free Tech Support Multi function display - PC Monitor, Digital Picture Frame & Component Video with picture in picture function while DVR records in the background »»»»»»»»»FEATURESThis product redefines how people use a surveillance system by turning it into a multi-function unit that provides practical and intuitive utility for a wide range of business and homeapplications. It is the first system of its kind to offer a professional solution designed for surveillance that also works as a PC monitor, an entertainment video display and a Digital Picture Frame.Protect what matters to you most. This 8 channel recording solution with 4 or 8 high resolution cameras provides an expandable solution. Record your critical data on a pre-installed 500GB security certified hard drive that is designed to work 24/7. Indoor/Outdoor night vision cameras provide excellent image quality in all lighting conditions, utilizing the automatic IR filtering mechanism.Connect to your system over the internet regardless of your physical location. Control multiple systems remotely with the included software.Innovative, practical and intuitive. A reliable solution that will exceed your expectations.HOME & BUSINESS SECURITYALL-IN-ONE INTEGRATED, MULTI FUNCTION, USER FRIENDLY22” WIDE SCREEN LCD MONITOR WITH BUILT-IN 8 CHANNEL DIGITAL VIDEORECORDER & HIGH RESOLUTION DAY/NIGHTCOLOR CAMERASSecurityPC MonitorEntertainmentPicture FrameInstallation GuidePublic View MonitorInternet Remote MonitoringMonitor/Interface:22” Wide screen LCD with user selectable aspect ratio (Wide 16:9, Standard 4:3) Professional Grade High Resolution (1680 x 1050) Glossy LCD panel VGA Input - use your LCD Display as a PC monitorUSB picture frame feature - display digital pictures from a USB flash drive Entertainment Component Video input (YPbPr)PIP (Picture In Picture) functionally in VGA/Component and Picture Frame mode while still recording in the backgroundReverse PIP (Picture-In-Picture) of Component Video or PC while in DVR mode Spot Video Out supports a connection to another monitor to display video in a different location (e.g. Public View Monitor)Multiple control options; front panel buttons, remote control, mouse, remote softwareTri-lingual On Screen Display (English, Spanish, French)Screen saver for energy efficiency Wall mountable (VESA standard)Stand with cable management solutionEnvironmentally friendly, recyclable packaging materialDigital Video Recorder:8 Channels with Pentaplex operation - View, Record, Playback, Back Up & Remotely Control the system simultaneously MPEG4 Digital Video Compression - small file sizes without compromising video qualityRecording Frames Per Second (FPS): 240/200 (NTSC/PAL) @ 352X240 Recording Resolution: 704x480, 704x240, 352x240(NTSC), 704x576, 704x288, 352x288(PAL)Custom recording for each cameraCovert Camera - record without displaying camera imageContinuous Recording with Motion Event logging for easy event searching Selectable 4 channel audio recording Programmable motion detectionPre-Event Recording of a preset amount of time before motion triggers the recording to see activities leading up to an eventHard Drive with SATA interface, 100% duty cycle for optimal performance in the commercial video security market. Expandable up to 1000GB****S.M.A.R.T HDD Support (Self-Monitoring Analysis and Reporting Technology): Auto Detection / Recovery to ensure the HDD is functioning properly at all timesSupports external USB: Hard Drive, Optical Drive (DVDRW, CDRW) and Flash DriveScheduled back up to an external USB storage and Network Storage Using FTPWatermarking of video files to encrypt the data 8 Programmable Alarm Inputs, 1 Relay Alarm output Pan/Tilt/Zoom Camera Control: RS-485 interface Network Protocol: TCP/IP, DDNS and Web»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»»Cameras SG7540:High resolution image sensor produces sharp and clear video with 450 TV Lines 18 IR LEDs provide night vision range of 50ft (15m)*IR cut filter provides accurate color reproduction in all lighting conditions Advanced Day/Night mode: Picture automatically switches to B&W delivering better clarity in low light conditionsWeatherproof Design: Ideal for outdoor and indoor applications (IP66**)Built-in microphone provides one way audio from camera to the system 60 ft (18m) DIN weatherproof (IP66)** extension cable included per camera All-in-one camera cable (providing video, audio & power) plugs directly to the monitor and eliminates the need for a separate power adaptor, when connected to a DIN portCeiling or wall mountable cameras with versatile stand provides flexible mounting optionsCameras CVC6993R (optional):Advanced High Resolution Image Sensor -Produces Sharp and Clear Video with 450 TV Lines 30 IR LEDs Night Vision Range of 50ft (15m)*True Day/Night Operation using Built-in IR Filter Changeable Mechanism to Achieve Accurate Color Representation in Varying Lighting Conditions Advanced Day/Night mode: Picture Automatically Switches to B&W delivering Better Clarity in Low Light ConditionsWeatherproof Design: Ideal for Outdoor and Indoor applications (IP66**)Software:Remote monitoring software supporting multiple sites (up to 16 cameras) with full remote control over the Internet or Local Area Network (LAN)Internet Remote Functions: Live View, Live Recording, Search, Set-up, Back-upFirmware Upgrade over networkEmail alerts with a web browser link (DDNS signup required)Microsoft Windows XP™, Window Vista™ Compatible Software (included)Free DDNS Service»»»»»»»»»»»»»»»»»»»»* Requires a high speed internet connection and router - not included ** Not intended for submersion in water*** IR illumination range up to 50 ft (15M) under ideal conditions. Objects at or beyond this range may be partially orcompletely obscured, depending on the camera application.**** Recording capacity may vary based on recording resolution & quality, lighting conditions and movement in the sceneBACK PANEL:PTZAlarm BlockComponent Input (YPbPr)BNC Video inputs Audio inputsSpot OutAudio OutVGADIN Camera inputsSPECIFICATIONS:Includes:Supply, Ethernet cable, Software application CD, MouseL22WD804501 Package- LCD DVR- 4 x SG7540 Cameras CVC6993R Camera Pack: 4.1 KG / 9.1 LBSPackage Dimensions:System: 650mm x 550mm x 271mm / 25.6” x 21.7” x 10.7” (W x H x D)CVC6993R Camera Pack: 310mm/12.2”(W) x 310mm/12.2”(D) x 150mm/5.9”(H). Package Cube: 0.51CBF / 0.02CBM©2009 Lorex Technology Inc.Lorex Technology Inc.Monitor:LCD:22” Wide Screen LCD Resolution: 1680 x 1050Monitor display: Real time 240FPS (NTSC), 200 FPS (PAL) Image size: 3-5 Kbyte (352x240, 352x288) (NTSC, PAL) 5-10 Kbyte (704x240, 704x288) (NTSC, PAL)6-16 Kbyte (704x480, 704x576) (NTSC, PAL)Video inputs: 4 x DIN, 8 x BNCVideo outputs: Programmable Spot Out (BNC)Audio inputs: 4 x line-in, RCA sockets Audio output: 1 x line-out, RCA socket VGA input: Included Component input: YPbPrSupply Voltage: 100VAC-240VAC, 12VDC, 6.67A, 60/50Hz Power consumption: Approx. 65WTemperature range: 5° ~ 40° C / 41° ~ 104° F Weight: 8.7 kg / 19.3 lbsDimensions: 21” X 14.4” X 2.7” / 532mm X 365mm X 67mm (without stand)21” X 17” X 7.4” / 532mm X 433mm X 188mm (with stand)DVR:Hard disk capacity: SATA Interface (Max 1000 GB), 100% duty cycle,Backup: USB Default (USB memory stick, USB HDD), USB Optical Drive(CDRW, DVDRW)Back-up file formats: AVI, JPG, BMP Compression: MPEG4Recording speed: 240/200 (NTSC/PAL) @ 352x240 120/100 (NTSC/PAL) @ 704x24060/50 (NTSC/PAL) @ 704x480Record Scheduling: Hourly, Daily, Weekly adjustable per channelPre/Post alarm recording: 5 seconds (Pre); 3 minutes (Post), programmable per camera Event/Log search: Up to 100,000 for user login/out,configuration changes, remote access, connects/disconnects Playback: Single, Quad or 8CH Simultaneous Alarm inputs: 8 x TTL, programmable as NC/NOAlarm outputs: 1 x Relay with NO/NC contact; 30VDC/1A, 125VAC/0.5A resistive Activity detection: 16 x 16 grid, Sensitivity levels: 10PTZ Control: RS-485 interfaceRemote Functions: Live View, Live Recording, Search, Set-up, Back-up Network Speed Control: 8 levels (56Kb ~ 8MB)/work Protocol: TCP/IP, DDNS and Web Network Interface:10/100-Base-TX, RJ-45Camera: CVC6993R (optional)Image Sensor: High Resolution 1/4” Advanced Color Image Sensor Video Format: NTSC Effective Pixels: H: 656, V: 492Resolution: 450 TV Line Scan System: 2:1 Interlace Sync System: Internal S/N Ratio: More than 48dB Iris:AESAES Shutter Speed: 1/60~1/50,000 SecMini Illumination: 0.6 Lux without IR LED, 0 Lux with IR LED Video Output: Composite 1.0Vpp @ 75 ohm Lens/ Lens Mount: 5mm F 2.0/ Fixed FOV (Diagonal): 50 degrees Termination: BNC Type IR LED/ Night Vision Range: 30 pieces / 850 nm / 50ftPower Requirement: 12VdcPower Consumption: 220 mA or 3W max Operating Temp Range: -10° ~ 50° C (14° ~ 122° F)Environmental Rating:IP 66Monitor67mm/2.6”188mm/7.4”Camera: SG7540Image Sensor: High Resolution 1/4” Color Image Sensor Video Format: NTSCEffective Pixels: H: 656, V: 492Resolution: 450 TV Lines Scan System: 2:1 Interlace Sync System: InternalS/N Ratio: More than 48dB Iris:AESAES Shutter Speed: 1/60~1/50,000 SecMini Illumination: 3.0 Lux without IR LED, 0 Lux with IR LED Video Output: 1.0Vpp @ 75 ohm Lens/ Lens Mount: 3.6mm F 2.0/ Fixed FOV (Diagonal): 73 degrees Termination:6 pin DINIR LED/ Night Vision Range: 18 pieces / 850 nm / 50ft/15m Power Requirement: 12Vdc Power Consumption: 280 mAOperating Temp Range: -10° ~ 50° C (14° ~ 122°F)Environmental Rating: IP 66。

常见英文缩写(D C S、P L C)-CAL-FENGHAI-(2020YEAR-YICAI)_JINGBIANHMI—Human Machine Interface（人机界面）HTML—Hyper Text Markup Language（超文本链接标示语言）CM——Control Module控制模块SCM——Sequential Control Module顺序控制模块CPM——Control Processing Module控制处理模块CEE——Control Execution Environment控制执行环境CNI——Control Net Interface控制网络接口C200——Control processor控制处理器RM——Redundancy Module冗余模块IOMs——input/output Modules输入/输出模块SCE——Simulation Control Module模拟控制模块ACE——Application Control Module应用控制模块IOLIM——IO Link Interface Module接口模块FIM——Fieldbus Inerface Module现场总线模块PMIO—Process Manager Input/Output流程管理器输入/输出FTA-Field Termination AssembliesIOP——Input/Output Processor (card) 输入/输出处理器（卡）ERDB——Engineering Repository Database工程数据库EMDB—Enterprise model database企业模型数据库RTDB—Real Time Database实时数据库ODBC—Open Database Connectivity开放式数据库连接SQL—Structured Query Language结构化查询语言PV—Process Value工艺价值SCADA—Supervisory control and data acquisition监督控制和数据采集FTE-fault tolerant Ethernet容错以太网CP-control processor控制处理器CNI-control net interface控制网接口FTEB-fault tolerant Ethernet bridge容错以太网桥RM-redundancy module冗余模块FIM-fieldbus interface module现场总线接口模块OPC-OLE for process control用于过程控制ACE-application control environment（应用控制环境）DSA-distributed system architecture分布式系统架构CEE-control execute environment控制执行环境ES-CE --Console Extension Station控制扩展控制站ES-F --Experion Flex StationES-C --Experion Console StationFTA--Field Termination Assembly (for Serial Interface) CDA server ：Contorl Data Access Server 控制数据接入服务器OPC：OLE for process controlDSA：disbuted system Architecture 分布式系统结构FTE：fault tolerant Ethernet??容错以太网RTD：热电阻T/C：热电偶PIM：pulse Input Module 脉冲输入模块SIM：Serial Interface Module 串口接口模块SIEMENS PLC常用英语缩写表集散控制系统——Distributed Control System（DCS）现场总线控制系统——Fieldbus Control System（FCS）监控及数据采集系统——Supervisory Control And Data Acqusition（SCADA）可编程序控制器——Programmable Logic Controller（PLC）可编程计算机控制器——Programmable Computer Controller（PCC）工厂自动化——Factory Automation（FA）过程自动化——Process Automation（PA）办公自动化——Office Automation（OA）管理信息系统——Management Information System（MIS）楼宇自动化系统——Building Automation System人机界面——Human Machine Interface（HMI）工控机——Industrial Personal Computer（IPC）单片机——Single Chip Microprocessor计算机数控（CNC）远程测控终端——Remote Terminal Unit（RTU）上位机——Supervisory Computer图形用户界面（GUI）人工智能——Artificial Intelligent（AI）智能终端——Intelligent Terminal模糊控制——Fuzzy Control组态——Configuration仿真——Simulation冗余——Redundant客户/服务器——Client/Server网络——Network设备网——DeviceNET基金会现场总线——foundation fieldbus（FF）现场总线——Fieldbus以太网——Ethernet变频器——Inverter脉宽调制——Pulse Width Modulation（PWM）伺服驱动器——Servo Driver软起动器——Soft Starter步进——Step-by-Step控制阀——Control Valver流量计——Flowmeter仪表——Instrument记录仪—— Recorder传感器——Sensor智能传感器——Smart Sensor智能变送器——Smart Transducer虚拟仪器——Virtual Instrument主站/从站——Master Station/Slave station操作员站/工程师站/管理员站——Operator Station/Engineer Station/Manager StationDCS画面常用常用缩写词语1ST1级FRQ频率A报警FSH末级过热器ADS自动调度系统FSSS炉膛安全监测系统AGC自动发电机控制FW给水AH空气预热器FWP给水泵AS轴向位移GC高压调门控制ATC汽轮机自动控制GEN发电机AUTO自动GV（高压）调节汽门AUX辅助的HH高高BASE基本HAV暖通BCP炉水循环泵HDR联箱，集箱BD排污HP高压缸BF锅炉跟随HTR加热器BFP锅炉给水泵IC中压调门控制BMCR锅炉最大连续出力ID标志，标识BMP燃烧器管理系统IDF引风机BOP轴承油泵IMP冲动式（级）BP旁路INCR提高，增加BRG轴承INTERM定期，间断BTG锅炉－汽机－发电机IV中压调门C切换LL低低CAF冷却风机LDC负荷指令计算机CAMP控制＋报警＋监测＋保护LOP顶轴油泵CCCW闭式循环冷却水Lp低压CCS协调控制系统LSH低温过热器CDSR凝汽器LUB润滑油COND凝结MANU手动（方式）CON连续的MCR最大连续出力COOR连续的MCS模拟量控制系统CORR校正，修正MEH小型汽轮机电液调节CRT显示器MFT主燃料失去保护CRH低温再热器MIN最小CSH包覆过热器MS主蒸汽CW循环水MW兆瓦D NO编号，第。

General DescriptionThe Zynq® UltraScale+™ MPSoC family is based on the Xilinx® UltraScale™ MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core or dual-core Arm® Cortex™-A53 and dual-core Arm Cortex-R5 based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces.Processing System (PS)Arm Cortex-A53 Based Application Processing Unit (APU)•Quad-core or dual-core•CPU frequency: Up to 1.5GHz•Extendable cache coherency•Armv8-A Architectureo64-bit or 32-bit operating modeso TrustZone securityo A64 instruction set in 64-bit mode,A32/T32 instruction set in 32-bit mode •NEON Advanced SIMD media-processing engine •Single/double precision Floating Point Unit (FPU)•CoreSight™and Embedded Trace Macrocell(ETM)•Accelerator Coherency Port (ACP)•AXI Coherency Extension (ACE)•Power island gating for each processor core •Timer and Interruptso Arm Generic timers supporto Two system level triple-timer counterso One watchdog timero One global system timer•Cacheso32KB Level1, 2-way set-associativeinstruction cache with parity (independent foreach CPU)o32KB Level1, 4-way set-associative data cache with ECC (independent for each CPU) o1MB 16-way set-associative Level2 cache with ECC (shared between the CPUs)Dual-core Arm Cortex-R5 Based Real-Time Processing Unit (RPU)•CPU frequency: Up to 600MHz•Armv7-R Architectureo A32/T32 instruction set•Single/double precision Floating Point Unit (FPU)•CoreSight™ and Embedded Trace Macrocell (ETM)•Lock-step or independent operation•Timer and Interrupts:o One watchdog timero Two triple-timer counters•Caches and Tightly Coupled Memories (TCMs) o32KB Level1, 4-way set-associativeinstruction and data cache with ECC(independent for each CPU)o128KB TCM with ECC (independent for each CPU) that can be combined to become 256KBin lockstep modeOn-Chip Memory•256KB on-chip RAM (OCM) in PS with ECC •Up to 36Mb on-chip RAM (UltraRAM) with ECC in PL•Up to 35Mb on-chip RAM (block RAM) with ECC in PL•Up to 11Mb on-chip RAM (distributed RAM) in PL 找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司Programmable Logic (PL)Configurable Logic Blocks (CLB)•Look-up tables (LUT)•Flip-flops•Cascadable adders36Kb Block RAM•True dual-port•Up to 72 bits wide•Configurable as dual 18Kb UltraRAM•288Kb dual-port•72 bits wide•Error checking and correctionDSP Blocks•27x18 signed multiply•48-bit adder/accumulator•27-bit pre-adder Programmable I/O Blocks •Supports LVCMOS, LVDS, and SSTL• 1.0V to 3.3V I/O•Programmable I/O delay and SerDes JTAG Boundary-Scan•IEEE Std 1149.1 Compatible Test Interface PCI Express•Supports Root complex and End Pointconfigurations•Supports up to Gen3 speeds•Up to five integrated blocks in select devices 100G Ethernet MAC/PCS•IEEE Std 802.3 compliant•CAUI-10 (10x 10.3125Gb/s) orCAUI-4 (4x 25.78125Gb/s)•RSFEC (IEEE Std 802.3bj) in CAUI-4 configuration •Up to four integrated blocks in select devices Interlaken•Interlaken spec 1.2 compliant•64/67 encoding•12 x 12.5Gb/s or 6 x 25Gb/s•Up to four integrated blocks in select devices Video Encoder/Decoder (VCU)•Available in EV devices•Accessible from either PS or PL •Simultaneous encode and decode•H.264 and H.265 supportSystem Monitor in PL•On-chip voltage and temperature sensing•10-bit 200KSPS ADC with up to 17 external inputsZynq UltraScale+ MPSoCsA comprehensive device family, Zynq UltraScale+ MPSoCs offer single-chip, all programmable,heterogeneous multiprocessors that provide designers with software, hardware, interconnect, power, security, and I/O programmability. The range of devices in the Zynq UltraScale+MPSoC family allows designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each Zynq UltraScale+MPSoC contains the same PS, the PL, Video hard blocks, and I/O resources vary between the devices.The Zynq UltraScale+ MPSoCs are able to serve a wide range of applications including:•Automotive: Driver assistance, driver information, and infotainment•Wireless Communications: Support for multiple spectral bands and smart antennas•Wired Communications: Multiple wired communications standards and context-aware network services •Data Centers: Software Defined Networks (SDN), data pre-processing, and analytics •Smarter Vision: Evolving video-processing algorithms, object detection, and analytics•Connected Control/M2M: Flexible/adaptable manufacturing, factory throughput, quality, and safetyThe UltraScale MPSoC architecture provides processor scalability from 32 to 64 bits with support for virtualization, the combination of soft and hard engines for real-time control, graphics/video processing, waveform and packet processing, next-generation interconnect and memory, advanced powermanagement, and technology enhancements that deliver multi-level security, safety, and reliability. Xilinx offers a large number of soft IP for the Zynq UltraScale+MPSoC family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. Xilinx’s Vivado® Design Suite, SDK™, and PetaLinux development environments enable rapid product development for software, hardware, and systems engineers. The Arm-based PS also brings a broad range of third-party tools and IP providers in combination with Xilinx's existing PL ecosystem.The Zynq UltraScale+MPSoC family delivers unprecedented processing, I/O, and memory bandwidth in the form of an optimized mix of heterogeneous processing engines embedded in a next-generation, high-performance, on-chip interconnect with appropriate on-chip memory subsystems. Theheterogeneous processing and programmable engines, which are optimized for different application tasks, enable the Zynq UltraScale+ MPSoCs to deliver the extensive performance and efficiency required to address next-generation smarter systems while retaining backwards compatibility with the original Zynq-7000 All Programmable SoC family. The UltraScale MPSoC architecture also incorporates multiple levels of security, increased safety, and advanced power management, which are critical requirements of next-generation smarter systems. Xilinx’s embedded UltraFast™ design methodology fully exploits theTable 7:Zynq UltraScale+ MPSoC Device FeaturesCG DevicesEG DevicesEV DevicesAPU Dual-core Arm Cortex-A53Quad-core Arm Cortex-A53Quad-core Arm Cortex-A53RPU Dual-core Arm Cortex-R5Dual-core Arm Cortex-R5Dual-core Arm Cortex-R5GPU –Mali-400MP2Mali-400MP2VCU––H.264/H.265ASIC-class capabilities afforded by the UltraScale MPSoC architecture while supporting rapid system development.The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating systems used with the Cortex-A53 processor are also available for theZynq UltraScale+MPSoC family. The PS and the PL are on separate power domains, enabling users to power down the PL for power management if required. The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.。

DATASHEETOverview Synopsys Platform Architect is a SystemC TLM standards-based graphical environment for capturing, configuring, simulating, and analyzing the system-level performance and power of multicore systems and next-generation SoC architectures.Platform Architect enables system designers to explore and optimize the hardware-software partitioning and the configuration of the SoC infrastructure, specifically the global interconnect and memory subsystem, to achieve the right system performance, power and cost.Its efficient turnaround time, powerful analysis views, and available IP models make Platform Architect the premier choice for system-level analysis and optimization of Arm AMBA®-based SoCs.Workload and Platform Authoring Architecture analysisand optimization forperformance andpowerPlatform ArchitectPlatform Architect is a production- proven solution used by leading systems OEMs and semiconductor companies worldwide.Highlights• Address the architecture challenges of Artificial Intelligence (AI)-enabled SoCs and multi-chip systems• Hardware-software partitioning and optimization of multicore systems• SoC interconnect and memory subsystem performance and power optimization• Efficient exploration using traffic generation and cycle-accurate TLM interconnect models• Unified view of activity, performance and power for root-cause analysis• Parameter sweeping and sensitivity analysis• Hardware-software validation using cycle-accurate TLM processor models• Compliant with IEEE 1666-2011 SystemC and TLM-2.0 as well as IEEE 1804 UPF 3.0 for system level power analysis Problem: Predicting System Performance and PowerPredicting the dynamic system performance and power of today’s multi-function, multi-application SoCs requires simulation.This impacts both system OEMs and semiconductor companies, and creates an opportunity for information sharing and collaboration within the supply chain.Challenges with Traditional MethodsDiscovering problems with system performance and power consumption late in the development cycle can be catastrophic to project schedules and product competitiveness, causing failure in the market. Accurate architecture analysis must be done earlier in the design cycle:• While spreadsheets are good for aggregating data, static spreadsheet calculations are not accurate enough to estimate performance and power and make design decisions. Dynamic simulation is needed.• Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition,the RTL may simply not be available• Risks include over-design, under-design, cost increases, schedule delays, and re-spinsSolution: Dynamic System-Level Architecture Simulation and AnalysisSynopsys Platform Architect provides system designers with the dynamic transaction-level simulation of performance and power, rapid turnaround time, and powerful system-level visibility they need to greatly improve the analysis and decision-making process. Address the Architecture Challenges of AI SoCs and Multi-Chip SystemsEasily map AI workloads to different SoC architectures to resolve AI power and performance design challenges with Platform Architect. Quickly address challenges of evolving algorithms, highly parallel compute and high memory requirements, with• A library of configurable AI operators for modeling Convolutional Neural Networks (CNNs)• Automated import of workloads from AI frameworks via prototxt and ONNX• An example NVDLA performance model to rapidly represent custom AI acceleratorsAI Operator library CNN workload modelFigure 2: AI Exploration Pack for performance analysis of AI accelerators Hardware-Software Partitioning and Optimization of Multicore Systems Platform Architect enables architects to create task-based workload models of the end-product application for early architecture analysis.Product trends requiring analysis Dynamic workloads generated by multiple initiators and software stacks Highest processing and memory bandwidth requirements by AI applicationsComplex interconnect topologies with hierarchical arbitration and advanced QoS capabilitiesComplex memory hierarchies with caches, on-chip SRAM, off-chip DDRResults with Platform Architect Quantitative analysis results on Key Performance Indicators like effective operations per second, frame-rate, etc. Fast turn-around time for architectural 'what-if' experimentsMeasurable improvement in product performance and powerReduced schedule risk vs. traditional RTL-based methodsFigure 3: SoC performance analysis challenges and the benefits of using system-levelmethods for performance and power analysis in Synopsys Platform ArchitectGeneric task models are easily configured to create a SystemC performance model of the application, called a task-graph.• Using a task-graph, the performance workload of parallel application tasks are mapped onto Virtual Processing Unit (VPU) task-driven traffic generators• Simulation and task analysis enables hardware/software partitioning to be optimized for best system performanceand power well before the application software is available• Task graphs also model the traffic generated by the initiators enabling performance optimization of the interconnect and memory subsystem• Platform Architect includes a Task Graph Generator (TGG) tool that generates application task graphs from sofware execution traces, like VDK software analysis, Linux ftrace, Android atrace, or QNX kernel trace. The TGG can be customized to generate task graphs from custom software trace formats.Interconnect and Memory Subsystem Performance Optimization Using Synthetic and Trace-Driven Traffic GenerationPlatform Architect focuses on architecture design challenges associated with the optimization and performance validation of the backbone SoC interconnect and global memory subsystem:• Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance and power before software is available• Simulation sweeping enables analysis data to be collected parametrically, exploring all traffic scenarios against a wide range of architecture configurations• Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable identification of performance and power bottlenecks, determine their root-cause, and examine the sensitivity that system performance may have to individual or combined parameter settingsThe result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support the latency, bandwidth, and power requirements of all relevant SoC components, under all operating conditions.Hardware/Software Performance Validation Using Processor Modelsand Critical SoftwareAfter exploration, the model of the candidate architecture can be refined to replace the task-based workload model with cycle- accurate processor models. This enables architects to validate the architecture candidate using the available performance critical software.Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure performanceand power, and to confirm goals are met.Complete IEEE 1666-2011 SystemC TLM-2.0 Standards-Based EnvironmentSynopsys Platform Architect is a SystemC-based environment fully compatible with the IEEE 1666-2011 SystemC and TLM-2.0 Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of abstraction, including:• Standards-based SystemC transaction-level models using IEEE 1666-2011 TLM-2.0 and Accellera Systems Initiative (ASI) TLM industry standards, and the open Synopsys SystemC Modeling Library (SCML) API library for highly reusable TLM-2.0 based peripheral modeling• Support for the IEEE 1804 UPF standard for the creation of system level power models. These can be connected to the TLM performance models to analyze the system-level power consumption based on dynamic activity.• M ixed SystemC/HDL co-simulation with Synopsys VCS and other third-party HDL simulation environments enabling reuse of RTL memory controllers and other IP components• A n Eclipse-based Integrated Development Environment for development and integration of SystemC based models, including a TLM Creation perspective for development and testing of SCML-based peripheral models and custom task models, as well as a TLM Debug perspective for SystemC aware source code debugging, tracing and analysisGetting Started with Available Architecture IP ModelsPlatform Architect supports the broadest commercially available portfolio of pre-instrumented SystemC TLM IP models for architecture exploration and validation.Task-based and Software-based Workload Modeling• G eneric Virtual Processing Units (VPUs) for application task-mapping with synthetic and trace-based traffic generation• Cycle-accurate SystemC-based TLM Arm Cycle Models, ARC nSim/nCam and xCAM models, Tensilica and MIPS processor families, and HDL co-simulation with user-provided RTL for other processor families• Accurate performance models of the DesignWare Embedded Vision (EV) subsystem, including nSim/nCAM model of the ARC Vector processor and the Fast Performance Model (FPM) of the Deep Neural Network (DNN) acceleratorInterconnect Models• Generic, fast, approximately-timed SystemC TLM models for AMBA-based coherent and non-coherent interconnect andnetwork-on-chip• Integration of architecture models for the Arteris FlexNoC™ Network on Chip (NoC) interconnect• C ycle-accurate SystemC TLM bus libraries for Arm CoreLink™ Network Interconnect and Synopsys DesignWare IPAXI interconnect• I ntegration of Arm Cycle Models for implementation accurate interconnect models of Arm coherent and non-coherent interconnects• F low for integration of 3rd-party interconnect models for full configurability in Platform Architect• G eneric configurable models of chip-to-chip protocols for PCIe and EthernetMemory Controller Models• Accurate SystemC TLM performance models of Synopsys DesignWare DDR memory controllers, including the DDR5/4 controller, the DDR5/4/4X controller and the enhanced Universal DDR Memory Controller (uMCTL2)• Generic approximately-timed SystemC TLM multi-port memory subsystem models for Arm AXI and CHI protocols• Cycle-accurate memory subsystem models through HDL co-simulation with user-provided, third-party, and Synopsys RTL memory controller IPProcessor Models• Cycle-accurate SystemC TLM processor support packages (PSPs) for Tensilica and MIPS processor families, and through HDL co-simulation with user-provided RTL for Arm processor familiesCoStart Enablement ServicesSynopsys CoStart is a packaged service that shortens the ramp-up cycle for architecture design methodologies so that users become productive in the shortest time.The Synopsys CoStart program contains an intense knowledge transfer, while assisting in architecture study project planning, use case traffic capture, architecture model creation, simulation, and analysis of results:• Tool, IP model, and methodology training that ensures end-user value at each step, accelerating results• Modeling services for the development and integration of custom interconnect and memory subsystem models, minimizing the modeling effort to get started and achieve initial value• Expert consulting and support to maximize ROI through exploration (not just checking)About Synopsys Virtual Prototyping SolutionsPlatform Architect is part of Synopsys’ comprehensive Virtual Prototyping solution offering that:• Provides the broadest portfolio of system-level IP models from a single supplier• Accelerates the creation and optimization of common SoC blocks• Facilitates SoC architecture exploration and optimization• Provides the most complete prototyping solutions to accelerate embedded software development and system validation• Includes comprehensive training materials and examples• Enables value throughout the semiconductor supply chainFor more information on Platform Architect visit: /platformarchitect©2021 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.。