IRF7220TRPBF;中文规格书,Datasheet资料

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7220)FEATURES• All-silicon, low-power CMOS technology• TTL/CMOS compatible inputs and outputs• Vapor phase, IR and wave solderable• Auto-insertable (DIP pkg.)• Low ground bounce noise• Leading- and trailing-edge accuracy • Delay range: 0.75ns through 7000ns • Delay tolerance: 2% or 0.5ns • Temperature stability: ±2% typical (-40C to 85C)• Vdd stability: ±1% typical (4.75V-5.25V)• Minimum input pulse width: 15% of total delay• 14-pin Gull-Wing available as drop-inreplacement for hybrid delay linesFUNCTIONAL DESCRIPTIONThe 3D7220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.The all-CMOS 3D7220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.PACKAGES1413121110981234567IN N/C O2O4O6O8GND VDDO1 O3 O5 O7 O9 O10 3D7220-xx DIP 3D7220G-xx Gull-Wing 12345678161514131211109IN N/C N/C O2O4O6O8GNDVDD N/C O1 O3 O5 O7 O9 O103D7220S-xx SOL1234567141312111098IN N/C O2O4O6O8GND VDD O1 O3 O5 O7 O9 O103D7220D-xx SOICPIN DESCRIPTIONSIN Delay Line Input O1 Tap 1 Output (10%) O2 Tap 2 Output (20%) O3 Tap 3 Output (30%) O4 Tap 4 Output (40%) O5 Tap 5 Output (50%) O6 Tap 6 Output (60%) O7 Tap 7 Output (70%) O8 Tap 8 Output (80%) O9 Tap 9 Output (90%) O10 Tap 10 Output (100%) VDD +5 Volts GND GroundTABLE 1: PART NUMBER SPECIFICATIONSTOLERANCES INPUT RESTRICTIONS DASH NUMBER TOTAL DELAY (ns) TAP-TAP DELAY (ns) Rec’d Max Frequency Absolute Max Frequency Rec’d Min Pulse Width Absolute Min Pulse Width-.75 6.75 ± 0.5* 0.75 ± 0.428.4 MHz 166.7 MHz 17.6 ns 3.00 ns -1 9.0 ± 0.5* 1.0 ± 0.523.8 MHz 166.7 MHz 21.0 ns 3.00 ns -1.5 13.5 ± 0.5* 1.5 ± 0.718.0 MHz 166.7 MHz 27.8 ns 3.00 ns -2 18.0 ± 0.5* 2.0 ± 0.814.5 MHz 166.7 MHz 34.5 ns 3.00 ns -2.5 22.5 ± 0.5* 2.5 ± 1.012.1 MHz 125.0 MHz 41.2 ns 4.00 ns -4 36.0 ± 0.7* 4.0 ± 1.38.33 MHz 133.3 MHz 60.0 ns 6.00 ns -5 50.0 ± 1.0 5.0 ± 1.56.67 MHz 66.7 MHz 75.0 ns7.50 ns -10 100.0 ± 2.0 10.0 ± 2.03.33 MHz 33.3 MHz 150 ns 15.0 ns -20 200.0 ±4.0 20.0 ± 4.01.67 MHz 16.7 MHz 300 ns 30.0 ns -50 500.0 ± 10 50.0 ± 100.67 MHz 6.67 MHz 750 ns 75.0 ns -100 1000 ± 20 100 ± 200.33 MHz 3.33 MHz 1500 ns 150 ns -7007000 ± 140 700 ± 1400.05 MHz 0.48 MHz 10500 ns 1050 ns* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0nsNOTE: Any dash number between .75 and 700 not shown is also available as standard.2005 Data Delay DevicesAPPLICATION NOTESOPERATIONAL DESCRIPTIONThe 3D7220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series.Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.INPUT SIGNAL CHARACTERISTICSThe Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.OPERATING FREQUENCYThe Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7220 must be tested at the user operating frequency.Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. Theprogrammed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.OPERATING PULSE WIDTHThe Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7220 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include aVDDO1 INO2 O3 O4Temp & VDD CompensationGNDFigure 1: 3D7220 Functional Diagram10% 10% 10% 10% 10%10%10%10%10%10%O5O6O7O8O9O10APPLICATION NOTES (CONT’D)custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.POWER SUPPLY AND TEMPERATURE CONSIDERATIONS The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7220 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature.The thermal coefficient is reduced to 250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±2% from the room-temperature delay settings and/or1.0ns, whichever is greater. The power supply coefficient is reduced, over the 4.75V-5.25V operating range, to ±1% of the delay settings at the nominal 5.0VDC power supply and/or1.0ns, whichever is greater. It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred.DEVICE SPECIFICATIONSTABLE 2: ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL MIN MAXUNITSNOTES DC Supply Voltage V DD -0.3 7.0 VInput Pin Voltage V IN -0.3V DD+0.3 VInput Pin Current I IN -1.0 1.0 mA25C Storage Temperature T STRG -55 150 CLead Temperature T LEAD300 C10secTABLE 3: DC ELECTRICAL CHARACTERISTICS(-40C to 85C, 4.75V to 5.25V)PARAMETER SYMBOLMINTYPMAXUNITSNOTES Static Supply Current* I DD 3.55.5mAHigh Level Input Voltage V IH 2.0 VLow Level Input Voltage V IL0.8 VHigh Level Input Current I IH 1.0µA V IH = V DDLow Level Input Current I IL 1.0µA V IL = 0VHigh Level Output Current I OH-35.0-4.0mAV DD = 4.75VV OH = 2.4VLow Level Output Current I OL 4.015.0 mAV DD = 4.75VV OL = 0.4V Output Rise & Fall Time T R & T F 2.0 2.5 ns C LD = 5 pf *I DD(Dynamic) = 10 * C LD * V DD * F Input Capacitance = 10 pf typical where: C LD = Average capacitance load/tap (pf) Output Load Capacitance (C LD) = 25 pf maxF = Input frequency (GHz)SILICON DELAY LINE AUTOMATED TESTINGTEST CONDITIONSINPUT: OUTPUT:Ambient Temperature: 25o C ± 3oC R load : 10K Ω ± 10%Supply Voltage (Vcc): 5.0V ± 0.1V C load : 5pf± 10% Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. 10K Ω470Ω5pfDevice Under Test Digital Scope Rise/Fall Time: 3.0 ns Max. (measuredbetween 0.6V and 2.4V ) Pulse Width: PW IN = 1.25 x Total DelayPeriod: PER IN = 2.5 x Total DelayNOTE: The above conditions are for test only and do not in any way restrict the operation of the device.Figure 2: Test SetupFigure 3: Timing Diagramt PLHt PHLPER INPW INt RISEt FALL0.6V0.6V1.5V 1.5V2.4V 2.4V 1.5V1.5VV IHV ILV OHV OLINPUT SIGNALOUTPUT SIGNAL。

Adapters convert older SCSI devices to work with newer SCSI installations Perfect for upgrading mixed installations
Description
Used to connect SCA (single connector attachment) Ultra Micro 80 drives to wide HD68 internal cabling. Tripp Lite's internal adapters convert SCSI devices with mixed installations. These adapters can save you the time and expense of buying new cables by simply adapting your existing ones to interface with the connector types found on many of the newer model SCSI installations. Tripp Lite warrants this product to be free from defects in materials and workmanship for life. System Requirements SCA drive needing to be attached to a wide HD68 SCSI ribbon Package Includes Internal SCSI Adapter HD68F to Ultra Micro 80F
Features
THale Waihona Puke e adapter will adapt a 80pin SCA device to a 68pin cable or connector All Tripp Lite SCSI products, regardless of the SCSI generation, meet the latest specifications of ANSI Tripp Lite offers a complete line of internal and external solutions for SCSI/RAID and fibre channel ranging from the very latest ultra 320 to legacy SCSI-1 and every combination in between Tripp Lite warrants this product to be free from defects in materials and workmanship for life

P OWER TRANSFORMER P C M O U N T : SPLIT PACK
FS20-120
Description:
The FS20-120 is a dual primary and dual secondary, split bobbin design which operates with either a parallel input of 115V or a series input of 230V. The output voltage will be either 20.0V with a center-tap under a 0.12A load with the secondaries wired in series, or 10.0V under a 0.24A load with the secondaries wired in parallel. The split bobbin design eliminates the need for costly electrostatic shielding.
1
As of April 7, 2008, UL standards 506 and 1585 will be migrated to UL 5085-2 and 5085-3, respectively. * Upon printing, this document is considered “uncontrolled”. Please contact Triad Magnetics’ website for the most current version. Web: Phone 951-277-0757 Fax 951-277-2757
Electrical Specifications (@25C)

AUIRG4PH50SFeaturesStandard: Optimized for minimum saturationvoltage and low operating frequencies (< 1kHz)Generation 4 IGBT design provides tighterparameter distribution and higher efficiencyIndustry standard TO-247AC packageLead-FreeAutomotive Qualified *IGBT's optimized for specified application conditionsBenefitsStandard Speed IGBT I NSULATED GATE BIPOLAR TRANSISTOR1PD -96301AUTOMOTIVE GRADEAbsolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.CGC04/13/10AUIRG4PH50SParameterMin.Typ.Max.Units Conditions Q gTotal Gate Charge (turn-on)—167251I C = 33A Q ge Gate - Emitter Charge (turn-on)—2538nC V CC = 400V See Fig. 8Q gc Gate - Collector Charge (turn-on)—5583V GE = 15V t d(on)Turn-On Delay Time —32—t r Rise Time—29—T J = 25°Ct d(off)Turn-Off Delay Time —8451268I C = 33A, V CC = 960V t f Fall Time—425638V GE = 15V, R G = 5.0ΩE on Turn-On Switching Loss — 1.80—Energy losses include "tail"E off Turn-Off Switching Loss —19.6—mJ See Fig. 9, 10, 14E ts Total Switching Loss —21.444t d(on)Turn-On Delay Time —32—T J = 150°C,t r Rise Time—30—I C = 33A, V CC = 960Vt d(off)Turn-Off Delay Time —1170—V GE = 15V, R G = 5.0Ωt f Fall Time—1000—Energy losses include "tail"E ts Total Switching Loss—37—mJ See Fig. 10,11,14L E Internal Emitter Inductance —13—nH Measured 5mm from package C ies Input Capacitance —3600—V GE = 0V C oes Output Capacitance—160—pF V CC = 30V See Fig. 7C res Reverse Transfer Capacitance—30—ƒ = 1.0MHzParameter Min.Typ.Max.Units ConditionsV (BR)CESCollector-to-Emitter Breakdown Voltage 1200——V V GE = 0V, I C = 250µA V (BR)ECS Emitter-to-Collector Breakdown Voltage 18——V V GE = 0V, I C = 1.0 A ∆V (BR)CES /∆T J Temperature Coeff. of Breakdown Voltage — 1.22—V/°C V GE = 0V, I C = 2.0 mA — 1.471.7 I C = 33A V GE = 15V V CE(ON)Collector-to-Emitter Saturation Voltage — 1.75— I C = 57A See Fig.2, 5— 1.55— I C = 33A , T J = 150°C V GE(th)Gate Threshold Voltage 3.0— 6.0V CE = V GE , I C = 250µA DV GE(th)/DT J Temperature Coeff. of Threshold Voltage —-11—mV/°C V CE = V GE , I C = 250µA g fe Forward Transconductance 2740—S V CE = 100V, I C = 33A ——250V GE = 0V, V CE = 1200V—— 2.0V GE = 0V, V CE = 10V, T J = 25°C ——1000V GE = 0V, V CE = 1200V, T J = 150°C I GES Gate-to-Emitter Leakage Current ——±100nA V GE = ±20VDynamic Electrical Characteristics @ T J = 25°C (unless otherwise specified)I CES Zero Gate Voltage Collector CurrentVµAStatic or Switching Electrical Characteristics @ T J = 25°C (unless otherwise specified)nsnsPulse width ≤ 80µs; duty factor ≤ 0.1%. Pulse width 5.0µs, single shot.Notes:Repetitive rating; V GE = 20V, pulse width limited bymax. junction temperature. ( See fig. 13b ) V CC = 80%(V CES ), V GE = 20V, L = 10µH, R G = 5.0Ω,(See fig. 13a)Repetitive rating; pulse width limited by maximumjunction temperature.AUIRG4PH50S 3Qualification standards can be found at International Rectifier s web site: http/// Exceptions to AEC-Q101 requirements are noted in the qualification report.Qualification Information †AUIRG4PH50SFig. 1 - Typical Load Current vs. Frequency(Load Current = I RMS of fundamental)02040600.1110f, Frequency (kHz)L o ad C u r re n t (A )AUIRG4PH50S 5Fig. 6 - Maximum Effective Transient Thermal Impedance, Junction-to-CaseFig. 5 - Typical Collector-to-Emitter Voltagevs. Junction TemperatureFig. 4 - Maximum Collector Current vs. CaseTemperatureAUIRG4PH50SFig. 7 - Typical Capacitance vs.Collector-to-Emitter Voltage Fig. 8 - Typical Gate Charge vs.Gate-to-Emitter VoltageResistance Junction TemperatureAUIRG4PH50S 7Collector-to-Emitter CurrentAUIRG4PH50S8* Note: Due to the 50V power supply, pulse width and inductor will increase to obtain rated Id.Fig. 13a - Clamped InductiveLoad Test CircuitFig. 13b - Pulsed CollectorCurrent Test CircuitFig. 14b - Switching LossWaveformsFig. 14a - SwitchingLoss Test Circuit* Driver same type as D.U.T., VC = ----V0 - VCCR L ICMVCC=Pulsed Collector CurrentTest CircuitTO-247AC Package Outline Dimensions are shown in milimeters (inches)XX or XXAUIRG4PH50S分销商库存信息: IRAUIRG4PH50S。