当前位置：文档之家 › FPGA可编程逻辑器件芯片XCVU125-H1FLVB1760E中文规格书

FPGA可编程逻辑器件芯片XCVU125-H1FLVB1760E中文规格书

  • 格式：pdf
  • 大小：494.39 KB
  • 文档页数：5

Summary of FeaturesRF Data Converter Subsystem OverviewMost Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or in most cases can be configured in pairs for real and imaginary I/Q data. See RF-ADCs and RF-DACs sections.Soft Decision Forward Error Correction (SD-FEC) OverviewSome Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.Processing System OverviewZynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU) with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm Mali™-400 MP2 graphics processing unit (GPU). See Table 2.To support the processors' functionality, a number of peripherals with dedicated functions are included in the PS. For interfacing to external memories for data or configuration storage, the PS includes amulti-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller and a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1 (L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memory subsystem. Each has access to a 256KB on-chip memory.For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs oftransceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can interface to the high-speed peripheral blocks that support PCIe at 5.0GT/s (Gen 2) as a root complex or Endpoint in x1, x2, or x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and up to two lanes of Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can also interface to components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).Table 2:Zynq UltraScale+ MPSoC and RFSoC Device FeaturesMPSoCRFSoC CG DevicesEG DevicesEV DevicesDR DevicesAPU Dual-core Arm Cortex-A53Quad-core Arm Cortex-A53Quad-core Arm Cortex-A53Quad-core Arm Cortex-A53RPU Dual-core Arm Cortex-R5FDual-core Arm Cortex-R5FDual-core Arm Cortex-R5FDual-core Arm Cortex-R5FGPU –Mali-400MP2Mali-400MP2–VCU––H.264/H.265–External MemoryThe PS can interface to many types of external memories through dedicated memory controllers. The dynamic memory controller supports DDR3, DDR3L, DDR4, LPDDR3, and LPDDR4 memories. Themulti-protocol DDR memory controller can be configured to access a 2GB address space in 32-bit addressing mode and up to 32GB in 64-bit addressing mode using a single or dual rank configuration of 8-bit, 16-bit, or 32-bit DRAM memories. Both 32-bit and 64-bit bus access modes are protected by ECC using extra bits.The SD/eMMC controller supports 1 and 4 bit data interfaces at low, default, high-speed, andultra-high-speed (UHS) clock rates. This controller also supports 1-, 4-, or 8-bit-wide eMMC interfaces that are compliant to the eMMC 4.51 specification. eMMC is one of the primary boot and configuration modes for Zynq UltraScale+ MPSoCs and RFSoCs and supports boot from managed NAND devices. The controller has a built-in DMA for enhanced performance.The Quad-SPI controller is one of the primary boot and configuration devices. It supports 4-byte and3-byte addressing modes. In both addressing modes, single, dual-stacked, and dual-parallel configurations are supported. Single mode supports a quad serial NOR flash memory, while in double stacked and double parallel modes, it supports two quad serial NOR flash memories.The NAND controller is based on ONFI3.1 specification. It has an 8-pin interface and provides 200Mb/s of bandwidth in synchronous mode. It supports 24 bits of ECC thus enabling support for SLC NAND memories. It has two chip-selects to support deeper memory and a built-in DMA for enhanced performance.General ConnectivityThere are many peripherals in the PS for connecting to external devices over industry standard protocols, including CAN2.0B, USB, Ethernet, I2C, and UART. Many of the peripherals support clock gating and power gating modes to reduce dynamic and static power consumption.USB 3.0/2.0The pair of USB controllers can be configured as host, device, or On-The-Go (OTG). The core is compliant to USB 3.0 specification and supports super, high, full, and low speed modes in all configurations. In host mode, the USB controller is compliant with the Intel XHCI specification. In device mode, it supports up to 12 end points. While operating in USB3.0 mode, the controller uses the serial transceiver and operates up to 5.0Gb/s. In USB2.0 mode, the Universal Low Peripheral Interface (ULPI) is used to connect the controller to an external PHY operating up to 480Mb/s. The ULPI is also connected in USB3.0 mode to support high-speed operations.Ethernet MACThe four tri-speed ethernet MACs support 10Mb/s, 100Mb/s, and 1Gb/s operations. The MACs support jumbo frames and time stamping through the interfaces based on IEEE Std 1588v2. The ethernet MACs can be connected through the serial transceivers (SGMII), the MIO (RGMII), or through EMIO (GMII). The GMII interface can be converted to a different interface within the PL.Input/OutputAll UltraScale devices, whether FPGA, MPSoC, or RFSoCs, have I/O pins for communicating to external components. In addition, in the PS, there are another 78 I/Os that the I/O peripherals use to communicate to external components, referred to as multiplexed I/O (MIO). If more than 78 pins are required by the I/O peripherals, the I/O pins in the PL can be used to extend the MPSoC or RFSoC interfacing capability, referred to as extended MIO (EMIO).The number of I/O pins in UltraScale FPGAs and in the programmable logic of Zynq UltraScale+ MPSoCs and RFSoCs varies depending on device and package. Each I/O is configurable and can comply with a large number of I/O standards. The I/Os are classed as high-range (HR), high-performance (HP), or high-density (HD). The HR I/Os offer the widest range of voltage support, from 1.2V to 3.3V. The HP I/Os are optimized for highest performance operation, from 1.0V to 1.8V. The HD I/Os are reduced-feature I/Os organized in banks of 24, providing voltage support from 1.2V to 3.3V.The static memory interface controller (NAND, eMMC, or Quad-SPI) is configured using default settings. To improve device configuration speed, these settings can be modified by information provided in the boot image header. The ROM boot image is not user readable or executable after boot.Configuring FPGAsThe SPI (serial NOR) interface (x1, x2, x4, and dual x4 modes) and the BPI (parallel NOR) interface (x8 and x16 modes) are two common methods used for configuring the FPGA. Users can directly connect an SPI or BPI flash to the FPGA, and the FPGA's internal configuration logic reads the bitstream out of the flash and configures itself, eliminating the need for an external controller. The FPGA automatically detects the bus width on the fly, eliminating the need for any external controls or switches. Bus widths supported are x1, x2, x4, and dual x4 for SPI, and x8 and x16 for BPI. The larger bus widths increase configuration speed and reduce the amount of time it takes for the FPGA to start up after power-on.In master mode, the FPGA can drive the configuration clock from an internally generated clock, or for higher speed configuration, the FPGA can use an external configuration clock source. This allowshigh-speed configuration with the ease of use characteristic of master mode. Slave modes up to 32bits wide that are especially useful for processor-driven configuration are also supported by the FPGA. In addition, the new media configuration access port (MCAP) provides a direct connection between the integrated block for PCIe and the configuration logic to simplify configuration over PCIe.SEU detection and mitigation (SEM) IP, RSA authentication, post-configuration CRC, and Security Monitor (SecMon) IP are not supported in the KU025 FPGA.。

合集下载

FPGA可编程逻辑器件芯片XCKU085-2FLVA1517E中文规格书

FPGA可编程逻辑器件芯片XCKU085-2FLVA1517E中文规格书

Board InstallationIntroductionThis appendix provides the information required to install, program, debug, and deploy a Xilinx® accelerator board to execute applications created with the SDx® environment. The SDx environment executes in hardware using one of the FPGA boards listed in the application.Installing a BoardThe KCU1500 card is a high-performance reconfigurable computing card for data center applications and includes these features:•XCKU1500-2FLVB2104E FPGA •Four 4GB DDR4 banks (16GB total)The following sections describe how to install a board.Step 1: Set Up the Card and Computer1.Make sure the host computer is completely turned off.2.Install the FPGA board in an open PCIe® slot on the host computer.3.Turn on the host computer.Note:Follow the host computer manufacturer recommendations to ensure proper mountingand adequate cooling.找FPGA 和CPLD 可编程逻辑器件，上赛灵思半导体（深圳）有限公司Step 2: Prepare Board Installation FilesThe SDx environment provides the xbinst utility, which generates firmware and driver files for the target board plugged into the deployment computer.1.Run the following commands to prepare files for the target board installation.See the SDx Command and Utility Reference Guide (UG1279) [Ref6] for more details on the xbinst utility. Depending on the target location, some commands must be run with root or sudo privilege. Otherwise, access permissions must be changed to enable read access for all users on that system.e the following commands to create the deployment area inside/opt/dsa/:$ mkdir /opt/dsa$ mkdir /opt/dsa/xilinx_vcu1525_dynamic_5_1$ cd /opt/dsa/xilinx_vcu1525_dynamic_5_1Note:To install and deploy the KCU1500 files, use xilinx_kcu1500_dynamic_5_0 in step 2 and 3.3.Execute xbinst to install the files needed for the deployment machine. Output similarto the following is displayed:$ xbinst --platform xilinx_vcu1525_dynamic_5_1 -d .****** xbinst v2018.2 (64-bit)**** SW Build 2254440 on Sun Jun 10 18:05:35 MDT 2018** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.Attempting to get a license: ap_openclFeature available: ap_openclINFO: [XBINST 60-895] Target platform:/opt/Xilinx/SDx/2018.2/platforms/xilinx_vcu1525_dynamic_5_1/xilinx_vcu1525_dynamic_ 5_1.xpfmINFO: [XBINST 60-267] Packaging for PCIe...INFO: [XBINST 60-1032] Extracting DSA to./.Xil/xbinst-1273/xilinx_vcu1525_dynamic_5_1INFO: Adding section [FIRMWARE (3)] using: 'mgmt' (23192 Bytes)INFO: Adding section [SCHED_FIRMWARE (5)] using: 'sched' (9748 Bytes)Successfully completed 'xclbincat'INFO: [XBINST 60-268] Packaging for PLETEINFO: [XBINST 60-667] xbinst has successfully created a board installation directory at /opt/dsa/xilinx_vcu1525_dynamic_5_1.The files are installed in this location:/opt/dsa/xilinx_vcu1525_dynamic_5_1/xbinst:Make a note of the deployment location area because it is required at a later stage.This section refers to this location as the <xbinst-area> or as the deploymentdirectory.4.Install the drivers as described in Step 3: Install Board Drivers.Capabilities: <access denied>Kernel driver in use: xoclKernel modules: xocl03:00.1 Serial controller: Xilinx Corporation Device 6a8f (prog-if 01 [16450]) Subsystem: Xilinx Corporation Device 4351Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-Region 0: Memory at f4000000 (32-bit, non-prefetchable) [size=32M]Region 2: Memory at f8020000 (32-bit, non-prefetchable) [size=128K]Region 4: Memory at f8000000 (32-bit, non-prefetchable) [size=128K]Capabilities: <access denied>Kernel driver in use: xclmgmtKernel modules: xclmgmt。

FPGA可编程逻辑器件芯片5CGXFC5F6M11I7N中文规格书

FPGA可编程逻辑器件芯片5CGXFC5F6M11I7N中文规格书

2.TriMatrix EmbeddedMemory Blocks in Stratix IIand Stratix II GX DevicesIntroduction Stratix®II and Stratix II GX devices feature the TriMatrix™ memorystructure, consisting of three sizes of embedded RAM blocks thatefficiently address the memory needs of FPGA designs.TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and512-Kbit M-RAM blocks, which are each configurable to support manyfeatures. TriMatrix memory provides up to 9megabits of RAM at up to550 MHz operation, and up to 16 terabits per second of total memorybandwidth per device. This chapter describes TriMatrix memory blocks,modes, and features.TriMatrix Memory Overview The TriMatrix architecture provides complex memory functions for different applications in FPGA designs. For example, M512 blocks are used for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical; M4K blocks are ideal for applications requiring medium-sized memory, such as asynchronous transfer mode (ATM) cell processing; and M-RAM blocks are suitable for large buffering applications, such as internet protocol (IP) packet buffering and system cache.The TriMatrix memory blocks support various memory configurations, including single-port, simple dual-port, true dual-port (also known as bidirectional dual-port), shift register, and read-only memory (ROM) modes. The TriMatrix memory architecture also includes advanced features and capabilities, such as parity-bit support, byte enable support, pack mode support, address clock enable support, mixed port width support, and mixed clock mode support.When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.SII52002-4.5DC & Switching CharacteristicsTable5–97.DQS Phase Jitter Specifications for DLL-Delayed Clock(tDQS PHASE_JITTER) Note(1)Number of DQS DelayDQS Phase Jitter UnitBuffer Stages (2)130ps260ps390ps4120psNotes to Table5–97:(1)Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is causedby DLL tracking).(2)Delay stages used for requested DQS phase shift are reported in your project’sCompilation Report in the Quartus II software.Table5–98.DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR)(1)Number of DQS Delay Buffer Stages (2)–3 Speed Grade–4 Speed Grade–5 Speed Grade Unit 1253035ps2506070ps37590105ps4100120140ps Notes to Table5–98:(1)This error specification is the absolute maximum and minimum error. For example, skew on three delay bufferstages in a C3 speed grade is 75ps or ± 37.5ps.(2)Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in theQuartus II software.Table5–99.DQS Bus Clock Skew Adder Specifications(tDQS_CLOCK_SKEW_ADDER)Mode DQS Clock Skew Adder Unit×4 DQ per DQS40ps×9 DQ per DQS70ps×18 DQ per DQS75ps×36 DQ per DQS95psNote to Table5–99:(1)This skew specification is the absolute maximum and minimum skew. Forexample, skew on a ×4 DQ group is 40 ps or ±20ps.Stratix II Device Handbook, Volume 1TriMatrix MemoryFigure2–22.M4K RAM Block LAB Row InterfaceM-RAM BlockThe largest TriMatrix memory block, the M-RAM block, is useful forapplications where a large volume of data must be stored on-chip. Eachblock contains 589,824 RAM bits (including parity bits). The M-RAMblock can be configured in the following modes:■True dual-port RAM■Simple dual-port RAM■Single-port RAM■FIFOYou cannot use an initialization file to initialize the contents of an M-RAMblock. All M-RAM block contents power up to an undefined value. Onlysynchronous operation is supported in the M-RAM block, so all inputsare registered. Output registers can be bypassed.Stratix II Device Handbook, Volume 1。

FPGA可编程逻辑器件芯片XCZU11EG-L2FFVB1517E中文规格书

FPGA可编程逻辑器件芯片XCZU11EG-L2FFVB1517E中文规格书

XAPP377 (v1.0) May 8, 2002
Using the CoolRunner-II SMBus/I2C Port Expander Design
Start Condition
Both SCL and SDA remain high when the interface is inactive. The master signals the start condition by transitioning SDA from high to low while SCL is high (Figure 2). Once a start condition is recognized by the CPLD, an internal ‘start’ pulse is generated, and the state machine will begin.
Figure 2: Start Condition Initiated
Acknowledge
The acknowledge bit is sent every 9th bit, indicating receipt of each data byte. Each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge pulse. This means that when the master is transmitting to the CPLD, the CPLD generates the acknowledge bit. When the CPLD is transmitting to the master, the master generates the acknowledge bit.
FPGA可编程逻辑器件芯片XC6VLX760-1FFG1760I中文规格书

FPGA可编程逻辑器件芯片XC6VLX760-1FFG1760I中文规格书

SummaryThis chapter covers the following topics:•Introduction•Device/Package Combinations and Maximum I/Os•Pin DefinitionsIntroductionThis section describes the pinouts for Virtex®-5 devices in the 1.00mm pitch flip-chip fine-pitch BGA packages.Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages thatare optimally designed for improved signal integrity and jitter. Package inductance isminimized as a result of optimal placement and even distribution as well as an increasednumber of Power and GND pins.All of the devices supported in a particular package are pinout compatible and are listed inthe same table (one table per package). Pins that are not available for the smaller devicesare listed in the “No Connects” column of each table.For Virtex-5Q devices, the EF package is offered. The only difference between an EF and anFF package is that the discrete substrate capacitors on the EF package are coated withepoxy. The coating is comprised of an undercoat epoxy that is dispensed under thecapacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All otherpackage construction characteristics of the EF matches that of the FF package. The EFpackage changes are noted in Chapter4, “Mechanical Drawings.”Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/Ostandards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG,configuration, and power/ground pins, are listed at the end of each table. Table1-7provides definitions for all pin types.For information on package electrical characteristics and how the characteristics aremeasured, refer to UG112: Device Package User Guide found on the Xilinx website.For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updatesto this document.Virtex-5 FPGA Packaging and Pinout SpecificationChapter 2:Pinout TablesTable 2-1:FF323 Package—LX20T and LX30T (Continued)Bank Pin Description Pin Number No Connect (NC)13IO_L7N_SM2N_13L1713IO_L8P_CC_SM1P_13N1213IO_L8N_CC_SM1N_13(2)M1113IO_L9P_CC_SM0P_13K1613IO_L9N_CC_SM0N_13(2)L1613IO_L10P_CC_13N1813IO_L10N_CC_13(2)M1813IO_L11P_CC_13M1413IO_L11N_CC_13(2)L1313IO_L12P_VRN_13P1813IO_L12N_VRP_13N1713IO_L13P_13L1413IO_L13N_13K1413IO_L14P_13R1713IO_L14N_VREF_13P1713IO_L15P_13N1313IO_L15N_13M1313IO_L16P_13R1513IO_L16N_13R1613IO_L17P_13P1413IO_L17N_13P1513IO_L18P_13N1613IO_L18N_13M1613IO_L19P_13N1513IO_L19N_13M1517IO_L4P_17M1017IO_L4N_VREF_17N1117IO_L5P_17T1717IO_L5N_17T1617IO_L6P_17T1217IO_L6N_17R1217IO_L7P_17T1817IO_L7N_17U18Virtex-5 FPGA Packaging and Pinout SpecificationFF1760 Package—LX110, LX155, LX220, and LX330Table 2-10:FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)Bank Pin Description Pin Number No Connect (NC)27IO_L7N_27 A35LX110, LX155, LX22027IO_L8P_CC_27 D35LX110, LX155, LX22027IO_L8N_CC_27(2)D36LX110, LX155, LX22027IO_L9P_CC_27 C36LX110, LX155, LX22027IO_L9N_CC_27(2)C35LX110, LX155, LX22027IO_L10P_CC_27 A37LX110, LX155, LX22027IO_L10N_CC_27(2)A36LX110, LX155, LX22027IO_L11P_CC_27 B37LX110, LX155, LX22027IO_L11N_CC_27(2)B36LX110, LX155, LX22027IO_L12P_VRN_27 C38LX110, LX155, LX22027IO_L12N_VRP_27 D38LX110, LX155, LX22027IO_L13P_27 C39LX110, LX155, LX22027IO_L13N_27 C40LX110, LX155, LX22027IO_L14P_27 B39LX110, LX155, LX22027IO_L14N_VREF_27 B38LX110, LX155, LX22027IO_L15P_27 A39LX110, LX155, LX22027IO_L15N_27 A40LX110, LX155, LX22027IO_L16P_27 A41LX110, LX155, LX22027IO_L16N_27 B41LX110, LX155, LX22027IO_L17P_27 B42LX110, LX155, LX22027IO_L17N_27 C41LX110, LX155, LX22027IO_L18P_27 D40LX110, LX155, LX22027IO_L18N_27 D41LX110, LX155, LX22027IO_L19P_27 E42LX110, LX155, LX22027IO_L19N_27 D42LX110, LX155, LX22028IO_L0P_28 C13LX110, LX155, LX22028IO_L0N_28 D13LX110, LX155, LX22028IO_L1P_28 B11LX110, LX155, LX22028IO_L1N_28 C11LX110, LX155, LX22028IO_L2P_28 B12LX110, LX155, LX22028IO_L2N_28 A12LX110, LX155, LX22028IO_L3P_28 D11LX110, LX155, LX22028IO_L3N_28 D12LX110, LX155, LX220 Virtex-5 FPGA Packaging and Pinout SpecificationVirtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)August 9, 2018Chapter 2:Pinout TablesFF1760 Package—LX110, LX155, LX220, and LX330Table 2-10:FF1760 Package—LX110, LX155, LX220, and LX330 (Continued)Bank Pin Description Pin Number No Connect (NC)30IO_L13N_30 AW10LX110, LX155, LX22030IO_L14P_30 BB9LX110, LX155, LX22030IO_L14N_VREF_30 BA10LX110, LX155, LX22030IO_L15P_30 AY8LX110, LX155, LX22030IO_L15N_30 AY9LX110, LX155, LX22030IO_L16P_30 AW11LX110, LX155, LX22030IO_L16N_30 AW12LX110, LX155, LX22030IO_L17P_30 BA12LX110, LX155, LX22030IO_L17N_30 BB12LX110, LX155, LX22030IO_L18P_30 BB11LX110, LX155, LX22030IO_L18N_30 BA11LX110, LX155, LX22030IO_L19P_30 AY13LX110, LX155, LX22030IO_L19N_30 AY12LX110, LX155, LX22031IO_L0P_31 E14LX110, LX155, LX22031IO_L0N_31 D15LX110, LX155, LX22031IO_L1P_31 E15LX110, LX155, LX22031IO_L1N_31 F14LX110, LX155, LX22031IO_L2P_31 D16LX110, LX155, LX22031IO_L2N_31 D17LX110, LX155, LX22031IO_L3P_31 F16LX110, LX155, LX22031IO_L3N_31 F15LX110, LX155, LX22031IO_L4P_31 F17LX110, LX155, LX22031IO_L4N_VREF_31 E17LX110, LX155, LX22031IO_L5P_31 E20LX110, LX155, LX22031IO_L5N_31 F20LX110, LX155, LX22031IO_L6P_31 D18LX110, LX155, LX22031IO_L6N_31 E18LX110, LX155, LX22031IO_L7P_31 E19LX110, LX155, LX22031IO_L7N_31 F19LX110, LX155, LX22031IO_L8P_CC_31 D22LX110, LX155, LX22031IO_L8N_CC_31(2)D23LX110, LX155, LX22031IO_L9P_CC_31 D21LX110, LX155, LX22031IO_L9N_CC_31(2)D20LX110, LX155, LX220 Virtex-5 FPGA Packaging and Pinout Specification。