LF347.数据手册

FM24C64数据⼿册This product conforms to specifications per the terms of the RamtronRamtron International Corporationstandard warranty. Production processing does not necessarily in- 1850 Ramtron Drive, Colorado Springs, CO 80921 clude testing of all parameters. (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058Low Power Operation A Active Current (100 kHz) A Standby Current DescriptionThe FM24C64 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.The FM24C64 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately. TheFM24C64 is capable of supporting 1012 read/write cycles, or a million times more write cycles than EEPROM.These capabilities make the FM24C64 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writes with less overhead for the system.The FM24C64 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C64 is available in an industry standard 8-pin SOIC package using a two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin ConfigurationA0A1A2VSSVDD WP SCL SDAPin Names FunctionA0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage 5VOrdering InformationFM24C64-S 8-pin SOICFigure 3. Data Transfer ProtocolStop ConditionA Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition.Start ConditionA Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM24C64 for a new operation.If during operation the power supply drops below the specified V DD minimum, the system should issue a Start condition prior to performing another operation Data/Address TransferAll data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high.AcknowledgeThe Acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a No-Acknowledge and the operation is aborted. The receiver could fail to acknowledge for two distinct reasons. First, if a byte transfer fails, the No-Acknowledge ends the current operation so that the device can be addressed again. This allows the last byte to be recovered in the event of a communication error. Second and most common, the receiver does not acknowledge the data to deliberately end an operation. For example, during a read operation, the FM24C64 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24C64 to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command.Slave AddressThe first byte that the FM24C64 expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the Slave ID (device type), the device select address bits, and a bit that specifies if the transaction is a read or a write. Bits 7-4 define the device type and must be set to 1010b for the FM24C64. These bits allow other types of function types to reside on the 2-wire bus within an identical address range. Bits 3-1 are the select bits which are equivalent to chip select bits. They must match the corresponding value on the external address pins to select the device. Up to eightFM24C64s can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit. A 1 indicates a read operation, and a 0 indicates a write.1010A2A1A0R/W Slave ID Device Select7654321Figure 4. Slave AddressAddressing OverviewAfter the FM24C64 (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB (upper byte). Since the device uses only 13 address bits, the value of the upper three bits are don’t care. Following the MSB is the LSB (lower byte) with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below.After transmission of each data byte and just prior to the acknowledge, the FM24C64 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address (1FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation.Data TransferAfter the address information has been transmitted, data transfer between the bus master and the FM24C64 can begin. For aread operation, the FM24C64 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C64 will transfer the next sequential byte. If the Acknowledge is not sent, the FM24C64 will end the read operation. For a write operation, the FM24C64 will accept 8 data bits from the master and then send an Acknowledge. All data transfer occurs MSB (most significant bit) first. Memory OperationThe FM24C64 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C64 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below.Write OperationAll writes begin with a device address, then a memory address. The bus master indicates a write operation by setting the LSB of the device address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 1FFFh to 0000h.Unlike other nonvolatile memory technologies, there is no write delay with FRAM. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition.Internally, the actual memory write occurs after the 8th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8th data bit. The FM24C64 uses no page buffering.Portions of the memory array can be write protected using the WP pin. Pulling the WP pin high (V DD ) will write-protect addresses in the upper quadrant from 1800h to 1FFFh. The FM24C64 will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Pulling WP low (V SS ) will deactivate this feature. WP should not be left floating.Figures 5 and 6 illustrate both a single-byte write and multiple-byte write.。

GigaDevice Semiconductor Inc.GD32F107xxARM® Cortex™-M3 32-bit MCUDatasheetTable of ContentsList of Figures (3)List of Tables (4)1 General description (5)2 Device overview (6)2.1 Device information (6)2.2 Block diagram (8)2.3 Pinouts and pin assignment (9)2.4 Memory map (12)2.5 Clock tree (13)2.6 Pin definitions (14)3 Functional description (22)3.1 ARM® Cortex™-M3 core (22)3.2 On-chip memory (22)3.3 Clock, reset and supply management (23)3.4 Boot modes (23)3.5 Power saving modes (24)3.6 Analog to digital converter (ADC) (24)3.7 Digital to analog converter (DAC) (25)3.8 DMA (25)3.9 General-purpose inputs/outputs (GPIOs) (25)3.10 Timers and PWM generation (26)3.11 Real time clock (RTC) (27)3.12 Inter-integrated circuit (I2C) (27)3.13 Serial peripheral interface (SPI) (28)3.14 Universal synchronous asynchronous receiver transmitter (USART) (28)3.15 Inter-IC sound (I2S) (28)3.16 Universal serial bus on-the-go full-speed (USB OTG FS) (29)3.17 Controller area network (CAN) (29)3.18 Ethernet MAC interface (29)3.19 External memory controller (EXMC) (30)3.20 Debug mode (30)3.21 Package and operation temperature (30)4 Electrical characteristics (31)4.1 Absolute maximum ratings (31)4.2 Recommended DC characteristics (31)4.3 Power consumption (32)4.4 EMC characteristics (33)4.5 Power supply supervisor characteristics (33)4.6 Electrical sensitivity (34)4.7 External clock characteristics (34)4.8 Internal clock characteristics (35)4.9 PLL characteristics (36)4.10Memory characteristics (36)4.11 GPIO characteristics (36)4.12 ADC characteristics (37)4.13 DAC characteristics (37)4.14 I2C characteristics (37)4.15SPI characteristics (38)5 Package information (39)6 Ordering Information (41)7 Revision History (42)List of FiguresFigure 1. GD32F107xx block diagram (8)Figure 2. GD32F107Zx LQFP144 pinouts (9)Figure 3. GD32F107Vx LQFP100 pinouts (10)Figure 4. GD32F107Rx LQFP64 pinouts (11)Figure 6. GD32F107xx memory map (12)Figure 7. GD32F107xx clock tree (13)Figure 8. LQFP package outline (39)List of TablesTable 1. GD32F107xx devices features and peripheral list (6)Table 2. GD32F107xx pin definitions (14)Table 3. Absolute maximum ratings (31)Table 4. DC operating conditions (31)Table 5. Power consumption characteristics (32)Table 6. EMS characteristics (33)Table 7. EMI characteristics (33)Table 8.Power supply supervisor characteristics (33)Table 9. ESD characteristics (34)Table 10. Static latch-up characteristics (34)Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics (34)Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics (35)Table 13. High speed internal clock (HSI) characteristics (35)Table 14. Low speed internal clock (LSI) characteristics (35)Table 15. PLL characteristics (36)Table 16. Flash memory characteristics (36)Table 17. I/O port characteristics (36)Table 18. ADC characteristics (37)Table 19. DAC characteristics (37)Table 20. I2C characteristics (37)Table 21. SPI characteristics (38)Table 22. LQFP package dimensions (40)Table 23. Part ordering code for GD32F107xx devices (41)Table 24. Revision history (42)1 General descriptionThe GD32F107xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bitgeneral-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhancedconnectivity performance and best ratio in terms of processing power, reduced powerconsumption and peripheral set. The Cortex™-M3 is a next generation processor core whichis tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer andadvanced debug support.The GD32F107xx device incorporates the ARM®Cortex™-M3 32-bit processor coreoperating at 108 MHz frequency with Flash accesses zero wait states to obtain maximumefficiency. It provides up to 1 MB on-chip Flash memory and 96 KB SRAM memory. Anextensive range of enhanced I/Os and peripherals connected to two APB buses. Thedevices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standardand advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, twoUARTs, two I2Ss, two CANs, an USB OTG FS and an Ethernet MAC.The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °Ctemperature range. Several power saving modes provide the flexibility for maximumoptimization between wakeup latency and power consumption, an especially importantconsideration in low power applications.The above features make the GD32F107xx devices suitable for a wide range ofinterconnection applications, especially in areas such as industrial control, motor drives,power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS,LED display and so on.2 Device overview 2.1 Device information2.2 Block diagramFigure 1. GD32F107xx block diagram2.3 Pinouts and pin assignmentFigure 2. GD32F107Zx LQFP144 pinoutsPF2PF3PF7PC6PG8PG7PG6PG5PG4PG3PD15PD14PA3V SS_4V DD_4PA4PA5PA6PA7PC4PC5V DD_3V SS_3PE1PE0PB9PB8BOOT0PB7PB6PB5PB4PB3PF13PE7V DD_2V SS_2NC PA13PA12PA11PA10PA9PA8PC9PC8PC7PG14PG13PG12PG10PG9PD7PD6V BATPC14-OSC32_IN PC15-OSC32_OUTPF4PF0PF1OSC_IN V SS_10PF5V V PF6PG15V SSA V V V PD13PD12PD11PD10PD9PD8PB15PB14PB13PB12PD5PD4PD3PD2PD1PD0PC12PC10PA15PA14PF8PF9PF10V SS_6V DD_6PE8V SS_7V DD_7V SS_1V DD_1V DD_8V SS_8PG2V DD_9V SS_9V DD_10V SS_11V DD_11Figure 3. GD32F107Vx LQFP100 pinoutsOSC_IN OSC_OUTV SSA V REF-PA1PC6PD15PD14PD13PD12PD11PD10PD9PD8PB15PB14PB13PA3SS_4V DD_4PA4PA5PA6PA7PC4PC5PB0PB1PB2V DD_3V SS_3PE1PE0PB9PB8BOOT0PB7PB6PB5PB4PB3PE7PE8PE9PE10PE11PB11V SS_1V DD_2V SS_2NC PA13PA12PA11PA10PA9PA8PC9PC8PC7PD5PD4PD3PD2PD1PD0V BATPC13-TAMPER-RTCPC14-OSC32_IN PC15-OSC32_OUTNRST V SS_5V DD_5PA0-WKUPPE2PA2PB12V DD_1PE3PE4PE5PE6PC0PC1PC2PC3V V DDAPD6PD7Figure 4. GD32F107Rx LQFP64 pinoutsV SSA PA1PA12PA11PA10PA9PA8PC9PC8PC7PC6PB15PB14PB13PA3V SS_4V DD_4PA4PA5PA6PA7PC4PC5PB0PB1PB2V DD_3V SS_3PB8PB9PB7PB6BOOT0PB5PB4PB3PD2PC12PB10PB11V SS_1V DD_2V SS_2PA13PA15PA14V BATPC13-TAMPER-RTCPC14-OSC32_IN PC15-OSC32_OUTNRST PA0-WKUPPA2PB12V DD_1PC0PC1PC2PC3V DDAPC10PC11PD1 OSC_OUTPD0-OSC_IN2.4 Memory mapFigure 5. GD32F107xx memory map76543210x 4000 00000x 4000 04000x 4000 08000x 4000 0C000x 4000 10000x 4000 14000x 4000 18000x 4000 1C000x 4000 20000x 4000 24000x 4000 28000x 4000 2C000x 4000 30000x 4000 34000x 4000 38000x 4000 3C000x 4000 40000x 4000 44000x 4000 48000x 4000 4C000x 4000 50000x 4000 54000x 4000 58000x 4000 5C000x 4000 64000x 4000 68000x 4000 6C000x 4000 70000x 4000 74000x 4000 78000x 4001 00000x 4001 04000x 4001 08000x 4001 0C000x 4001 10000x 4001 14000x 4001 18000x 4001 1C000x 4001 20000x 4001 24000x 4001 28000x 4001 2C000x 4001 30000x 4001 34000x 4001 38000x 4001 3C000x 4001 40000x 4001 4C000x 4001 50000x 4001 54000x 4001 58000x 4002 00000x 4002 04000x 4002 08000x 4002 10000x 4002 14000x 4002 20000x 4002 24000x 4002 30000x 4002 34000x 4002 80000x 5000 04002.5 Clock treeFigure 6. GD32F107xx clock treeLegend:HSE = High speed external clockHSI = High speed internal clockLSE = Low speed external clockLSI = Low speed internal clock2.6 Pin definitionsNotes:1. Type: I = input, O = output, P = power.2. I/O Level: 5VT = 5 V tolerant.3. Functions are available in GD32F107xC, GD32F107xD, GD32F107xE, GD32F107xF, GD32F107xGdevices.4. Functions are available in GD32F107xF, GD32F107xG devices.3 Functional description3.1 ARM® Cortex™-M3 coreThe Cortex™-M3 processor is the latest generation of ARM®processors for embeddedsystems. It has been developed to provide a low-cost platform that meets the needs of MCUimplementation, with a reduced pin count and low-power consumption, while deliveringoutstanding computational performance and an advanced system response to interrupts.⏹32-bit ARM® Cortex™-M3 processor core⏹Up to 108 MHz operation frequency⏹Single-cycle multiplication and hardware divider⏹Integrated Nested Vectored Interrupt Controller (NVIC)⏹24-bit SysTick timerThe Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumband Thumb-2 instruction sets. Some system peripherals listed below are also provided byCortex™-M3:⏹Internal Bus Matrix connected with ICode bus, DCode bus, system bus, PrivatePeripheral Bus (PPB) and debug accesses (AHB-AP)⏹Nested Vectored Interrupt Controller (NVIC)⏹Flash Patch and Breakpoint (FPB)⏹Data Watchpoint and Trace (DWT)⏹Instrument Trace Macrocell (ITM)⏹Memory Protection Unit (MPU)⏹Serial Wire JTAG Debug Port (SWJ-DP)⏹Trace Port Interface Unit (TPIU)3.2 On-chip memory⏹Up to 1024 Kbytes of Flash memory⏹96 Kbytes of SRAMThe ARM®Cortex™-M3 processor is structured in Harvard architecture which can useseparate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at mostand 96 Kbytes of inner SRAM is available for storing programs and data, both accessed(R/W) at CPU clock speed with zero wait states.The Figure 6. GD32F107xx memory mapshows the memory map of the GD32F107xx series of devices, including code, SRAM,peripheral, and other pre-defined regions.3.3 Clock, reset and supply management⏹Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator⏹Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator⏹Integrated system clock PLL⏹ 2.6 to 3.6 V application supply and I/Os⏹Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltagedetector (LVD)The Clock Control Unit (CCU) provides a range of oscillator and clock functions. Theseinclude speed internal RC oscillator and external crystal oscillator, high speed and low speedtwo types.Several prescalers allow the configuration of the AHB frequency, the high-speedAPB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHBand the high-speed APB domains is 108 MHz. The maximum allowed frequency of thelow-speed APB domain is 54 MHz. See Figure 7 for details on the clock tree.The Reset Control Unit (RCU) controls three kinds of reset: system reset resets theprocessor core and peripheral IP components. Power-on reset (POR) and power-down reset(PDR) are always active, and ensures proper operation starting from/down to 2.6 V. Thedevice remains in reset mode when V DD is below a specified threshold. The embedded lowvoltage detector (LVD) monitors the power supply, compares it to the voltage threshold andgenerates an interrupt as a warning message for leading the MCU into security.Power supply schemes:⏹V DD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.Provided externally through V DD pins.⏹V SSA, V DDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,RCs and PLL. V DDA and V SSA must be connected to V DD and V SS, respectively.⏹V BAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator andbackup registers (through power switch) when V DD is not present.3.4 Boot modesAt startup, boot pins are used to select one of three boot options:⏹Boot from main flash memory (default)⏹Boot from system memory⏹Boot from on-chip SRAMThe boot loader is located in the internal boot ROM memory (system memory). It is used toreprogram the Flash memory by using USART1, USART2, CAN2, USB OTG FS in devicemode. It also can be used to transfer and update the Flash memory code, the data and thevector table sections. In default condition, boot from bank 1 of Flash memory is selected. Italso supports to boot from bank 2 of Flash memory by setting a bit in option bytes.3.5 Power saving modesThe MCU supports three kinds of power saving modes to achieve even lower powerconsumption. They are Sleep mode, Deep-sleep mode, and Standby mode.These operatingmodes reduce the power consumption and allow the application to achieve the best balancebetween the CPU operating time, speed and power consumption.⏹Sleep modeIn sleep mode, only the clock of CPU core is off. All peripherals continue to operate andany interrupt/event can wake up the system.⏹Deep-sleep modeIn Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speedcrystal oscillator (HSI, HSE) and PLL are disabled. Only the contents of SRAM andregisters are retained. Any interrupt or wakeup event from EXTI lines can wake up thesystem from the Deep-sleep mode including the 16 external lines, the RTC alarm, theLVD output, and USB wakeup. When exiting the Deep-sleep mode, the HSI is selectedas the system clock.⏹Standby modeIn Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all ofHSI, HSE and PLL are disabled.The contents of SRAM and registers (except BackupRegisters) are lost. There are four wakeup sources for the Standby mode, including theexternal reset from NRST pin, the RTC alarm, the IWDG reset, and the rising edge onWKUP pin.3.6 Analog to digital converter (ADC)⏹12-bit SAR ADC engine⏹Up to 1 MSPS conversion rate⏹Conversion range: V SSA to V DDA (2.6 to 3.6 V)⏹Temperature sensorUp to three 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of upto 21 multiplexed external channels. An analog watchdog block can be used to detect thechannels, which are required to remain within a specific threshold window. A configurablechannel management block of analog inputs also can be used to perform conversions insingle, continuous, scan or discontinuous mode to support more advanced usages.The ADCs can be triggered from the events generated by the general-purpose timers (TMx)and the advanced-control timers (TM1 and TM8) with internal connection. The temperaturesensor has to generate a voltage that varies linearly with temperature. The conversion rangeis between 2.6 V < V DDA< 3.6 V. The temperature sensor is internally connected to theADC_IN16 input channel which is used to convert the sensor output voltage into a digitalvalue.3.7 Digital to analog converter (DAC)⏹Two 12-bit DAC converters of independent output channel⏹8-bit or 12-bit mode in conjunction with the DMA controllerThe two 12-bit buffered DAC channels are used to generate variable analog outputs. TheDACs are designed with integrated resistor strings structure. The DAC channels can betriggered by the timer update outputs or EXTI with DMA support.In dual DAC channeloperation, conversions could be done independently or simultaneously. The maximumoutput value of the DAC is V REF+.3.8 DMA⏹7 channel DMA 1 controller and 5 channel DMA 2 controller⏹Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S⏹Dedicated DMA controller with the Ethernet applicationThe flexible general-purpose DMA controllers provide a hardware method of transferringdata between peripherals and/or memory without intervention from the CPU, thereby freeingup bandwidth for other system functions. Four types of access method are supported:peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memoryEach channel is connected to fixed hardware DMA requests. The priorities of DMA channelrequests are determined by software configuration and hardware channel number.Transfersize of source and destination are independent and configurable.3.9 General-purpose inputs/outputs (GPIOs)⏹Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)⏹Analog input/output configurable⏹Alternate function input/output configurableThere are up to 112 general purpose I/O pins (GPIO) in GD32F107xx, named PA0 ~ PA15and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 toimplement logic input/output functions. Each of the GPIO ports has related control andconfiguration registers to satisfy the requirements of specific applications. The externalinterrupts on the GPIO pins of the device have related control and configuration registers inthe External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with otheralternative functions (AFs) to obtain maximum flexibility on the package pins. Each of theGPIO pins can be configured by software as output (push-pull or open-drain), as input (withor without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins areshared with digital or analog alternate functions. All GPIOs are high-current capable exceptfor analog inputs.3.10 Timers and PWM generation⏹Up to two 16-bit advanced-control timer (TM1 & TM8), ten 16-bit general-purpose timers(GPTM), and two 16-bit basic timer (TM6 & TM7)⏹Up to 4 independent channels of PWM, output compare or input capture for each GPTMand external trigger input⏹16-bit, motor control PWM advanced-control timer with programmable dead-timegeneration for output match⏹Encoder interface controller with two inputs using quadrature decoder⏹24-bit SysTick timer down counter⏹ 2 watchdog timers (Independent watchdog and window watchdog)The advanced-control timer (TM1 & TM8) can be seen as a three-phase PWM multiplexedon 6 channels. It has complementary PWM outputs with programmable dead-timegeneration. It can also be used as a complete general-purpose timer. The 4 independentchannels can be used for⏹Input capture⏹Output compare⏹PWM generation (edge- or center-aligned counting modes)⏹Single pulse mode outputIf configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer.Itcan be synchronized with external signals or to interconnect with other GPTMs togetherwhich have the same architecture and features.The general-purpose timer (GPTM), known as TM2 ~ TM5, TM9 ~ TM11, TM12 ~ TM14 canbe used for a variety of purposes including general time, input signal pulse widthmeasurement or output waveform generation such as a single pulse generation or PWMoutput, up to 4 independent channels for input capture/output compare. The GPTM alsosupports an encoder interface with two inputs using quadrature decoder.The basic timer, known as TM6 and TM7 are mainly used for DAC trigger generation. Theycan also be used as a simple 16-bit time base.The GD32F107xx have two watchdog peripherals, Independent watchdog and windowwatchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.The independent watchdog timer includes a 12-bit down-counting counter and a 8-bitprescaler, It is clocked from an independent 40 kHz internal RC and as it operatesindependently of the main clock, it can operate in stop and standby modes.It can be usedeither as a watchdog to reset the device when a problem occurs, or as a free-running timerfor application timeout management.The window watchdog is based on a 7-bit down counter that can be set as free-running. Itcan be used as a watchdog to reset the device when a problem occurs. It is clocked from themain clock. It has an early warning interrupt capability and the counter can be frozen indebug mode.The SysTick timer is dedicated for OS, but could also be used as a standard down counter. Itfeatures:⏹ A 24-bit down counter⏹Auto reload capability⏹Maskable system interrupt generation when the counter reaches 0⏹Programmable clock source3.11 Real time clock (RTC)⏹32-bit up-counter with a programmable 20-bit prescaler⏹Alarm function⏹Interrupt and wake-up eventThe real time clock is an independent timer which provides a set of continuously runningcounters which can be used with suitable software to provide a clock calendar function, andprovides an alarm interrupt and an expected interrupt. The RTC features a 32-bitprogrammable counter for long-term measurement using the compare register to generatean alarm. A 20-bit prescaler is used for the time base clock and is by default configured togenerate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.3.12 Inter-integrated circuit (I2C)⏹Up to two I2C bus interfaces can support both master and slave mode with a frequencyup to 400 kHz⏹Provide arbitration function, optional PEC (packet error checking) generation andchecking⏹Supports 7-bit and 10-bit addressing mode and general call addressing modeThe I2C interface is an internal circuit allowing communication with an external I2C interfacewhich is an industry standard two line serial interface used for connection to externalhardware. These two serial lines are known as a serial data line (SDA) and a serial clock line(SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400kHz of the fast mode. The I2C module also has an arbitration detect function to prevent thesituation where more than one master attempts to transmit data to the I2C bus at the sametime. A CRC-8 calculator is also provided in I2C interface to perform packet error checkingfor I2C data.3.13 Serial peripheral interface (SPI)⏹Up to two SPI interfaces with a frequency of up to 18 MHz⏹Support both master and slave mode⏹Hardware CRC calculation and transmit automatic CRC error checkingThe SPI interface uses 4 pins, among which are the serial data input and output lines (MISO& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served bythe DMA controller.The SPI interface may be used for a variety of purposes, includingsimplex synchronous transfers on two lines with a possible bidirectional data line or reliablecommunication using CRC checking.3.14 Universal synchronous asynchronous receiver transmitter(USART)⏹Up to three USARTs with operating frequency up to 4.5 MHz⏹Supports both asynchronous and clocked synchronous serial communication modes⏹IrDA SIR encoder and decoder support⏹LIN break generation and detection⏹USARTs support ISO 7816-3 compliant smart card interfaceThe USART (USART1, USART2 and USART3) are used to translate data between paralleland serial interfaces, provides a flexible full duplex data exchange using synchronous orasynchronous transfer. It is also commonly used for RS-232 standard communication. TheUSART includes a programmable baud rate generator which is capable of dividing thesystem clock to produce a dedicated clock for the USART transmitter and receiver.TheUSART also supports DMA function for high speed data communication except UART5.3.15 Inter-IC sound (I2S)⏹Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz⏹Support either master or slave modeThe Inter-IC sound (I2S) bus provides a standard communication interface for digital audioapplications by 3-wire serial lines. GD32F107xx contain two I2S-bus interfaces that can beoperated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI2 andSPI3. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5%accuracy error.3.16 Universal serial bus on-the-go full-speed (USB OTG FS)⏹One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s⏹Internal main PLL for USB CLK compliantlyThe Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The devicecontroller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTGmode. Full-speed peripheral is compliant with the USB 2.0 specification. Transactionformatting is performed by the hardware, including CRC generation and checking. The statusof a completed USB transfer or error condition is indicated by status registers. An interrupt isalso generated if enabled. The dedicated 48 MHz clock is generated from the internal mainPLL (the clock source must use a HSE crystal oscillator) and the operating frequency dividedfrom APB1 should be 12 MHz above.3.17 Controller area network (CAN)⏹Two CAN2.0B interface with communication frequency up to 1 Mbit/s⏹Internal main PLL for USB CLK compliantlyController area network (CAN) is a method for enabling serial communication in field bus.The CAN protocol has been used extensively in industrial automation and automotiveapplications. It can receive and transmit standard frames with 11-bit identifiers as well asextended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission andtwo FIFOs of three message deep for reception.It also provides 14 scalable/configurableidentifier filter banks for selecting the incoming messages needed and discarding the others.3.18 Ethernet MAC interface⏹IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN⏹10/100 Mbit/s rates with dedicated DMA controller and SRAM⏹Support hardware precision time protocol (PTP) with conformity to IEEE 1588The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fullysupports IEEE 1588 standards. The embedded MAC provides the interface to the requiredexternal network physical interface (PHY) for LAN bus connection via an internal mediaindependent interface (MII) or a reduced media independent interface (RMII). The number ofMII signals provided up to 17 with 25 MHz output and RMII up to 9 with 50 MHz output. Thefunction of 32-bit CRC checking is also available.3.19 External memory controller (EXMC)⏹Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash andCF card⏹Up to 16-bit data bus⏹Support to interface with Motorola 6800 and Intel 8080 type LCD directlyExternal memory controller (EXMC) is an abbreviation of external memory controller. It isdivided in to several sub-banks for external device support, each sub-bank has its own chipselection signal but at one time, only one bank can be accessed. The EXMC support codeexecution from external memory except NAND Flash and CF card. The EXMC also can beconfigured to interface with the most common LCD module of Motorola 6800 and Intel 8080series and reduce the system cost and complexity.3.20 Debug mode⏹Serial wire JTAG debug port (SWJ-DP)The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debugport that enables either a serial wire debug or a JTAG probe to be connected to the target.3.21 Package and operation temperature⏹LQFP144 (GD32F107Zx), LQFP100 (GD32F107Vx), LQFP64 (GD32F107Rx)⏹Operation temperature range: -40°C to +85°C (industrial level)。

主要参数 MAIN CHARACTERISTICSI T(RMS) 8A V DRM 600V or 800VI GT 10mA用途APPLICATIONSz 交流开关 z AC switching z 相位控制 z Phase control产品特性FEATURESz 平面钝化芯片高可靠性、一致性 z Planar chip for reliabilityand uniformz 低通态电流和高浪涌电流能力 z High I TSM z 环保RoHS 产品z RoHS productsz 通过UL 认证： E258645z UL ：E258645订货信息 ORDER MESSAGES订 货 型 号 Order code印 记 Marking封 装 Package包 装 PackagingBT137-O-Z-N-C BT137 TO-220 袋装 Bag BT137-O-J-N-B BT137 TO-220S 条管 Tube BT137-O-HF-N-B BT137TO-220HF 条管 Tube绝对最大额定值 ABSOLUTE RATINGS (T C =25℃)项 目 Parameter符 号Symbol 试 验 条 件 Condition数 值Value 单位Unit重复峰值断态电压Repetitive peak off-state voltage V DRM±600 ±800 V 通态方均根电流On-state RMS current I T(RMS)full sine wave 8 A full sine wave ,t=20ms 65 A 非重复浪涌峰值通态电流Non- repetitive surge peak on-state current I TSMfull sine wave ,t=16.7ms 71AI 2t t =10ms 21 A 2s 通态电流临界上升率Repetitive rate ofrise of on-state current after triggering dI/dtI TM =12A, I G =0.2A, dI G /dt=0.2A/μs50 A/μs 峰值门极电流 Peak gate current I GM 2 A 峰值门极电压 Peak gate voltage V GM 5 V 峰值门极功率 Peak gate power P GM 5 W 平均门极功率 Average gate power P G(AV)over any 20ms period0.5W存储温度 Storage temperatureT stg -40~150 ℃ 操作结温Operation junction temperatureT VJ125 ℃电特性 ELECTRICAL CHARACTERISTIC (T C =25℃)项 目 Parameter符 号 Symbol测 试 条 件 Condition最小Min典型 Typ 最大 Max 单位Unit峰值重复断态电流Peak Repetitive Blocking CurrentI DRMV DM =V DRM , Tj=125℃,gate open- 0.10.5 mA峰值通态电压Peak on-state voltageV TM I TM =10A - 1.3 1.65 VMT1(-),MT2(+),G(+)- 2.5 10 mA MT1(-),MT2(+),G(-)- 4.0 10 mA MT1(+),MT2(-),G(-)- 5.0 10 mA 门极触发电流Gate trigger currentI GTV DM =12V,R L =100ΩMT1(+),MT2(-),G(+)- 11 25 mA MT1(-),MT2(+),G(+)- - 1.5 V MT1(-),MT2(+),G(-)- - 1.5 V 门极触发电压Gate trigger voltage V GTV DM =12V,R L =100ΩMT1(+),MT2(-),G(-)- - 1.5 V维持电流Holding current I H V DM =12V, I GT =0.1A - - 20 mAMT1(-),MT2(+),G(+)- 3.0 25 mA MT1(-),MT2(+),G(-)- 14 35 mA 擎住电流Latching current I LV DM =12V,I GT =0.1AMT1(+),MT2(-),G(-)- 3.0 25 mA 断态临界电压上升率 Rise of off- state voltagedV/dtV DM =67% V DRM(MAX), Tj=125℃, gate open- 50 -V/μs 热特性THERMAL CHARACTERISTIC项 目 Parameter 符 号 Symbol条 件 Condition最小Min典型Typ 最大Max 单位Unitfull cycle(TO-220)2.0 ℃/W full cycle(TO-220S)2.8 ℃/W 结到管壳的热阻Thermal resistance junction to caseR th(j-c) full cycle(TO-220HF)4.5℃/W 电绝缘特性ELECTRICAL ISOLATION项 目 Parameter 符 号Symbol 条 件 Condition数 值Value 单位Unit 1 minute, leads to mounting tab TO-220S 2000 V 绝缘电压Isolation voltageV ISOL1 minute, leads to mounting tab TO-220HF2000V特征曲线 ELECTRICAL CHARACTERISTICS (curves)P tot - I T(RMS)I T(RMS) – T c态峰值耗散功率P t o t (W )通态方均根电流I T（R M S ）(A )通态方均根电流I T （RMS ）（A ）管壳温度Tc (℃)I TSM - tpI T(RMS)- ts通态浪涌电流I T S M (A )通态方均根电流I T （R M S ）(A )脉冲宽度tp(ms)冲击持续时间ts(s)I GT (Tj)/I GT (25℃) - TjV TM - I T比值I G T (T j )/I G T (25℃)电流I T (A )结温Tj(℃)通态压降V TM (V)TO-220/TO-220S 单位Unit ：mmNote：For customer requirements，the top of TO-220S mounting base can be formed as angle.TO-220HF 单位Unit ：mm注意事项 NOTE1.吉林华微电子股份有限公司的产品销售分为直销和销售代理，无论哪种方式，订货时请与公司核实。

N E W P R O D U C TProduct SummaryDescription and ApplicationsThe schottky rectifier providing low V F and excellent reverse leakage stability at high temperatures, this device is ideal for use in general rectification applications such as:∙ Boost Diode ∙ Blocking Diode ∙ Recirculating DiodeFeatures and Benefits∙ Reduced Low Forward Voltage Drop (V F ); Better Efficiency and Cooler Operation∙Reduced High-temperature Reverse Leakage; Increased Reliability against Thermal Runaway Failure in High Temperature Operation.∙ Lead-Free Finish; RoHS Compliant (Notes 1 & 2)∙ Halogen and Antimony Free. “Green” Device (Note 3)Mechanical Data∙ Case: SMA∙ Case Material: M olded Plastic, “Green” Molding Compound. UL Flammability Classification Rating 94V-0 ∙ Moisture Sensitivity: Level 1 per J-STD-020∙ Terminals: Finish - Matte Tin Annealed over Copper Leadframe. Solderable per MIL-STD-202, Method 208 ∙ Polarity: Cathode Band∙Weight: 0.063 grams (Approximate)Notes: 1. EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. All applicable RoHS exemptions applied.2. See /quality/lead_free.html for more information about Diodes Incorporated’s definitions of Hal ogen- and Antimony-free, "Green" and Lead-free.3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.4. For packaging details, go to our website at /products/packages.html.Marking InformationB3XXAE = Product Type Marking Code, ex: B320AE= Manufacturers’ Code Marking YWW = Date Code MarkingY = Last Digit of Year (ex: 6 for 2016) WW = Week Code (01 to 53)Top ViewSMABottom ViewB3XXAEGreenN E W P R O D U C TMaximum Ratings (@T A = +25°C, unless otherwise specified.)Single phase, half wave, 60Hz, resistive or inductive load.Thermal CharacteristicsNotes: 5. Device mounted on FR-4 substrate, 1"*1", 2oz, single-sided, PC boards with 0.56"*0.73" copper pad.6. Short duration pulse test used to minimize self-heating effect.N E W P R O D U C TN E W P R O D U C TPackage Outline DimensionsPlease see /package-outlines.html for the latest version.SMASuggested Pad LayoutPlease see /package-outlines.html for the latest version.SMAN E W P R O D U C T万联芯城专注电子元器件配单服务，只售原装现货库存，万联芯城电子元器件全国供应，专为终端生产，研发企业提供现货物料，价格优势明显，BOM配单采购可节省逐个搜索购买环节，只需提交BOM物料清单，商城即可为您报价，万联芯城现货库存销售能够满足多种客户的物料需求，一站式报价为客户节省采购成本，点击进入万联芯城。