SN74LVCH244ADGVR中文资料

O CTAL 3-S TATE N ONINVERTINGB UFFER/L INE D RIVER/L INE R ECEIVERHigh-Speed Silicon-Gate CMOS The IN74ACT244 is identical in pinout to the LS/ALS244, HC/HCT244. The IN74ACT244 may be used as a level converterfor interfacing TTL or NMOS outputs to High Speed CMOSinputs.designed to be used with 3-state memory address drivers, clocknoninverting outputs and two active-low output enables.•TTL/NMOS Compatible Input Levels•Outputs Directly Interface to CMOS, NMOS, and TTL•Operating Voltage Range: 4.5 to 5.5 V •Low Input Current: 1.0 µA; 0.1 µA @ 25°C •Outputs Source/Sink 24 mAORDERING INFORMATIONIN74ACT244N PlasticIN74ACT244DW SOICT A = -40° to 85° C for allpackagesFUNCTION TABLEInputs Outputs Enable A,Enable BA,B YA,YBL L LL H HH X ZX=don’t careZ = high impedanceLOGIC DIAGRAMPIN 20=V CCPIN 10 = GNDPIN ASSIGNMENTMAXIMUM RATINGS*Symbol Parameter ValueUnit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 VV IN DC Input Voltage (Referenced to GND) -0.5 to V CC +0.5 VV OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 VI IN DC Input Current, per Pin ±20 mAI OUT DC Output Sink/Source Current, per Pin ±50 mAI CC DC Supply Current, V CC and GND Pins ±50 mAP D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750500mWTstg Storage Temperature -65 to +150 °CT L Lead Temperature, 1 mm from Case for 10Seconds(Plastic DIP or SOIC Package)260 °C*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°CSOIC Package: - 7 mW/°C from 65° to 125°CRECOMMENDED OPERATING CONDITIONSSymbol Parameter MinMaxUnit V CC DC Supply Voltage (Referenced to GND) 4.5 5.5 VV IN, V OUT DC Input Voltage, Output Voltage (Referenced toGND)0 V CC VT J Junction Temperature (PDIP) 140 °CT A Operating Temperature, All Package Types -40 +85 °CI OH Output Current - High -24 mAI OL Output Current - Low 24 mAt r, t f Input Rise and Fall Time * (except Schmitt Inputs) V CC=4.5 VV CC =5.5 V108.0ns/V* VINfrom 0.8 V to 2.0 VThis device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be constrained to the range GND≤(V IN or V OUT)≤V CC.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)V CC Guaranteed LimitsSymbol Parameter Test Conditions V 25 °C -40°C to85°CUnit V IH Minimum High-Level Input VoltageV OUT = V CC -0.1 V 4.5 5.5 2.0 2.0 2.0 2.0 VV IL Maximum Low -Level Input VoltageV OUT =0.1 V 4.5 5.5 0.8 0.8 0.8 0.8 VV OH Minimum High-Level Output VoltageI OUT ≤ -50 µA 4.5 5.5 4.4 5.4 4.4 5.4 V*V IN =V IHI OH =-24 mAI OH =-24 mA4.55.5 3.86 4.86 3.76 4.76 V OL Maximum Low-Level Output VoltageI OUT ≤ 50 µA 4.5 5.5 0.1 0.1 0.1 0.1 V*V IN =V ILI OL =24 mAI OL =24 mA4.55.5 0.36 0.36 0.44 0.44 I IN Maximum Input Leakage CurrentV IN =V CC or GND 5.5 ±0.1 ±1.0 µAI OZ Maximum Three-State Leakage Current V IN (OE)=V IL or V IH V IN =V CC or GND V OUT =V CC or GND5.5 ±0.5 ±5.0 µA∆I CCT Additional MaxI CC /InputV IN =V CC - 2.1 V 5.5 1.5 mA I OLD +Minimum Dynamic Output CurrentV OLD =1.65 V Max 5.5 75 mAI OHD +Minimum Dynamic Output CurrentV OHD =3.85 V Min 5.5 -75 mAI CC Maximum Quiescent Supply Current(per Package)V IN =V CC or GND 5.5 8.0 80 µAAll outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time.AC ELECTRICAL CHARACTERISTICS(V CC=5.0 V ± 10%, C L=50pF,Input t r=t f=3.0 ns)LimitsGuaranteedUnitSymbol Parameter 25 °C -40°C to85°CMax MinMaxMin t PLH Propagation Delay, A to YA or B to YB2.0 9.0 1.5 10.0 ns(Figure 1)2.0 9.0 1.5 10.0 nst PHL Propagation Delay, A to YA or B to YB(Figure 1)1.5 8.5 1.0 9.5 nst PZH Propagation Delay, Output Enable to YAor YB (Figure 2)t PZL Propagation Delay, Output Enable to YA2.0 9.5 1.5 10.5 nsor YB (Figure 2)2.0 9.5 1.5 10.5 nst PHZ Propagation Delay, Output Enable to YAor YB (Figure 2)2.5 10.0 2.0 10.5 nst PLZ Propagation Delay, Output Enable to YAor YB (Figure 2)C IN Maximum Input Capacitance 4.5 4.5 pFTypical @25°C,V CC=5.0VC PD Power Dissipation Capacitance 45 pFFigure 1. Switching Waveforms Figure 2. Switching Waveforms。

74LV245是低压硅栅CMOS器件，与74HC245和74HCT245针脚和功能兼容。

74LV245是八位元收发器，在发送和接收方向上都具有非反相3态总线兼容输出。

发送/接收(DIR)输入控制方向，而输出使能(OE)输入则可实现轻松级联。

针脚OE控制输出，因此总线可以得到有效隔离。

特性和优势
•宽工作电压范围：1.0 V至5.5 V
•最适合低压应用：1.0 V至3.6 V
•接受介于VCC = 2.7 V和VCC = 3.6 V之间的TTL输入电平
•VCC = 3.3 V且T amb = 25 °C时的典型输出地弹：< 0.8 V
•VCC = 3.3 V且T amb = 25 °C时的典型高电平输出电压(VOH)欠冲：> 2 V •ESD保护：
o HBM JESD22-A114E超过2000 V
o MM JESD22-A115-A超过200 V
•多种封装选择
•额定温度范围为-40 °C至+85 °C和-40 °C至+125 °C
外形图
显示功能框图
真值表
INPUTS INPUTS/OUTPUT OE DIR An Bn
H=高电压L=低电压X=无输入、Z=高阻态。

PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN74LV221AD ACTIVE SOIC D 1640Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LV221ADBR ACTIVE SSOP DB 162000Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LV221ADGVR ACTIVE TVSOP DGV 162000Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221ADR ACTIVE SOIC D 162500Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LV221ANSR ACTIVE SO NS 162000Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LV221APW ACTIVE TSSOP PW 1690Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221APWE4ACTIVE TSSOP PW 1690Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221APWR ACTIVE TSSOP PW 162000Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221APWRE4ACTIVE TSSOP PW 162000Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221APWT ACTIVE TSSOP PW 16250Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LV221APWTE4ACTIVETSSOPPW16250Pb-Free (RoHS)CU NIPDAULevel-1-250C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI'sterms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM6-May-2005Addendum-Page 1元器件交易网元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. 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B data to A bus A data to B bus
Isolation
LOGIC DIAGRAM (POSITIVE LOGIC)
1 DIR
19 OE
A1 2 18 B1
To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
GND B8
SN74LVC245A OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS218T – JANUARY 1993 – REVISED FEBRUARY 2005
DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Voltage range applied to any output in the high or low state(2)(3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current