IDT74FCT16543ETPA中文资料

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Integrated Device Technology, Inc.MILITARY AND COMMERCIAL TEMPERATURE RANGESSEPTEMBER 1996©1996 Integrated Device Technology, Inc.5.12DSC-2618/71

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST CMOS16-BIT LATCHEDTRANSCEIVER

FEATURES:•Common features:–0.5 MICRON CMOS Technology–High-speed, low-power CMOS replacement forABT functions–Typical tSK(o) (Output Skew) < 250ps–Low input and output leakage ≤1µA (max.)–ESD > 2000V per MIL-STD-883, Method 3015;> 200V using machine model (C = 200pF, R = 0)–Packages include 25 mil pitch SSOP, 19.6 mil pitchTSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack–Extended commercial range of -40°C to +85°C–VCC = 5V ±10%•Features for FCT16543T/AT/CT/ET:–High drive outputs (-32mA IOH, 64mA IOL)–Power off disable outputs permit “live insertion”–Typical VOLP (Output Ground Bounce) < 1.0V atVCC = 5V, TA = 25°C•Features for FCT162543T/AT/CT/ET:–Balanced Output Drivers:±24mA (commercial),±16mA (military)–Reduced system switching noise–Typical VOLP (Output Ground Bounce) < 0.6V atVCC = 5V,TA = 25°CIDT54/74FCT16543T/AT/CT/ETIDT54/74FCT162543T/AT/CT/ETFUNCTIONAL BLOCK DIAGRAMDCDC1B11OEBA1CEBA1LEBA1OEAB1CEAB1A11LEABTO 7 OTHER CHANNELS2618 drw 012OEBA2CEBA2LEBADC2OEAB2CEAB2A12B12LEABTO 7 OTHER CHANNELS2618 drw 02DCDESCRIPTION:The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET16-bit latched transceivers are built using advanced dual metalCMOS technology. These high-speed, low-power devices areorganized as two independent 8-bit D-type latched transceiv-ers with separate input and output control to permit indepen-dent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be LOW in order to enter data fromthe A port or to output data from the B port. xLEAB controls thelatch function. When xLEAB is LOW, the latches are transpar-ent. A subsequent LOW-to-HIGH transition of xLEAB signalputs the A latches in the storage mode. xOEAB performs outputenable function on the B port. Data flow from the B port to theA port is similar but requires using xCEBA, xLEBA, and xOEBAinputs. Flow-through organization of signal pins simplifieslayout. All inputs are designed with hysteresis for improvednoise margin.The FCT16543T/AT/CT/ET are ideally suited for drivinghigh-capacitance loads and low-impedance backplanes. Theoutput buffers are designed with power off disable capability toallow "live insertion" of boards when used as backplane drivers.The FCT162543T/AT/CT/ET have balanced output drivewith current limiting resistors. This offers low ground bounce,minimal undershoot, and controlled output fall times–reducingthe need for external series terminating resistors. TheFCT162543T/AT/CT/ET are plug-in replacements for theFCT16543T/AT/CT/ET and 54/74ABT16543 for on-board businterface applications.

元器件交易网www.cecb2b.com5.122

IDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ETFAST CMOS 16-BIT LATCHED TRANSCEIVERMILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

GND1A11A2VCC1A31A4GND1A51A61A71A8GND2A12A2VCC2A32A52A42A7GND2A82A61B11B2GND1B31B4

VCC

1B51B61OEBA1B71B82B12B2GND2B32B4VCC2B5GND2B72B62B8GND2OEBA2OEAB2LEAB2CEAB1OEAB1LEAB1CEAB1LEBA1CEBA2LEBA2CEBA47

37383940414243444546333435365655495051525354481234567891012131415161718192011

21222324

29303132252627282618 drw 04CERPACK

TOP VIEW

E56-11B11B2GND1B31B4VCC1B51B61OEBA1B71B82B12B2GND2B32B4VCC2B5GND2B72B62B8GND2OEBAGND1A11A2

VCC

1A3

1A4

GND1A5

1A6

1A7

1A8

GND2A12A2

VCC

2A3

2A5

2A4

2A7

GND2A8

2A6

2OEAB2LEAB2CEAB

1CEAB1LEAB1OEAB1LEBA1CEBA

2LEBA2CEBA2618 drw 03

47373839404142434445463334353656554950515253544812345678910121314151617181920

11

21222324

SSOP/TSSOP/TVSOPTOP VIEW

SO56-1SO56-2SO56-3

2930313225262728

元器件交易网www.cecb2b.comIDT54/74FCT16543T/AT/CT/ET, 162543T/AT/CT/ETFAST CMOS 16-BIT LATCHED TRANSCEIVERMILITARY AND COMMERCIAL TEMPERATURE RANGES

5.123FUNCTION TABLE(1, 2)For A-to-B (Symmetric with B-to-A)LatchOutputInputsStatusBuffers

xCEABxLEABxOEABxAx to xBxxBxHXXStoringHigh ZXHXStoringXLLLTransparent Current A InputsLHLStoringPrevious* A InputsLLHTransparentHigh ZLHHStoringHigh Z

PIN DESCRIPTIONPin NamesDescriptionxOEABA-to-B Output Enable Input (Active LOW)xOEBAB-to-A Output Enable Input (Active LOW)xCEABA-to-B Enable Input (Active LOW)xCEBAB-to-A Enable Input (Active LOW)xLEABA-to-B Latch Enable Input (Active LOW)xLEBAB-to-A Latch Enable Input (Active LOW)xAxA-to-B Data Inputs or B-to-A 3-State OutputsxBxB-to-A Data Inputs or A-to-B 3-State Outputs2618 tbl 01