AGM-FPGA-AG16KSDF256_pinout

Ports and AttributesTable 5-4 defines the shared clocking ports.Table 5-5 defines the shared clocking attributes.Table 5-4:Shared Clocking PortsPort Dir Clock DomainDescriptionCLKINInN/AReference clock input to the shared PMA PLL.REFCLKOUTOut N/AThe REFCLKOUT port from each GTX_DUAL tile provides access to the reference clock provided to the shared PMA PLL (CLKIN). It can be routed for use in the FPGA logic.Table 5-5:Shared Clocking AttributesAttributeTypeDescriptionCLK25_DIVIDER IntegerCLK25_DIVIDER is set to get an internal clock for the tile.1: CLKIN < 25 MHz2: 25MHz < CLKIN < 50 MHz 3: 50MHz < CLKIN < 75 MHz 4: 75MHz < CLKIN < 100 MHz 5: 100MHz < CLKIN < 125 MHz 6: 125MHz < CLKIN < 150 MHz 10: 150MHz < CLKIN < 250 MHz 12: CLKIN > 250MHzCLKINDC_BBooleanMust be set to TRUE. Oscillators driving the dedicated reference clock inputs must be AC coupled.When set to FALSE for testing, the common mode voltage of the driving circuit must match the common mode voltage of the differential clock input pair (MGTCLKP , MGTCLKN). The differential swing must not exceed the maximum differential swing of the clock input pair.(1, 2)CLKRCV_TRSTBooleanWhen set to FALSE, switches off the internal termination resistors of the differential clock input pair. This results in a high impedance input characteristic that is only intended for testing.When set to TRUE, the differential clock input is nominally terminated with a 100Ω differential impedance. Each clock input in (MGTCLKP ,MGTCKLKN) is contacted via a 50Ω resistor to a midterm nominal voltage of 0.8V .(1, 2)Notes:1.Violation of the rules outlined in this section result in a marginal or dysfunctional design, device degradation in the future, or device damage.2.Consult DS202: Virtex-5 FPGA Data Sheet for the common mode voltage values and the associated differential swing and operating conditions.ResetChapter 5:Tile FeaturesPorts and AttributesTable 5-6 defines the shared tile reset ports.Figure 5-7:GTX_DUAL Reset HierarchyTable 5-6:Shared Tile Reset Ports PortDirDomainDescriptionGTXRESET (1)(2)In AsyncThis port is driven High and then deasserted to start the full GTX_DUAL reset sequence. This sequence takes about 120µs to complete, and systematically resets all subcomponents of the GTX_DUAL tile.RESETDONE0 RESETDONE1Out AsyncThis port goes High when the GTX transceiver has finished reset and is ready for use. For this signal to work correctly, CLKIN and all clock inputs on the individual GTX transceiver (TXUSRCLK, TXUSRCLK2, RXUSRCLK, RXUSRCLK2) must be driven.RXBUFRESET0(1)RXBUFRESET1(2)In AsyncThis active-High signal resets the RX elastic buffer logic.RXCDRRESET0(1)RXCDRRESET1(2)InRXUSRCLK2Individual reset signal for the RX CDR and the RX part of the PCSfor this channel. This signal is driven High to cause the CDR to giveup its current lock and return to the shared PMA PLL frequency.RXRESET0(1)RXRESET1(2)In Async Active-High reset for the RX PCS logic.TXRESET0(1)TXRESET1(2)InAsyncResets the PCS of the GTX transmitter, including the phase adjust FIFO, the 8B/10B encoder, and the FPGA TX interface.Notes:1.When these resets are active, then RESETDONE0 is driven Low. All resets are asynchronous, positive-edge triggered, and synchronized internally to a specific clock domain.2.When these resets are active, then RESETDONE1 is driven Low. All resets are asynchronous, positive-edge triggered, and synchronized internally to a specific clock domain.TX Out-of-Band/Beacon Signaling TX Out-of-Band/Beacon SignalingOverviewEach GTX transceiver provides support for generating the Out-of-Band (OOB) sequencesdescribed in the Serial ATA (SATA) specification and beaconing described in the PCIExpress specification. See Appendix B, “OOB/Beacon Signaling,” for an overview of OOBsignaling and how it is used in these protocols.GTX_DUAL support for SATA OOB signaling consists of the analog circuitry required toencode the OOB signal state and state machines to format bursts of OOB signals for SATACOM sequences (COMRESET, COMWAKE, and COMINIT). Each GTX transceiver alsosupports SATA auto-negotiation by allowing the timing of the COM sequences to bechanged based on the divider settings used for the TX line rate.GTX_DUAL supports beaconing as described in the PHY Interface for the PCI Express (PIPE)Specification. The format of the beacon sequence is controlled by the FPGA logic.Ports and AttributesTable6-20 describes the ports that control OOB/beacon signaling.Table 6-20:TX OOB/Beacon Signaling PortsPort Direction Domain DescriptionRXSTATUS0[2:0] RXSTATUS1[2:0]Out RXUSRCLK2The decoding of RXSTATUS[2:0] depends on the setting ofRX_STATUS_FMT:•When RX_STATUS_FMT = PCIE:RXSTATUS is not used for PCIe TXELECIDLE•When RX_STATUS_FMT = SATA:RXSTATUS[0]: TXCOMSTART operation completeRXSTATUS[1]: COMWAKE signal receivedRXSTATUS[2]: COMRESET/COMINIT signal receivedTXCOMSTART0 TXCOMSTART1In TXUSRCLK2Initiates the transmission of the COM* sequence selected byTXCOMTYPE (SATA only).TXCOMTYPE0 TXCOMTYPE1In TXUSRCLK2Selects the type of COM signal to send (SATA only):0: COMRESET/COMINIT1: COMWAKETXELECIDLE0 TXELECIDLE1In TXUSRCLK2When in the P2 power state, this signal controls whether anelectrical idle or a beacon indication is driven out onto the TX pair.TXPOWERDOWN0[1:0] TXPOWERDOWN1[1:0]In TXUSRCLK2Powers down the TX lanes. When in PCIe mode, the GTX_DUALtile must be in the P2 power state (TXPOWERDOWN = 11) togenerate beacon signaling. Use TXPOWERDOWN = 00 for SATAOOB signaling.Chapter 6:GTX Transmitter (TX)Table 6-21 defines the OOB/beacon signaling attributes.DescriptionThe GTX_DUAL tile supports two signaling modes: one for SATA operations and one for PCI Express operations. The use of these two mechanisms is mutually exclusive.Beacon Signaling for PCI Express OperationsBeacon signaling for PCI Express operations is performed when the GTX_DUAL tile is in the P2 power state. Transmission of a beacon is initiated by the deassertion ofTXELECIDLE, as shown in Figure 6-26. FPGA control logic controls beacon timing by the sequencing of TXELECIDLE.OOB Signaling for SAT A OperationsOOB signaling for SATA operation is initiated through the use of the TXELECIDLE, TXCOMSTART, and TXCOMTYPE ports. When TXELECIDLE is held High, assertion of TXCOMSTART for one TXUSRCLK2 cycle initiates the transmission of a COM sequence. The type of COM sequence generated is controlled by the TXCOMTYPE port as shown in Table 6-20.The number of bursts in the COM sequence is controlled by the COM_BURST_VALattribute. The timing of the COM sequences transmitted is correct as long as the PLL clock (see “Shared PMA PLL,” page 86) is set to 1.5GHz, and PLL_TXDIVSEL_OUT for each channel is set to either 1 (for a 3.0 Gb/s SATA Generation 2 rate) or 2 (for a 1.5 Gb/s SATA Generation 1 rate).Table 6-21:TX OOB/Beacon Signaling AttributesAttributeType DescriptionCOM_BURST_VAL_0COM_BURST_VAL_14-bit BinaryNumber of bursts in a COM sequence.PLL_SATA_0PLL_SATA_1BooleanTie to FALSE. When FALSE, PLL_SATA allows TX SATA operations to work at the SATA Generation 1 (1.5Gb/s) or SATA Generation 2 (3Gb/s) rate.PLL_TXDIVSEL_OUT_0PLL_TXDIVSEL_OUT_1IntegerSets the divider for the TX line rate for theindividual GTX transceiver. Can be set to 1, 2, or 4.Figure 6-26:Beacon Generation for PCI Express Operations。

Microsemi公司的SmartFusion2 SoC FPGA是低功耗FPGA器件,集成了第四代基于闪存FPGA架构,166MHz ARM Cortex-M3处理器和高性能通信接口,是业界最低功耗,最可靠和最高安全的可编逻辑解决方案.高速串行接口包括PCIe,10Gbps附加单元接口(XAUI)/XGMII)以及SerDes通信,主要用在数据安全,马达控制,系统管理,工业自动化,高速串行I/O应用,PCIe,,SGMII以及用户定义的串行接口.本文介绍了SmartFusion2 SoC FPGA主要特性,框图和芯片布局图,以及SmartFusion2 SoC FPGA评估板M2S090TS-EVAL-KIT主要特性,框图,电路图,材料清单和PCB设计图Microsemi SmartFusion®2 SoC FPGAs integrate a fourth-generation,flash-based FPGA fabric, an ARMCortex-M3 processor, and high-performance communications interfaces on a single chip. TheSmartFusion2 family is the industry’s lowest-power, most reliable, and highest-security programmablelogic solution.SmartFusion2 SoC FPGAs offer up to 3.6X the gate density and up to 2X the performance of previousflash-based FPGA families, and also includemultiple memory blocks and multiply-accumulate blocks forDSPprocessing. The 166-MHz ARM Cortex-M3 processor is enhanced with an embedded tracemacrocell (ETM), a memory protection unit (MPU), an 8-KB instruction cache, and additional peripherals,including controller areanetwork (CAN), gigabit Ethernet, and a high-speed universal serial bus(USB).High-speed serial interfaces include PCI Express (PCIe), 10-GbpsAttachment Unit Interface(XAUI)/XGMII extended sublayer (XGXS), plus native serialization/deserialization (SerDes)communication. TheDDR2/DDR3 memory controllers available in the devices provide high-speedmemory interfaces.SmartFusion2 SoC FPGA主要特性:The following sections list the features of SmartFusion2 SoC FPGAs.Reliability•Single event upset (SEU)-immune•Zero FIT FPGA configuration cells•Junction temperature•125 °C—military temperature•100 °C—industrial temperature•85 °C—commercial temperature•125 °C—automotive•Single error correct double error detect (SECDED) protection on the following:•Ethernet buffers•CAN message buffers•Cortex-M3 embedded scratch pad memory (eSRAMs)•USB buffersMicrosemi低功耗SmartFusion2 SoC FPGA开发方案•PCIe buffer•DDR memory controllers with optional SECDED modes•Buffers implemented with SEU resistant latches on the following:•DDR bridges (MSS, MDDR, and FDDR)•Instruction cache•MMUART FIFOs•SPI FIFOs•NVM integrity check at power-up and on demand•No external configuration memory required—instant-on, retains configuration when powered off Security•Design security features (available on all devices)•Intellectual property (IP) protection through unique security features and use models new to thePLD industry•Built-in CRI DPA pass-through license from Rambus Cryptography Research•Encrypted user key and bitstream loading, enabling programming in less-trusted locations•Supply-chain assurance device certificate•Enhanced anti-tamper features•Zeroization•Data security features•Non-deterministic random bit generator (NRBG)•User cryptographic services (AES-256, SHA-256, and elliptical curve cryptographic (ECC)engine)•User physically unclonable function (PUF) key enrollment and regeneration•CRI pass-through DPA patent portfolio license•Hardware firewalls protecting microcontroller subsystem (MSS) memories Low Power•Low static and dynamic power•Flash*Freeze mode for fabric•Power as low as 13 mW/Gbps per lane for SerDes devices•Up to 50% lower total power than competing SoC devices High Performance•Efficient 4-input look-up tables (LUTs) with carry chains for high performance and low power•Up to 236 blocks of dual-port 18-Kbit SRAM (LSRAM) with 400 MHz synchronous performance (512× 36, 512 × 32, 1 Kb × 18, 1 Kb × 16, 2 kbit × 9, 2 Kb × 8, 4 Kb × 4, 8 Kb × 2, or 16 Kb × 1)•Up to 240 blocks of three-port 1-Kb SRAM with two read ports and one write port (micro SRAM)•High-performance DSP signal processing•Up to 240 fast mathblocks with 18 × 18 signed multiplication, 17 × 17 unsigned multiplicationand 44-bit accumulator Microcontroller Subsystem•Hard 166-MHz 32-Bit ARM Cortex-M3 processor•1.25 DMIPS/MHz•8 Kbyte instruction cache•Embedded trace macrocell (ETM)•Memory protection unit (MPU)•Single cycle multiplication, hardware divide•JTAG debug (4 wires), serial wire debug (SWD, 2 wires), and serial wire viewer (SWV) interfaces•64 KB embedded SRAM (eSRAM)•Up to 512 KB embedded nonvolatile memory (eNVM)•Triple-speed Ethernet (TSE) 10/100/1000 Mbps MAC•USB 2.0 high speed on-the-go (OTG) controller with ULPI interface •2.0B-compliant CAN controller, conforms to ISO11898-1, 32 transmit and 32 receive buffers•Two SPI ports, two I2C ports, and multi-mode UARTs (MMUART) peripherals•Hardware-based watchdog timer•One general-purpose 64-bit (or two 32-bit) timer(s)•Real-time calendar/counter (RTC)•DDR bridge (4-port data R/W buffering bridge to DDR memory) with 64-bit AXI interface•Non-blocking, multi-layer AHB bus matrix allowing multi-master scheme supporting 10 masters and7 slaves •Two AHB-Lite/APB3 interfaces to FPGA fabric (master/slave-capable)•Two DMA controllers to offload data transactions from the Cortex-M3 processor•8-channel peripheral DMA (PDMA) for data transfer between MSS peripherals and memory•High-performance DMA (HPDMA) for data transfer between eSRAM and DDR memories Clocking Resources•Clock sources•Up to two high precision 32 KHz to 20 MHz main crystal oscillator•1-MHz embedded RC oscillator•50-MHz embedded RC oscillator•Up to eight clock conditioning circuits (CCCs) with up to eight integrated analog PLLs•Output clock with eight output phases and 45° phase difference (multiply/divide and delaycapabilities)•Frequency: 1 MHz to 200 MHz input, 20 MHz to 400 MHz output •High-Speed Serial Interfaces•Up to 16 SerDes lanes, each supporting:•XGXS/XAUI extension (to implement a 10-Gbps (XGMII) Ethernet PHY interface)•Native EPCS SerDes interface that facilitates implementation of serial rapidIO (SRIO) in fabricor an SGMII interface to the Ethernet MAC in MSS •PCI express (PCIe) endpoint controller•×1, ×2, and ×4 lane PCI express core •Maximum payload size of up to 256 bytes•64-bit/32-bit AXI interface and 64-Bit/32-Bit AHB master and slave interfaces to the applicationlayer High-Speed Memory Interfaces•Up to two high-speed DDRx memory controllers •MSS DDR (MDDR) and fabric DDR (FDDR) controllers •Supports LPDDR/DDR2/DDR3•Maximum 333 MHz DDR clock rate •SECDED enable/disable feature•Supports various DRAM bus width modes, ×8, ×9, ×16, ×18, ×32, ×36•Supports command reordering to optimize memory efficiency•Supports data reordering, returning critical word first for each command •SDRAM support through the SMC_FIC and additional soft SDRAM memory controller Operating Voltage and I/Os•1.2 V core voltage•Multi-standard user I/Os (MSIO/MSIOD)•LVTTL/LVCMOS 3.3 V (MSIO Only)•LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V •DDR (SSTL2_1, SSTL2_2)•LVDS, MLVDS, Mini-LVDS, RSDS differential standards •PCI•LVPECL (receiver only)•DDR I/Os (DDRIO)•DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL •LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V•Market-leading number of user I/Os with 5G SerDes图1:SmartFusion2 SoC FPGA框图SmartFusion2 flash-based fabric has zero FIT configuration rate due to its SEU immunity, which is criticalin reliability applications. The flash fabric also has the advantage that no external configuration memoryis required, making the device instant-on; it retains configuration when powered off. To complement thisunique FPGA capability, SmartFusion2 devices add reliability to many other aspects of the device. Singleerror correct double error detect (SECDED) protection is implemented on the Cortex-M3 embeddedscratch pad memory, Ethernet, CAN, and USB buffers, and is optional on the DDR memory controllers.This means that if a one-bit error is detected, the error is correctedautomatically. If errors of more thanone bit are detected, they are notcorrected. SECDED error signals are brought to the FPGA fabric toallow the user to monitor the status of these protected internal memories. Otherareas of the architectureare implemented with latches, which are moreresistant to SEUs. Therefore, no correction is needed inDDR bridges (MSS, MDDR, and FDDR), instruction cache and MMUART, SPI, and PCIe FIFOs.图2:SmartFusion2 SoC FPGA芯片布局图SmartFusion2 SoC FPGA评估板M2S090TS-EVAL-KIT The RoHS-compliant SmartFusion®2 SoC FPGA Security Evaluation Kit (M2S090TS-EVAL-KIT) enablesyou to develop the following types ofapplications:•Data security•Motor control•System management•Industrial automation•High-speed serial I/O applications:•Peripheral component interconnect express (PCIe)•Serial-gigabit media independent interface (SGMII)•User-customizable serial interfaces评估板M2S090TS-EVAL-KIT包括:图3:评估板M2S090TS-EVAL-KIT框图评估板M2S090TS-EVAL-KIT主要特性:The M2S090TS-EVAL-KIT offers a full-featured evaluation board forSmartFusion2 SoC FPGAs. Theboard integrates the following features on a single chip.•Reliable flash-based FPGA fabric•166 MHz ARM Cortex-M3 processor •Advanced security processing accelerators •Digital signal processing (DSP) blocks •Static random-access memory (SRAM)•Embedded non-volatile memory (eNVM)•High-performance communication interfacesThe SmartFusion2 Security Evaluation Board has several standardinterfaces, including.•A full-duplex serializer/deserializer (SerDes) lane connected through sub-miniature version A (SMA)connectors•A 64-bit GPIO header•Various connectors for serial peripheral interface (SPI) support The SmartFusion2 memory management system supports 512 Mb on-board low-power double data rate(LPDDR) SDRAM memory and 64 Mb SPI flash memory. The SerDes block can either be accessedusing the PCIe edge connector or using high-speed SMA connectors.图4:评估板M2S090TS-EVAL-KIT外形图。

ESP32硬件设计指南版本3.3乐鑫信息科技版权©2022关于本文档《ESP32硬件设计指南》主要提供了在使用ESP32系列产品进行电路设计和PCB布局时需注意的事项。

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目录1产品概述12原理图设计2 2.1电源32.1.1数字电源32.1.2模拟电源52.1.3RTC电源5 2.2上电时序与复位62.2.1上电时序62.2.2复位6 2.3Flash（必选）及SRAM（可选）72.3.1SiP Flash及SiP PSRAM72.3.2外部Flash及片外RAM7 2.4时钟源72.4.1外部时钟参考（必选）82.4.2RTC时钟（可选）8 2.5射频(RF)9 2.6ADC9 2.7外置阻容10 2.8UART10 2.9SDIO11 2.10触摸传感器113版图布局12 3.1独立的ESP32模组的版图设计123.1.1版图设计通用要点123.1.2模组在底板上的位置摆放133.1.3电源143.1.4晶振163.1.5射频173.1.6Flash及PSRAM183.1.7外置阻容183.1.8UART183.1.9触摸传感器18 3.2ESP32作为从设备的版图设计20 3.3版图设计常见问题213.3.1为什么电源纹波并不大，但射频的TX性能很差？213.3.2为什么芯片发包时，电源纹波很小，但射频的TX性能不好？213.3.3为什么ESP32发包时，仪器测试到的power值比target power值要高很多或者低很多，且EVM比较差？213.3.4为什么芯片的TX性能没有问题，但RX的灵敏度不好？224开发硬件介绍235典型应用案例24 5.1ESP32智能音频平台245.1.1ESP32-LyraT音频开发板245.1.2ESP32-LyraTD-MSC音频开发板25 5.2ESP32触摸传感器方案—ESP32-Sense Kit26 5.3ESP-Mesh应用—ESP32-MeshKit27修订历史28插图1ESP32系列芯片参考设计原理图2 2四线3.3V内部flash核心电路图3 3VDD_SDIO电源管脚电路(1.8V)4 4VDD_SDIO电源管脚电路(3.3V)4 5VDD_SDIO电源管脚电路（外部电源供电）4 6ESP32系列芯片模拟电源5 7ESP32系列芯片RTC电源5 8ESP32芯片上电、复位时序图6 9ESP32晶振电路图8 10外置晶振电路图8 11外部激励信号电路图9 12ESP32射频匹配电路图9 13ESP32外置电容10 14ESP32串口11 15ESP32版图设计12 16ESP32模组在底板上的位置示意图13 17ESP32天线区域净空示意图14 18ESP32四层板电源设计15 19九宫格设计15 20ESP32两层板电源设计16 21ESP32晶振设计16 22ESP32四层板射频部分版图设计17 23ESP32两层板射频部分版图设计17 24ESP32Flash及PSRAM版图设计18 25ESP32UART设计18 26典型的触摸传感器应用19 27电极图形要求19 28传感器布局布线20 29PAD/TV Box平面位置规划框架20 30ESP32-LyraT俯视图24 31ESP32-LyraT仰视图25 32ESP32-LyraTD-MSC外观图26 33ESP32-Sense Kit开发套件26 34ESP32-MeshKit-Light灯27 35ESP32-MeshKit-Sense开发板271.产品概述ESP32是集成2.4GHz Wi-Fi和蓝牙双模的单芯片方案，采用台积电(TSMC)低功耗40纳米工艺，具有超高的射频性能、稳定性、通用性和可靠性，以及超低的功耗，满足不同的功耗需求，适用于各种应用场景。

© Copyright 2010–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.General Description7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7 series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factor packaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitive applications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highest capability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable anunparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetric coefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3Endpoint and Root Port designs.•Wide variety of configuration options, including support forcommodity memories, 256-bit AES encryption with HMAC/SHA-256authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm,HKMG, HPL process, 1.0V core voltage process technology and 0.9V core voltage option for even lower power.DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. CapabilitySpartan-7Artix-7Kintex-7Virtex-7Logic Cells 102K 215K 478K 1,955K Block RAM (1) 4.2Mb 13Mb 34Mb 68Mb DSP Slices 1607401,9203,600DSP Performance (2)176 GMAC/s 929GMAC/s 2,845GMAC/s 5,335GMAC/s MicroBlaze CPU (3)260 DMIPs303 DMIPs438 DMIPs441 DMIPsTransceivers –163296Transceiver Speed – 6.6Gb/s 12.5Gb/s 28.05Gb/s Serial Bandwidth –211Gb/s 800Gb/s 2,784Gb/s PCIe Interface –x4 Gen2x8 Gen2x8 Gen3Memory Interface 800Mb/s 1,066Mb/s1,866Mb/s1,866Mb/s I/O Pins 400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V1.2V–3.3V Package Options Low-Cost, Wire-BondLow-Cost, Wire-Bond, Bare-Die Flip-ChipBare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.赛灵思半导体（深圳）有限公司Spartan-7 FPGA Feature Summary Table 2:Spartan-7 FPGA Feature Summary by DeviceDevice LogicCellsCLBDSPSlices(2)Block RAM Blocks(3)CMTs(4)PCIe GT XADCBlocksTotal I/OBanks(5)Max UserI/O Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7S66,000938701010518020002100 XC7S1512,8002,00015020201036020002100 XC7S2523,3603,6503138090451,62030013150 XC7S5052,1608,150600120150752,70050015250 XC7S7576,80012,000832140180903,24080018400 XC7S100102,40016,0001,1001602401204,32080018400 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Does not include configuration Bank 0.Artix-7 FPGA Feature SummaryTable 4:Artix-7 FPGA Feature Summary by DeviceDevice LogicCells Configurable Logic Blocks(CLBs)DSP48E1Slices(2)Block RAM Blocks(3)CMTs(4)PCIe(5)GTPsXADCBlocksTotal I/OBanks(6)Max UserI/O(7) Slices(1)MaxDistributedRAM (Kb)18Kb36Kb Max(Kb)XC7A12T12,8002,00017140402072031213150 XC7A15T16,6402,60020045502590051415250 XC7A25T23,3603,6503138090451,62031413150 XC7A35T33,2805,20040090100501,80051415250 XC7A50T52,1608,150600120150752,70051415250 XC7A75T75,52011,8008921802101053,78061816300 XC7A100T101,44015,8501,1882402701354,86061816300 XC7A200T215,36033,6502,88874073036513,14010116110500 Notes:1.Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.2.Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.4.Each CMT contains one MMCM and one PLL.5.Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.6.Does not include configuration Bank 0.7.This number does not include GTP transceivers.Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/OsPackage(1)CPG236CPG238CSG324CSG325FTG256SBG484FGG484(2)FBG484(2)FGG676(3)FBG676(3)FFG1156 Size (mm)10 x 1010 x 1015 x 1515 x 1517 x 1719 x 1923 x 2323 x 2327 x 2727 x 2735 x 35 Ball Pitch(mm)0.50.50.80.8 1.00.8 1.0 1.0 1.0 1.0 1.0Device GTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTP(4)I/OGTPI/OGTPI/O HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)HR(5)XC7A12T21122150XC7A15T21060210415001704250XC7A25T21124150XC7A35T21060210415001704250XC7A50T21060210415001704250XC7A75T0210017042858300XC7A100T0210017042858300XC7A200T42854285840016500 Notes:1.All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.2.Devices in FGG484 and FBG484 are footprint compatible.3.Devices in FGG676 and FBG676 are footprint compatible.4.GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.5.HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7VX690T-2FFG1927I的详细参数，仅供参考Table 11:Virtex-7 HT FPGA Device-Package Combinations and Maximum I/Os Package(1)FLG1155FLG1931FLG1932Size (mm)35 x 3545 x 4545 x 45Ball Pitch 1.0 1.0 1.0Device GTH GTZI/OGTH GTZI/OGTH GTZI/O HP(2)HP(2)HP(2)XC7VH580T248400488600XC7VH870T7216300 Notes:1.All packages listed are Pb-free with exemption 15. Some packages are available in Pb option.2.HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 1:Spartan-7 FPGA Ordering InformationThe Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free. Refer to the Package Marking section of UG475, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of the device markings.Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering Information。