PDU10256H-8MC5中文资料

2019 MotorcommYT8512C YT8512H DatasheetFAST ETHERNET TRANSCEIVERV1.11DATE 2020/04/24苏州裕太车通 | MotorcommRevision History版权声明Copyright Statement本文档版权归苏州裕太车通电子科技有限公司（以下简称“裕太车通”）所有，并保留一切权利。

未经裕太车通书面许可，任何公司和个人不得将此文档中的任何部分复制、传播、披露或以其他方式散发给第三方。

否则裕太车通将保留追究其法律责任的权利。

This document is copyright of Suzhou Motorcomm Electronic Technology Co., Ltd. ("Motorcomm"). All rights reserved. No company or individual may copy, disseminate, disclose or otherwise distribute any part of this document to any third party without the written consent of Motorcomm. If any company or individual so does, Motorcomm reserves the right to hold it or him liable therefor.免责声明Disclaimer本文档仅提供阶段性信息，所含内容将/可根据产品的实际情况随时更新，恕不另行通知。

如因文档使用不当造成直接或间接损失，裕太车通不承担任何责任。

This document only provides periodic information, and its contents will/may be updated from time to time according to actual situation of Motorcomm’s products without further notice. Motorcomm will not take any responsibility for any direct or indirect losses caused due to improper use of this document.1.General Description (8)Target Application (8)Block Diagram (9)2.Feature (10)3.Pin Assigment (11)YT8512C YT8512H QFN32 5x5mm (11)Pin Descriptions (12)Power on strapping (16)Mode config (17)PHY address (17)Wake on LAN selection (18)3Function Description (19)Application Diagram (19)100Base-Tx/10Base-Te application (19)MII interface (19)RMII interface (20)Management interface (20)DAC (20)ADC (20)Adaptive equalizer (21)Auto- negotiation (21)Polarity detection and auto correction (21)EEE (21)4Operational Description (22)Reset (22)PHY Address (22)XMII interface (23)MII (23)RMII (23)REMII interface (24)Loopback mode (25)Internal loopback: (25)External loopback (25)Remote loopback (25)WoL Wake on lan (27)WOL (27)WOL mechanism (27)WOL Interrupt (28)5Register Overview (29)MII Management Interface Clause 22 Register Programming (29)MII Registers (30)Mii register 00h: Basic control register (30)Mii register 01h: Basic status register (31)Mii register 02h: PHY identification register1 (33)Mii register 03h: PHY identification register2 (33)MII register 04h: Auto-Negotiation advertisement (33)MII register 05h: Auto-Negotiation link partner ability (36)MII register 06h: Auto-Negotiation expansion register (38)MII register 07h: Auto-Negotiation Next Page register (39)MII register 08h: Auto-Negotiation link partner Received Next Page register (39)MII register 0Ah: MASTER-SLAVE status register (40)MII register 0Dh: MMD access control register (41)MII register 0Eh: MMD access data register (42)Mii register 0Fh: Extended status register (42)MII register 10h: PHY specific function control register (42)MII register 11h: PHY specific status register (43)MII register 12h: Interrupt Mask Register (45)MII register 13h: Interrupt Status Register (46)MII register 14h: Speed Auto Downgrade Control Register (47)MII register 15h: Rx Error Counter Register (48)MII register 1Eh: Debug Register’s Address Offset Register (48)MII register 1Fh: Debug Register’s Data Register (48)Extended register (49)EXT 200Ah: 10BT Power control, Register (49)EXT 4000h: extended combo control1 (49)EXT 4001h: extended pad control (50)EXT 4003h: extended combo control2 (50)EXT 4004h: WOL MAC Address (51)EXT 4005h: WOL MAC Address (51)EXT 4006h: WOL MAC Address (51)EXT 40A0h: pkg_selftest control (52)EXT 40A1h: pkg_selftest control (53)EXT 40A2h: pkg_selftest control (53)EXT 40A3h: pkg_selftest status (53)EXT 40A4h: pkg_selftest status (53)EXT 40A5h: pkg_selftest status (54)EXT 40A6h: pkg_selftest status (54)EXT 40A7h: pkg_selftest status (54)EXT 40A8h: pkg_selftest status (54)EXT 40A9h: pkg_selftest status (54)EXT 40Aah: pkg_selftest status (55)EXT 40Abh: pkg_selftest status (55)EXT 40Ach: pkg_selftest status (55)EXT 40Adh: pkg_selftest status (55)EXT 40Aeh: pkg_selftest status (55)EXT 40Afh: pkg_selftest status (56)EXT 40B0h: pkg_selftest status (56)EXT 40B1h: pkg_selftest status (56)EXT 40B2h: pkg_selftest status (56)EXT 40B3h: pkg_selftest status (56)EXT 40B4h: pkg_selftest status (56)EXT 40B5h: pkg_selftest status (57)EXT 40B6h: pkg_selftest status (57)EXT 40B7h: pkg_selftest control (57)EXT 40B8h: pkg_selftest control (57)EXT 40B9h: pkg_selftest control (57)EXT 40BAh: pkg_selftest control (58)EXT 40C0h: LED0 control (58)EXT 40C1h: LED0/1 control (61)EXT 40C2h: LED0/1 control (62)EXT 40C3h: LED1 control (63)6Timing and electrical characteristics (66)Absolute Maximum Ratings (66)Recommended Operating Condition (66)Crystal Requirement (66)Oscillator/External Clock Requirement (67)DC Characteristics (67)MDC/MDIO Timing (68)Power On Sequence/Clock/Reset (68)MII Transmission Cycle Timing (69)MII Reception Cycle Timing (70)RMII Transmission and Reception Cycle Timing (71)7Power Requirements (72)Power consumption (72)MII mode (72)RMII mode (72)Maximum Power Consumption MII MODE (72)8Package information (73)RoHS-Compliant Packaging (73)Thermal resistance (73)9Mechanical Information (74)10Ordering Information (76)1.The YT8512C YT8512H is a low power single-port 10/100 Mbps Ethernet PHY. It provides all physical layer functions needed to transmit and receive data over both standard twisted pair cables transceiver. Additionally, the YT8512C YT8512H provides flexibility to connect to a MAC through a standard MII and RMII interface.The YT8512C YT8512H uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT5 twisted-pair cable.The YT8512C YT8512H offers integrated built-in self-test and loopback capabilities for ease of use. The YT8512C YT8512H offers innovative and robust approach for reducing power consumption through EEE, WoL and other programmable energy savings modes.TARGET APPLICATION⚫General Embedded Applications⚫Video Surveillance⚫Industrial Controls⚫Factory AutomationBLOCK DIAGRAM2.⚫EEE 802.3az, EEE⚫100Base-TX⚫10Base-Te⚫MII mode⚫RMII mode⚫Full/Half duplex⚫Auto-negotiation⚫Power down mode⚫Base Line Wander (BLW) compensation ⚫Auto MDIX⚫Interrupt function⚫WOL, Wake on Lan⚫Automatic Polarity correction⚫ 2 sets LED indicator⚫25 MHz crystal or OSC⚫Provide 50Mhz clock source for MAC ⚫Single Power supply, internal LDO⚫Package QFN 32, 5x 5mm3.YT8512C YT8512H QFN32 5X5MMPIN DESCRIPTIONS⚫I = Input⚫O = Output⚫I/O = Bidirectional⚫OD = Open-drain output⚫PU = Internal pull-up⚫PD = Internal pull-down⚫HZ= High Impendence during power on reset ⚫PWR= Power related⚫XT= Crystal relatedPOWER ON STRAPPINGWAKE ON LAN SELECTION3 FUNCTION DESCRIPTIONAPPLICATION DIAGRAM100BASE-TX/10BASE-TE APPLICATIONMII INTERFACEThe Media Independent Interface (MII) is the digital data interface between the MAC and the physical layer that can be enabled when the device is functioning in 10BASE-Te, 100BASE-TX,. The original MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals include RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Due to pin-count limitations, the YT8512 supports a subset of MII signals. This subset includes all MII signals except TX_ER.SWITCH/MAC MII/RMII/RGMII YT8512 RXD[3:0] TXD[3:0] CMC and Capacitive Coupling 100Base-Tx10Base-TeRMII INTERFACEReduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. If this interface is active, the number of data signal pins required to and from the MAC is reduced to half by doubling clock frequency.MANAGEMENT INTERFACEThe Status and Control registers of the device are accessible through the MDIO and MDC serial interface. The functional and electrical properties of this management interface comply with IEEE 802.3, Section 22 and also support MDC clock rates up to 12.5 MHzDACThe digital-to-analog converter (DAC) transmits MLT3, and Manchester coded symbols. The transmit DAC performs signal wave shaping that reduces electromagnetic interference (EMI). The transmit DAC uses voltage driven output with internal terminations and hence does not require external components or magnetic supply for operation.ADCReceive channel has its own analog-to-digital converter (ADC) that samples the incoming data on the receive channel and feeds the output to the digital data path.ADAPTIVE EQUALIZERThe digital adaptive equalizer removes inter-symbol interference (ISI) created by the channel. The equalizer accepts sampled data from the analog-to-digital converter (ADC) on channel and produces equalized data. The coefficients of the equalizer are adaptive to accommodate varying conditions of cable quality and cable length.AUTO- NEGOTIATIONThe YT8512 negotiates its operation mode using the auto negotiation mechanism according to IEEE 802.3 clause 28 over the copper media. Auto negotiation supports choosing the mode of operation automatically by comparing its own abilities and received abilities from link partner. The advertised abilities include:a)Speed: 10/100Mbpsb)Duplex mode: full duplex and/or half duplexc)PauseAuto negotiation is initialized when the following scenarios happen:a)Power-up/Hardware/Software resetb)Auto negotiation restartc)Transition from power-down to power upd)Link downAuto negotiation is enabled for YT8512 by default, and can be disable by software control.POLARITY DETECTION AND AUTO CORRECTIONYT8512 can detect and correct two types of cable errors: swapping of pairs within the UTP cable and swapping of wires within a pair.For 10BASE-Te/100BASE-TX, YT8512 can handle both cable errors at the same time.EEEEEE is IEEE 802.3az, an extension of the IEEE 802.3 standard. EEE defines support for the PHY to operate in Low Power Idle (LPI) mode which, when enabled, supports QUIET times during low link utilization allowing both link partners to disable portions of each PHY's circuitry and save power.4RESETYT8512 have a hardware reset pin(RESET_N) which is low active. RESET_N should be active for at least 10ms to make sure all internal logic is reset to a known state. Hardware reset should be applied after power up.RESET_N is also used as enable for power on strapping. After RESET_N is released , YT8512 latches input value on POS related pins are used as configuration information which provides flexibility inXMII INTERFACEYT8512 support 4 kinds of MII related interfaces: MII, RMII1, RMII2 and REMII.MIIThe Media Independent Interface (MII) is the digital data interface between the MAC and the physical layer that can be enabled when the device is functioning in 10BASE-Te, 100BASE-TX, The original MII transmit signals include TX_EN, TXC, TXD[3:0], and TX_ER. The receive signals include RX_DV, RXC, RXD[3:0], and RX_ER. The media status signals include CRS and COL. Duemethod;1. RMII1 mode: This is fully conforming to RMII standard.2. RMII2 mode: TXC will be 50MHz output to MAC.Figure .connection diagram of REMIILOOPBACK MODEThere are three loopback modes in YT8512.INTERNAL LOOPBACK:In Internal loopback mode, YT8512 feed transmit data to receive path in chip.Configure bit 14 of mii register(address 0h0) to enable internal loopback mode. For 10Base-Te and 100Base-Tx, YT8512 feeds digital DAC data to ADC directly.Figure . Internal loopbackEXTERNAL LOOPBACKIn external loopback mode, YT8512 feed transmit data to receive path out of chip. For 10Base-Te and 100Base-Tx, just connect TRX_P0/N0 to TRX_P1/N1.Figure . external loopbackREMOTE LOOPBACKIn remote loopback mode, YT8512 feed MII receive data to transmit path in chip. Configure bit 11 of extended register(address 0h4000) and for TRX interface, just connect to link partner normally.Figure . remote loopbackWOL WAKE ON LANWOLWake-on-LAN (WOL) is a mechanism to manage and regulate the total network power consumption.WOL MECHANISMYT8512 supports automatic detection of a specific frame and notification via dedicated hardware interrupt pin or general PHY interrupt pin. The specific frame contains a specific data sequence located anywhere inside the packet. The data sequence consists of 6 bytes of consecutive 1(0xFFFFFFFFFFFF), followed by 16 repetitions of the MAC address of the computer to be waked up. The 48-bit MAC address is written in EXT 0x4004, 0x4005, 0x4006 registers.For example, to write a specific MAC address (0xAAAABBBBCCCC) to PHY, write EXT 0x4004 = 0xAAAA, 0x4005 = 0xBBBB, and 0x4006 = 0xCCCC. The PHY internal MAC address can be set to any value.NOTE: The MAC address is not a real MAC address and is only a symbol to indicate the content of the frame.The WOL mechanism is enabled via EXT 0x4000 bit2. POS RXD[1] can’t control enable or disable the WOL mechanism but only control pad LED0 working as WOL interrupt.WOL INTERRUPTYT8512 support dedicated WOL interrupt pin. When the pad RXD[1] is externally PULL UP, pad LED0 will work as WOL interrupt.If EXT 0x4003 bit7 is 0, the dedicated WOL interrupt is programmed to a level, otherwise, it’s programed to a pulse; either is active low. When it’s programmed to a pulse, the pulse width can be programmed via EXT 0x4003 bit9:8.WOL interrupt is also wire-and to general PHY interrupt RXD[2]_INTN when the bit6 INT_WOL in Interrupt enable register (MII Register 0x12) is set to 1. If the general PHY interrupt is triggered by WOL, it can be cleared by reading MII register 0x13 bit6.NOTE:When general PHY interrupt is used to monitor WOL interrupt, EXT 0x4003 bit7 should be 1, otherwis e, the general PHY interrupt can’t be read cleared.Because PHY requires to receive packets from the line side, PHY cannot be powered down. If the link partner supports Energy Efficient Ethernet function, both ends can use EEE mode to save more power. MII register 0x0 bit10 ISOLATE: When this bit is set to 1, the xMII output pins are HighZ. The xMII inputs are ignored.5MII MANAGEMENT INTERFACE CLAUSE 22 REGISTER PROGRAMMINGThe YT8512 transceiver is designed to be fully compliant with the MII clause of the IEEE 802.3u Ethernet specification.The MII management interface registers are written and read serially, using the MDIO and MDC pins.A clock of up to 12.5 MHz must drive the MDC pin of the YT8512. Data transferred to and from the MDIO pin is synchronized with the MDC clock. The following sections describe what each MII read orMII REGISTERSMII REGISTER 00H: BASIC CONTROL REGISTERMII REGISTER 01H: BASIC STATUS REGISTERMII REGISTER 08H: AUTO-NEGOTIATION LINK PARTNER RECEIVED NEXT PAGE REGISTERMII REGISTER 0EH: MMD ACCESS DATA REGISTERMII REGISTER 12H: INTERRUPT MASK REGISTERMII REGISTER 13H: INTERRUPT STATUS REGISTERMII REGISTER 1FH: DEBUG REGISTER’S DATA REGISTEREXTENDED REGISTEREXT 200AH: 10BT POWER CONTROL, REGISTER。

OSC
RST /INH
Oscillation Pin. I/O The oscillation circuit of a resistor and capacitor connection.
Oscillator is activated when the key is pressed. Reset Pin. I This pin sets the initial volume level. The volume level is set to -46dB by “L” Input. Built-in Pull-up Resistor Low Active I Backup Mode Input Pin
PT2256V
VS S OUT1
IN 1
LT 1 AGND
VD D OUT2 IN 2
LT 2 AGND
/U P /D N
OSC
Decoder
Up/D own Counter Contr ol
D/A Con ve rte r
DCO /I N H /R ST
PT2256V V1.2
-2-
August, 2006
DCO
O DC Output Pin for Volume Level Meter
LT2
O Tap Output Pin 2 for Loudness Function
IN2 OUT2 VDD
I Volume Input Pin 2 O Volume Output Pin 2 - Positive Power Supply
PT2256V V1.2
-5-
August, 2006
元器件交易网
Tel:886-2-66296288 Fax:886-2-29174598 URL:

UL635H256Obsolete - Not Recommended for New DesignsPin ConfigurationPin DescriptionSignal Name Signal Description A0 - A14Address Inputs DQ0 - DQ7Data In/Out E Chip Enable G Output Enable W Write EnableVCC Power Supply Voltage VSSGroundG A11A9A8A13W n. c.VCC n. c.A14A12A7A6A5A4A3n.c.A10E DQ7DQ6DQ5DQ4DQ3VSS DQ2DQ1DQ0A0A1A2n.c.12345678910111213141516TSOPTop View32313029282726252423222120191817A14A12A7A6A5A4A3A2A1A0DQ0DQ1DQ2VSS VCC W A13A8A9A11G A10E DQ7DQ6DQ5DQ4DQ31234567891011121314SOPTop View 2827262524232221201918171615Low Voltage PowerStore 32K x 8 nvSRAM•High-performance CMOS non- volatile static RAM 32768 x 8 bits •35 and 45 ns Access Times •15 and 20 ns Output Enable Access Times•I CC = 8 mA typ. at 200 ns Cycle Time•Automatic STORE to EEPROM on Power Down using system capacitance•Software initiated STORE •Automatic STORE Timing•106 STORE cycles to EEPROM •100 years data retention in EEPROM•Automatic RECALL on Power Up •Software RECALL Initiation •Unlimited RECALL cycles from EEPROM•Wide voltage range: 2.7 ... 3.6 V (3.0 ... 3.6 V for 35 ns type)•Operating temperature range:0 to 70 °C -40 to 85 °C•QS 9000 Quality Standard •ESD protection > 2000 V(MIL STD 883C M3015.7-HBM)•RoHS compliance and Pb- free •Package:SOP28 (330 mil)The UL635H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab-led.The UL635H256 is a fast static RAM (35 and 45 ns), with a nonvo-latile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi-des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on powerup.The UL635H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity.STORE cycles also may be initia-ted under user control via a soft-ware sequence.Once a STORE cycle is initiated,further input or output are disabled until the cycle is completed.Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted.RECALL cycles may also be initia-ted by a software sequence.Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola-tile information is transferred into the SRAM cells.The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.FeaturesDescriptionUL635H256EEPROM Array 512 x (64 x 8)RECALLDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7Column I/O Column DecoderA0 - A13Store/Recall ControlR o w D e c o d e rV CC V SSGE WA0 A 1 A2 A3 A4A10Software DetectPower ControlV CCA5A6A7A8A9A11A12A13A14I n p u t B u f f e r sSTORESRAM Array 512 Rows x 64 x 8 ColumnsBlock DiagramTruth Table for SRAM OperationsOperating Mode E WGDQ0 - DQ7Standby/not selectedH **High-Z Internal ReadL H H High-Z Read L H LData Outputs Low-Z WriteLL*Data Inputs High-Z*H or LCharacteristicsAll voltages are referenced to V SS = 0 V (ground).All characteristics are valid in the power supply voltage range and in the operating temperature range specified.Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of V I , as well as input levels of V IL = 0 V and V IH = 3 V. The timing reference level of all input and output signals is 1.5 V,with the exception of the t dis -times and t en -times, in which cases transition is measured ± 200 mV from steady-state voltage.a: Stresses greater than those listed under …Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stressrating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.Absolute Maximum Ratings a Symbol Min.Max.Unit Power Supply Voltage V CC -0.5 4.6V Input Voltage V I -0.3V CC +0.5V Output Voltage V O -0.3V CC +0.5V Power Dissipation P D 1W Operating Temperature C-Type K-TypeT a 0-407085°C °C Storage TemperatureT stg-65150°CUL635H256b:I CC1 and I CC3 are depedent on output loading and cycle rate. The specified values are obtained with outputs unloaded.The current I CC1 is measured for WRITE/READ - ratio of 1/2.c:I CC2 and I CC4 are the average currents required for the duration of the respective STORE cycles.d:Bringing E ≥ V IH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTIONtable. The current I CC(SB)1 is measured for WRITE/READ - ratio of 1/2.DC Characteristics Symbol ConditionsC-TypeK-TypeUnitMin.Max.Min.Max.Operating Supply Current bI CC1V CC V IL V IH t c t c= 3.6 V = 0.8 V = 2.2 V = 35 ns = 45 ns 45354737mA mA Average Supply Current during c STOREI CC2V CC E W V IL V IH = 3.6 V ≤ 0.2 V≥ V CC -0.2 V ≤ 0.2 V≥ V CC -0.2 V 34mAOperating Supply Current b at t cR = 200 ns(Cycling CMOS Input Levels)I CC3V CC W V IL V IH = 3.6 V≥ V CC -0.2 V ≤ 0.2 V≥ V CC -0.2 V 1011mAAverage Supply Current during c PowerStore Cycle I CC4V CC V IL V IH = V CCmin = 0.2 V≥ V CC -0.2 V 22mAStandby Supply Current d (Cycling TTL Input Levels)I CC(SB)1V CC E t c t c= 3.6 V = V IH = 35 ns = 45 ns 1191210mA mA Standby Supply Curent d(Stable CMOS Input Levels)I CC(SB)V CC E V IL V IH= 3.6 V≥ V CC -0.2 V ≤ 0.2 V≥ V CC -0.2 V11mARecommendedOperating Conditions Symbol Conditions Min.Max.Unit Power Supply VoltageV CCt c = 35 ns t c = 45 ns3.02.7 3.63.6V V Input Low Voltage V IL -2 V at Pulse Width 10 ns permitted-0.30.8V Input High VoltageV IH2.2V CC +0.3VUL635H256DC Characteristics Symbol ConditionsC-Type K-TypeUnit Min.Max.Min.Max.Output High Voltage Output Low Voltage V OHV OLV CCI OHI OL= V CC min=-2 mA= 2 mA2.40.42.40.4VVOutput High Current Output Low Current I OHI OLV CCV OHV OL= V CC min= 2.4 V= 0.4 V2-22-2mAmAInput Leakage CurrentHigh Low I IHI ILV CCV IHV IL= 3.6 V= 3.6 V=0V-11-11μAμAOutput Leakage CurrentHigh at Three-State- Output Low at Three-State- Output I OHZI OLZV CCV OHV OL= 3.6 V= 3.6 V=0V-11-11μAμASRAM Memory OperationsNo.Switching CharacteristicsRead CycleSymbol3545UnitAlt.IEC Min.Max.Min.Max.1Read Cycle Time f t AVAV t cR3545ns 2Address Access Time to Data Valid g t AVQV t a(A)3545ns 3Chip Enable Access Time to Data Valid t ELQV t a(E)3545ns4Output Enable Access Time to Data Valid t GLQVt a(G)1520ns5 E HIGH to Output in High-Z h t EHQZ t dis(E)1315ns 6G HIGH to Output in High-Z h t GHQZ t dis(G)1315ns 7 E LOW to Output in Low-Z t ELQX t en(E)55ns 8G LOW to Output in Low-Z t GLQX t en(G)00ns 9Output Hold Time after Address Change t AXQX t v(A)33ns 10Chip Enable to Power Active e t ELICCH t PU00ns 11Chip Disable to Power Standby d, e t EHICCL t PD3545ns e:Parameter guaranteed but not tested.f:Device is continuously selected with E and G both Low.g:Address valid prior to or coincident with E transition LOW.h:Measured ± 200 mV from steady state output voltage.UL635H256Read Cycle 1: Ai-controlled (during Read cycle: E = G = V IL , W = V IH )fNo.Switching Characteristics Write Cycle Symbol3545UnitAlt. #1Alt. #2IEC Min.Max.Min.Max.12Write Cycle Time t AVAV t AVAVt cW 3545ns 13Write Pulse Widtht WLWHt w(W)2530ns 14Write Pulse Width Setup Time t WLEHt su(W)2530ns 15Address Setup Time t AVWL t AVEL t su(A)00ns 16Address Valid to End of Write t AVWH t AVEH t su(A-WH)2530ns 17Chip Enable Setup Time t ELWHt su(E)2530ns 18Chip Enable to End of Write t ELEHt w(E)2530ns 19Data Setup Time to End of Write t DVWH t DVEH t su(D)1215ns 20Data Hold Time after End of Write t WHDX t EHDX t h(D)00ns 21Address Hold after End of Write t WHAX t EHAX t h(A)0ns 22W LOW to Output in High-Z h, i t WLQZ t dis(W)1315ns 23W HIGH to Output in Low-Zt WHQXt en(W)55nsRead Cycle 2: G-, E-controlled (during Read cycle: W = V IH )gAi DQiOutputAi E GI CCDQiOutputUL635H256L- to H-level undefined H- to L-leveli:If W is low and when E goes low, the outputs remain in the high impedance state.j:E or W must be V IH during address transition.Write Cycle #1: W-controlled jWrite Cycle #2: E-controlled jAi E W DQiInputDQiOutputHigh ImpedanceAi E W DQiInputDQiOutputUL635H256 Nonvolatile Memory OperationsMode SelectionE W A13 - A0(hex)Mode I/O Power NotesH X X Not Selected Output High Z StandbyL H X Read SRAM Output Data Active m L L X Write SRAM Input Data ActiveL H0E3831C703E03C1F303F0FC0Read SRAMRead SRAMRead SRAMRead SRAMRead SRAMNonvolatile STOREOutput DataOutput DataOutput DataOutput DataOutput DataOutput High ZActive k, lk, lk, lk, lk, lk, lL H0E3831C703E03C1F303F0C63Read SRAMRead SRAMRead SRAMRead SRAMRead SRAMNonvolatile RECALLOutput DataOutput DataOutput DataOutput DataOutput DataOutput High ZActive k, lk, lk, lk, lk, lk, lk:The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details.The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.l:While there are 15 addresses on the UL635H256, only the lower 14 are used to control software modes.Activation of nonvolatile cycles does not depend on the state of G.m:I/O state assumes that G ≤ V IL.No.PowerStorePower Up RECALLSymbolConditions Min.Max.UnitAlt.IEC24Power Up RECALL Duration n t RESTORE650μs25STORE Cycle Duration f, e t PDSTORE the power supply decayrate has to be smallerthan 10 Vs-1 after thestart of the STOREoperation10ms26Time allowed to Complete SRAMCycle ft DELAY500ns Low Voltage Trigger Level V SWITCH 2.4 2.7Vn: t RESTORE starts from the time V CC rises above V SWITCH.UL635H256o:The software sequence is clocked with E controlled READs.p:Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.q:Note that STORE cycles (but not RECALL) are aborted by V CC < V SWITCH (STORE inhibit).r: An automatic RECALL also takes place at power up, starting when V CC exceeds V SWITCH and takes t RESTORE . V CC must not drop below V SWITCH once it has been exceeded for the RECALL to function properly.s:Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.t:If the Chip Enable Pulse Width is less than t a(E) (see Read Cycle) but greater than or equal t w(E)SR , than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated.No.Software Controlled STORE/RECALL Cycle k, o Symbol 3545UnitAlt.IEC Min.Max.Min.Max.27STORE/RECALL Initiation Time t AVAV t cR 3545ns 28Chip Enable to Output Inactive p t ELQZ t dis(E)SR 600600ns 29STORE Cycle Time q t ELQXS t d(E)S 1010ms 30RECALL Cycle Time rt ELQXR t d(E)R 2020μs 31Address Setup to Chip Enable s t AVELN t su(A)SR 00ns 32Chip Enable Pulse Width s, t t ELEHN t w(E)SR 2530ns 33Chip Disable to Address Change st EHAXNt h(A)SRnsPowerStore and automatic Power Up RECALLV CC3.0 VPowerStorePower Up V SWITCH W DQiPOWER UP RECALL BROWN OUT BROWN OUT PowerStore(NO SRAM WRITES)RECALL NO STOREUL635H256Software Controlled STORE/RECALL Cycle t, u, v (E = HIGH after STORE initiation)u:W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOWthroughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines wheter the UL635H256 performs a STORE or RECALL.v: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.Ai EDQiOutputSoftware Controlled STORE/RECALL Cycle t, u, v, w (E = LOW after STORE initiation)Ai EDQiOutputUL635H256Test Configuration for Functional CheckV IHV ILV SS1.1 k95030 pF wV O S i m u l t a n e o u s m e a s u r e -m e n t o f a l l 8 o u t p u t p i n sI n p u t l e v e l a c c o r d i n g t o t h er e l e v a n t t e s t m e a s u r e m e n tDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7A0A1A2A3A4A5A6A7A8A9A10A11A12E W G3 VA13A14V CCXw:In measurement of t dis -times and t en -times the capacitance is 5 pF.x:Between V CC and V SS must be connected a high frequency bypass capacitor 0.1 μF to avoid disturbances.Capacitance e Conditions Symbol Min.Max.Unit Input Capacitance V CC V I f T a= 3.0 V = V SS = 1MHz = 25 °CC I 8pF Output CapacitanceC O7pFAll Pins not under test must be connected with ground by capacitors.Operating Temperature Range C =0to 70 °C K =-40to 85 °CG1S245C UL635H256TypePackageS =SOP28 (330mil) Type 1 S2 = SOP28 (330mil) Type 2Ordering Code Leadfree Optionblank =Standard PackageG1=Leadfree Green Package Access Time35=35 ns (V CC = 3.0 ... 3.6 V)45=45 ns (V CC = 2.7 ... 3.6 V)y: on special requestExample Date of manufacture(The first 2 digits indicating the year, and the last 2 digits the calendar week.)Leadfree Green PackageProduct specificationInternal CodeDevice Marking (example)ZMDUL635H256S2C 45Z 0425G1UL635H25611March 31, 2006STK Control #ML0059Rev 1.0Device OperationThe UL635H256 has two separate modes of operation:SRAM mode and nonvolatile mode. The memory ope-rates in SRAM mode as a standard fast static RAM.Data is transferred in nonvolatile mode from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled.STORE cycles may be initiated under user control via a software sequence and are also automatically initiated when the power supply voltage level of the chip falls below V SWITCH . RECALL operations are automatically initiated upon power up and may also occur when the V CC rises above V SWITCH , after a low power condition.RECALL cycles may also be initiated by a software sequence.SRAM READThe UL635H256 performs a READ cycle whenever E and G are LOW and W is HIGH. The address specified on pins A0 - A14 determines which of the 32768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of t cR . If the READ is initiated by E or G, the out-puts will be valid at t a(E) or at t a(G), whichever is later.The data outputs will repeatedly respond to address changes within the t cR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW.SRAM WRITEA WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid t su(D) before the end of a W controlled WRITE or t su(D) before the end of an E controlled WRITE.It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers t dis (W) after W goes LOW.Automatic STOREThe UL635H256 uses the intrinsic system capacitance to perform an automatic STORE on power down. As long as the decay rate from the system power supply is smaller than 15 Vs -1 the UL635H256 will safely and automatically STORE the SRAM data in EEPROM on power down.In order to prevent unneeded STORE operations, auto-matic STORE will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether or not a WRITE operation has taken place.Automatic RECALLDuring power up, an automatic RECALL takes place. At a low power condition (power supply voltage < V SWITCH )an internal RECALL request may be latched. As soon as power supply voltage exceeds the sense voltage of V SWITCH , a requested RECALL cycle will automatically be initiated and will take t RESTORE to complete.If the UL635H256 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 k Ω resistor should be connected between W and power supply voltage.Software Nonvolatile STOREThe UL635H256 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the UL635H256 implements nonvolatile operation while remaining compatible with standard 32K x 8SRAMs. During the STORE cycle, an erase of the pre-vious nonvolatile data is performed first, followed by a parallel programming of all the nonvolatile elements.Once a STORE cycle is initiated, further inputs and out-puts are disabled until the cycle is completed.Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted.To initiate the STORE cycle the following READ sequence must be performed:1. Read addresses 0E38(hex)Valid READ 2. Read addresses 31C7(hex)Valid READ 3. Read addresses 03E0(hex)Valid READ 4. Read addresses 3C1F (hex)Valid READ 5. Read addresses 303F (hex)Valid READ 6.Read addresses0FC0(hex)Initiate STORE CycleOnce the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be LOW for the sequence to be valid. After the t STORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.UL635H25612 March 31, 2006STK Control #ML0059Rev 1.0Software Nonvolatile RECALLA RECALL cycle of the EEPROM data into the SRAMis initiated with a sequence of READ operations in amanner similar to the STORE initiation. To initiate theRECALL cycle the following sequence of READ opera-tions must be performed:1. Read addresses0E38(hex)Valid READ2. Read addresses31C7(hex)Valid READ3. Read addresses03E0(hex)Valid READ4. Read addresses3C1F(hex)Valid READ5. Read addresses303F(hex)Valid READ6. Read addresses0C63(hex)Initiate RECALLCycleInternally, RECALL is a two step procedure. First, theSRAM data is cleared and second, the nonvolatileinformation is transferred into the SRAM cells. Aftert d(E)R cycle time the SRAM will once again be ready forREAD and WRITE operations.The RECALL operationin no way alters the data in the EEPROM cells. Thenonvolatile data can be recalled an unlimited number oftimes.Hardware ProtectionThe UL635H256 offers hardware protection againstinadvertent STORE operation through V CC Sense.When V CC < V SWITCH all software STORE operationswill be inhibited.Low Average Active PowerThe UL635H256 has been designed to draw signifi-cantly less power when E is LOW (chip enabled) butthe cycle time is longer than 45 ns.When E is HIGH the chip consumes only standby cur-rent.The overall average current drawn by the part dependson the following items:1. CMOS or TTL input levels2. the time during which the chip is disabled (E HIGH)3. the cycle time for accesses (E LOW)4. the ratio of READs to WRITEs5. the operating temperature6. the V CC levelThe information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.UL635H256LIFE SUPPORT POLICYSimtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Simtek product could create a situation where personal injury or death may occur.Components used in life-support devices or systems must be expressly authorized by Simtek for such purpose. LIMITED WARRANTYThe information in this document has been carefully checked and is believed to be reliable. However, Simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics.Simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent Simtek’s warranty on any product beyond that set forth in its standard terms and conditions of sale.Simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.March 31, 2006Change recordDate/Rev Name Change01.11.2001Ivonne Steffens format revision and release for …Memory CD 2002“03.07.2002Matthias Schniebel adding 35 ns type with V CC = 3.0 ... 3.6 V25.09.2002Matthias Schniebel Adding …Type 1“ to SOP28 (330mil)09.01.2003Matthias Schniebel Removing 55 ns type20.10.2003Matthias Schniebel Low Voltage Trigger Level V SWITCH = 2.4 ... 2.7 V (old: 2.5 ... 2.7 V)changing max. decay rate from the system power supply to 15 Vs-1(old: 10 Vs-1)05.12.2003Matthias Schniebel I CC = 8 mA typ. at 200 ns Cycle Timeadding K-Type with 35 ns: I CC1 = 47 mA, I CC(SB)1 = 12mA21.04.2004Matthias Schniebel adding …Leadfree Green Package“ to ordering informationadding …Device Marking“7.4.2005Stefan Günther Page1: adding RoHS compliance and Pb- free, 106 endurance cyclesand 100a data retention,add also S2 package (chip pack) and ordering code31.3.2006Troy Meester changed to obsolete status1.0Simtek Assigned Simtek Document Control Number。

Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 0 2 2
Symbol#43;25°C §tRC = Read Cycle Time
†
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 8 10 pF pF
–55°C to +125°C –40°C to +85°C Industrial Commercial 0°C to +70°C
Output Capacitance VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2) Symbol VIH VIL V HC VLC VOL VOH Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., ILO Output Leakage Current CE = VIH, VOUT = GND to VCC CE ≥ VIH ISB Mil. ___ ___ 45 30 ___ ___ 30 n/a mA Mil. Ind./Com’l. Mil. Ind./Com’l. 2.4 –10 –5 –10 –5 +10 +5 +10 +5 Test Conditions P4C1256 Min Max VCC +0.5 2.2 P4C1256L Unit Min Max VCC +0.5 V 2.2 V V V V V +5 n/a +5 n/a µA µA