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IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service without notice, and advises its customers to obtain the latestversion of relevant information to verify, before placing orders, that the information being reliedon is current.TI warrants performance of its semiconductor products and related software to the specificationsapplicable at the time of sale in accordance with TI’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent TI deems necessary to support this warranty.Specific testing of all parameters of each device is not necessarily performed, except thosemandated by government requirements.Certain applications using semiconductor products may involve potential risks of death,personal injury, or severe property or environmental damage (“Critical Applications”).TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICESOR SYSTEMS OR OTHER CRITICAL APPLICATIONS.Inclusion of TI products in such applications is understood to be fully at the risk of the customer.Use of TI products in such applications requires the written approval of an appropriate TI officer.Questions concerning potential risk applications should be directed to TI through a local SCsales office.In order to minimize risks associated with the customer’s applications, adequate design andoperating safeguards should be provided by the customer to minimize inherent or proceduralhazards.TI assumes no liability for applications assistance, customer product design, softwareperformance, or infringement of patents or services described herein. Nor does TI warrant orrepresent that any license, either express or implied, is granted under any patent right, copyright,mask work right, or other intellectual property right of TI covering or relating to any combination,machine, or process in which such semiconductor products or services might be or are used.Copyright © 1996, Texas Instruments Incorporated2ContentsTitle Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. Introduction1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. Symbol Composition2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. Qualifying Symbols43.1 General Qualifying Symbols4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2 Qualifying Symbols for Inputs and Outputs5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3 Symbols Inside the Outline6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. Dependency Notation8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.1 General Explanation8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2 G (AND) Dependency9. . . . . . . . . . . . . . . . . . . . . .4.3 Conventions for the Application of Dependency Notation in General10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.4 V (OR) Dependency11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5 N (Negate) (Exclusive-OR) Dependency11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.6 Z (Interconnection) Dependency12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.7 X (Transmission) Dependency13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.8 C (Control) Dependency14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.9 S (Set) and R (Reset) Dependencies15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.10 EN (Enable) Dependency16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.11 M (Mode) Dependency174.11.1 M Dependency Affecting Inputs17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.11.2 M Dependency Affecting Outputs174.12 A (Address) Dependency19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Bistable Elements21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. Coders23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. Use of a Coder to Produce Affecting Inputs25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. Use of Binary Grouping to Produce Affecting Inputs26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9. Sequence of Input Labels2710. Sequence of Output Labels28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .List of TablesTable Title Page 1General Qualifying Symbols4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Qualifying Symbols for Inputs and Outputs5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Symbols Inside the Outline7 4Summary of Dependency Notation20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iiiList of IllustrationsFigure Title Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Symbol Composition2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Common-Control Block2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Common-Output Element3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4G Dependency Between Inputs9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5G Dependency Between Outputs and Inputs9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6G Dependency With a Dynamic Input9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7ORed Affecting Inputs10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Substitution for Numbers10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9V (OR) Dependency11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10N (Negate) (Exclusive-OR) Dependency11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Z (Interconnection) Dependency12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12X (Transmission) Dependency13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13CMOS Transmission Gate Symbol and Schematic13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Analog Data Selector (Multiplexer/Demultiplexer)13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 C (Control) Dependency14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16S (Set) and R (Reset) Dependencies15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17EN (Enable) Dependency16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18M (Mode) Dependency Affecting Inputs17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Type of Output Determined by Mode18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20An Output of the Common-Control Block18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Determining an Output’s Function18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Dependent Relationships Affected by Mode18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 A (Address) Dependency1924Array of 16 Sections of Four Transparent Latches With 3-State Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Comprising a 16-Word × 4-Bit Random-Access Memory20 25Four Types of Bistable Circuits21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Coder General Symbol23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27An X/Y Code Converter23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28An X/Octal Code Converter24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Producing Various Types of Dependencies25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Producing One Type of Dependency25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Use of the Binary Grouping Symbol26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Input Labels27 33Factoring Input Labels27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Placement of 3-State Symbols28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Output Labels28 36Factoring Output Labels28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv1 IntroductionThe International Electrotechnical Commission (IEC) has been developing a very powerful symbolic language that can show the relationship of each input of a digital logic circuit to each output without showing explicitly the internal logic. At the heart of the system is dependency notation, which will be explained in Section 4.The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32.14-1973. Lacking at that time a complete development of dependency notation, it offered little more than a substitution of rectangular shapes for the familiar distinctive shapes for representing the basic functions of AND, OR, negation, etc. This is no longer the case.Internationally, Working Group 2 of IEC Technical Committee TC-3 has prepared a new document (Publication 617-12) that consolidates the original work started in the mid 1960s and published in 1972 (Publication 117-15) and the amendments and supplements that have followed. Similarly for the USA, IEEE Committee SCC 11.9 has revised the publication IEEE Std 91/ANSI Y32.14. Now numbered simply IEEE Std 91-1984, the IEEE standard contains all of the IEC work that has been approved, and also a small amount of material still under international consideration. Texas Instruments is participating in the work of both organizations and this document introduces new logic symbols in accordance with the new standards. When changes are made as the standards develop, future editions will take those changes into account.The following explanation of the new symbolic language is necessarily brief and greatly condensed from what the standards publications will contain. This is not intended to be sufficient for those people who will be developing symbols for new devices. It is primarily intended to make possible the understanding of the symbols used in various data books, and the comparison of the symbols with logic diagrams, functional block diagrams, and/or function tables will further help that understanding.1The internal (virtual) input is an input originating somewhere else in the circuit and is not connected directly to a terminal. The internal (virtual) output is likewise not connected directly to a terminal. The application of internal inputs and outputs requires an understanding of dependency notation, which is explained in Section 4.In an array of elements, if the same general qualifying symbol and the same qualifying symbols associated with inputs and outputs would appear inside each of the elements of the array, these qualifying symbols usually are shown only in the first element. This is done to reduce clutter and to save time in recognition. Similarly, large identical elements that are subdivided into smaller elements may each be represented by an unsubdivided outline.3.3 Symbols Inside the OutlineTable 3 shows some symbols used inside the outline. Note particularly that open-collector (open-drain), open-emitter (open-source), and 3-state outputs have distinctive symbols. An EN input affects all the external outputs of the element in which it is placed, plus the external outputs of any elements shown to be influenced by that element. It has no effect on inputs. When an enable input affects only certain outputs, affects outputs located outside the indicated influence of the element in which the enable input is placed, and/or affects one or more inputs, a form of dependency notation indicates this (see 4.10). The effects of the EN input on the various types of outputs are shown.It is particularly important to note that a D input is always the data input of a storage element. At its internal 1 state, the D input sets the storage element to its 1 state, and at its internal 0 state it resets the storage element to its 0 state.The binary grouping symbol is explained more fully in Section 8. Binary-weighted inputs are arranged in order and the binary weights of the least-significant and the most-significant lines are indicated by numbers. In this document, weights of input and output lines are represented by powers of two, usually only when the binary grouping symbol is used, otherwise, decimal numbers are used. The grouped inputs generate an internal number on which a mathematical function can be performed or that can be an identifying number for dependency notation (Figure 28). A frequent use is in addresses for memories.Reversed in direction, the binary grouping symbol can be used with outputs. The concept is analogous to that for the inputs, and the weighted outputs indicate the internal number assumed to be developed within the circuit.Other symbols are used inside the outlines in accordance with the IEC/IEEE standards, but are not shown here. Generally, these are associated with arithmetic operations and are self-explanatory.When nonstandardized information is shown inside an outline, it is usually enclosed in square brackets []. The square brackets are omitted when associated with a nonlogic input, which is indicated by an X superimposed on the connection line outside the symbol.64.11 M (Mode) DependencyThe symbol denoting mode dependency is the letter M.Mode dependency is used to indicate that the effects of particular inputs and outputs of an element depend on the mode in which the element is operating.If an input or output has the same effect in different modes of operation, the identifying numbers of the relevant affecting Mm inputs will appear in the label of that affected input or output between parentheses and separated by solidi (Figure 22).4.11.1 M Dependency Affecting InputsM dependency affects inputs the same as C dependency. When an Mm input or Mm output stands at its internal 1 state, the inputs affected by this Mm input or Mm output have their normally defined effect on the function of the element, i.e., the inputs are enabled.When an Mm input or Mm output stands at its internal 0 state, the inputs affected by this Mm input or output have no effect on the function of the element. When an affected input has several sets of labels separated by solidi (e.g., C4/2→/3+), any set in which the identifying number of the Mm input or Mm output appears has no effect and is to be ignored. This represents disabling of some of the functions of a multifunction input.The circuit in Figure 18 has two inputs, b and c , that control which one of four modes (0, 1, 2, or 3) will exist at any time. Inputs d , e , and f are D inputs subject to dynamic control (clocking) by the a input. The numbers 1 and 2 are in the series chosen to indicate the modes so inputs e and f are only enabled in mode 1 (for parallel loading) and input d is only enabled in mode 2 (for serial loading). Note that input a has three functions. It is the clock for entering data. In mode 2, it causes right shifting of data, which means a shift away from the control block. In mode 3, it causes the contents of the register to be incremented by one count.2,4D d a 0b 1c M 031,4D e 1,4DfC4/2→/3+Note that all operations are synchronous.In mode 0 (b = 0, c = 0), the outputs remain at their existing states as none of the inputs has an effect.In mode 1 (b = 1, c = 0), parallel loading takes place through inputs e and f.In mode 2 (b = 0, c = 1), shifting down and serial loading through input d take place.In mode 3 (b = c = 1), counting up by increment of one per clock pulse takes place.Figure 18.M (Mode) Dependency Affecting Inputs4.11.2 M Dependency Affecting OutputsWhen an Mm input or output stands at its internal 1 state, the affected outputs stand at their normally defined internal logic states, i.e., the outputs are enabled.When an Mm input or output stands at its internal 0 state, at each affected output any set of labels containing the identifying number of the Mm input or Mm output has no effect and is to be ignored. When an output has several different sets of labels separated by solidi (e.g., 2,4/3,5), only those sets in which the identifying number of this Mm input or Mm output appears are to be ignored.Figure 19 shows a symbol for a device whose output can behave like either a 3-state output or an open-collector output, depending on the signal applied to input a . Mode 1 exists when input a stands at its internal 1 state and, in that case, the 3-state symbol applies and the open-element symbol has no effect.When a = 0, mode 1 does not exist, so the 3-state symbol has no effect and the open-element symbol applies.Transparent latches have a level-operated control input. The D input is active as long as the C input is at its internal 1 state. The outputs respond immediately. Edge-triggered elements accept data from D, J, K, R, or S inputs on the active transition of C. Pulse-triggered elements require the setup of data before the start of the control pulse; the C input is considered static since the data must be maintained as long as C is at its 1 state. The output is postponed until C returns to its 0 state. The data lock-out element is similar to the pulse-triggered version except that the C input is considered dynamic, in that shortly after C goes through its active transition, the data inputs are disabled and data does not have to be held. However, the output is still postponed until the C input returns to its initial external level.Notice that synchronous inputs can be readily recognized by their dependency labels (1D, 1J, 1K, 1S, 1R) compared to the asynchronous inputs (S, R), which are not dependent on the C inputs.6 CodersThe general symbol for a coder or code converter is shown in Figure 26. X and Y may be replaced by appropriate indications of the code used to represent the information at the inputs and at the outputs, respectively.X/YFigure 26.Coder General SymbolIndication of code conversion is based on the following rule:Depending on the input code, the internal logic states of the inputs determine an internal value. This value is reproduced by the internal logic states of the outputs, depending on the output code.The indication of the relationships between the internal logic states of the inputs and the internal value is accomplished by:beling the inputs with numbers. In this case the internal value equals the sum of the weightsassociated with those inputs that stand at their internal 1 state, or by2.replacing X by an appropriate indication of the input code and labeling the inputs with charactersthat refer to this code.The relationships between the internal value and the internal logic states of the outputs are indicated by:beling each output with a list of numbers representing those internal values that lead to theinternal 1 state of that output. These numbers shall be separated by solidi, as shown in Figure 27.This labeling may also be applied when Y is replaced by a letter denoting a type of dependency (see Section 7). If a continuous range of internal values produces the internal 1 state of an output, this can be indicated by two numbers that are inclusively the beginning and the end of the range, with these two numbers separated by three dots (e.g., 4 . . . 9 = 4/5/6/7/8/9) or by2.replacing Y by an appropriate indication of the output code and labeling the outputs with charactersthat refer to this code, as shown in Figure 28.Alternatively, the general symbol may be used, together with an appropriate reference to a table, in which the relationship between the inputs and outputs is indicated. This is a recommended way to symbolize a PROM after it has been programmed.X/Y1 a2 b4 cd1/4e2/3f3/4g7FUNCTION TABLEc111111b1111a11INPUTS OUTPUTSg11f111e1d10 Figure 27.An X/Y Code ConverterX/OCT1 a2 b4 cd1e2f3g4FUNCTION TABLEc111111b1111a11INPUTSg11f1e1d0 h5i6j7OUTPUTSj1i1h1Figure 28.An X/Octal Code Converter7 Use of a Coder to Produce Affecting InputsIt often occurs that a set of affecting inputs for dependency notation is produced by decoding the signals on certain inputs to an element. In such a case, use can be made of the symbol for a coder as an embedded symbol (Figure 29).X/Y C312G1G210V42N52/3Figure 29.Producing Various Types of DependenciesIf all affecting inputs produced by a coder are of the same type and their identifying numbers are shown at the outputs of the coder, Y (in the qualifying symbol X/Y) may be replaced by the letter denoting the type of dependency. The indications of the affecting inputs should then be omitted (Figure 30).X/M 12102X/Y12M0M110M22≡Figure 30.Producing One Type of Dependency8 Use of Binary Grouping to Produce Affecting InputsIf all affecting inputs produced by a coder are of the same type and have consecutive identifying numbers not necessarily corresponding with the numbers that would have been shown at the outputs of the coder, use can be made of the binary grouping symbol. k external lines effectively generate 2k internal inputs. The bracket is followed by the letter denoting the type of dependency, followed by m1/m2. The m1 is to be replaced by the smallest identifying number and the m2 by the largest one, as shown in Figure 31.X/Y12G5G610G72G83≡01G 58X/YA0A110A22A33≡A 072124A4A554A66A77Figure e of the Binary Grouping Symbol。

For Asus2008.3Outline -1•Introduction to power supplies–Typical power system block diagrams, power supply building blocks –Dc-dc converters (definition, family chart, control and regulation overview)•Dc-dc converter topologies–Nonisolated dc-dc converters•Basic converters (buck, boost, buck-boost)•Derivative converters (two-switch noninverting buck-boost, 2L-2Cconverters)Outline -2•Inductors for DC/DC–Inductor Basics–Typical Inductor Datasheet–Inductor Types and their Characteristics •Capacitors for DC/DC–Capacitors Basics–Typical Capacitors Datasheet–Capacitors Types and their Characteristics •Mosfet for DC/DC–Typical Mosfet Datasheet–Switching waveform–Power Loss estimate•Basic Controller ArchitecturesIntroduction to power suppliesTypical Distributed Line-Powered Power SystemPower Supply of a Desktop ComputerPower Supply System of a Notebook Computer (isolated)Power Supply Building Blocks •Ac-dc interface section–Only for ac-powered supplies•EMI filter•Rectifier/power-factor corrector•Isolated dc-dc converter–Both for ac-powered and dc-powered systems •Nonisolated dc-dc converter–Postregulator in multi-output ac-dc or dc-dc power supplies –Point-of-load (POL) converter in distributed power systemsDefinition of the Dc-dc Converter •The dc-dc converter is an electrical network powered by a dc voltage or current source and capable of supplying dc power to a load at a dc voltage or current level which exceeds that of thesource (i.e., the network shows a net dc voltage or dc currentgain—it is equivalent to a transformer with a BW that extends to dc).•Minimum required number of components for implementing a dc-dc converter–One reactive element (inductor or capacitor)–One switch– A second switch or a diodeDc-dc Converter Family ChartControlling and Regulating Dc-dc Converters •Control techniques–Duty ratio control•Constant-frequency•Variable-frequency (constant on-time [“PFM”], constant off-time, both times vary)•Pulse-skipping, burst-mode, phase-shedding, etc.–Impedance control•Changing impedance by varying the frequency, while maintaining constant duty ratio•Changing an inductance with bias voltage or current–Magnetic amplifier–Linear variable inductor•Regulation techniques–Single-loop negative feedback•Voltage-mode control•Single-loop ripple regulator (simple, enhanced)–Multiple-loop (nested) negative feedback•Current-mode control•Charge control•V2control–Negative feedback combined with feedforward•Input voltage feedforward•Load current feedforwardDc-dc converter topologiesSimplest Practical Nonisolated Dc-dc Converters -1 (one inductor, one capacitor, one switch, one diode)S: control switchD: free-wheeling diodeSimplest Practical Nonisolated Dc-dc Converters -2 (one inductor, one capacitor, two switches)S1: control switchS2: synchronous rectifier switch●Truly synchronous: always “on”when S1 is “off”●Diode emulation: “off”when inductor current reversesOperating Modes of the Dc-dc Converter •Continuous inductor current ( or “continuous conduction”) mode (CCM):–With diode or with a synchronous rectifier that emulates a diode the inductor current is always above zero. With truly synchronous rectifier, the inductorcurrent can cross zero.•Discontinuous inductor current (or :discontinuous conduction”) mode (DCM, requires diode or synchronous rectifier withdiode emulation):–The inductor current decays to zero within each period and stays at zero until the next turn-on of the control switch.General WaveformsDCMTDTD 2T ON OFFONOFFCCMInductor current i L (t)(only with truly synchronous rectifier)DT(1-D)TD 2T TTTDT(1 - D)Tcontrol-switch currentdiode/sync-rectifier currentONOFF ON OFF(1-D)TDT ON OFF ONOFFControl switch voltage v SW (t)ΔI LONOFFON OFFInductor current i L (t)Control switch voltage v SW (t)I pkConverter in CCMConverter in DCMConverter in CCMConverter in DCMTypical Waveforms of the Buck-Boost Converter in CCMConverter in DCMSteady-State Analyses -1•Volt-second balance on the inductor in CCM:or V 1DT + V 2(1 -D)T = 0–buck: V 1= V in -V out V 2= -V out–boost:V 1= V in V 2= V in -V out–buck-boost:V 1= V inV 2= V out•Output-input voltage ratio vs. duty ratio (sometimes called “voltage gain”) is obtained after substituting V 1and V 2in the starting equation and solving it for V out /V in :–buck:V out /V in = D –boost:V out /V in = 1/(1 -D)–buck-boost:V out /V in = -D/(1 -D)∫−=ττtTt Ld v )(Steady-State Analyses -2•Volt-second balance on the inductor in DCM:V 1DT + V 2D 2T = 0(D 2T : fall time of inductor current)•Additional equations–Current fall time:D 2T = -I pk L/V 2–Peak current; charge balance on the output capacitor:•buck:I pk = (V in -V out )DT/L and (D +D 2)I pk /2 = V out /R•boost:I pk = V in DT/L and D 2I pk /2 = V out /R •buck-boost:I pk = V in DT/Land D 2I pk /2 = -V out /RwhereL : inductance, R : load resistance, T : switching period•Output-input voltage ratio vs. duty ratio in DCM; condition for DCM –buck:–boost:–buck-boost:whereSteady-State Analyses -32inoutDK4112V V ++=D1K −<2K D 411V V 2in out ++=2D 1D K )(−<KDV V in out −=()2D 1K −<TR L 2K =M1K −<3M 1M K −<()2M 11K +<or ororandinoutV V M =Output-Input Voltage Ratios in CCM0.10.20.30.40.50.60.70.80.9112345|V out |/V inDBoostBuck-boostBuckBuck Output-Input Voltage Ratio vs. Duty Ratioand vs. Normalized Output Current0.10.20.30.40.50.60.70.80.91V out /V inD00.20.40.60.810.20.30.40.5DCM/CCM limitK = 0.100.050.10.150.20.250.30.20.40.60.81I out L/TV inD = 0.10.20.30.40.50.60.70.80.9V out /V inDCM/CCM limitBoost Output-Input Voltage Ratio vs. Duty Ratio and vs. Normalized Output Current0.020.040.060.080.10.120.14246810I out L/TV inD = 0.1V out /V in0.20.30.40.50.60.70.8DCM/CCM limit0.10.20.30.40.50.60.70.8V out /V inD12345K = 0.04DCM/CCM limit0.080.12CCM DCM/CCM limitBuck-Boost Output-Input Voltage Ratio vs. Duty Ratio and vs. Normalized Output Current0.10.20.30.40.50.60.70.8|V out |/V inD010.162340.320.48K = 0.08DCM/CCM limit00.020.040.060.080.10.120.140.160.1802468100.2I out L/TV in0.1|V out |/V in0.20.30.40.50.60.70.8D = 0.9DCM/CCM limitEffect of the Conduction Losses on the Output Voltage –Buck Converter with FW Diode (CCM)()w out d sw out in out R I D 1V D R I V V −−−−=)(andRV I outout =RR R D R 1D 1V D V V w sw d in out ++−−=)(yieldsVoltage balance equationwith low-ripple approximation←Effect of the Conduction Losses on the Output Voltage –Synchronous Buck Converter in CCM()w out sr out sw out in out R I D 1R I D R I V V −−−−=)(andRV I outout =()RR D 1R R R D R 1DV V wsr sw in out +−−+=yieldsIf R sw = R sr = R sRR R 1DV V w s in out ++=Voltage balance equation with low-ripple approximation←Ringing of the Switched Node in DCMRinging is caused by the parasiticcapacitances of the semiconductordevices. Damping is mostly due to thecore loss of the inductor.Inductor Average and Peak-to-Peak Ripple Currents(CCM)fL V V 1V I I I in out out outL ⎟⎟⎠⎞⎜⎜⎝⎛−=Δ=fL V V 1V I D1I I out in in outL ⎟⎟⎠⎞⎜⎜⎝⎛−=Δ−=fLV V 11V I D1I I outin inout L −=Δ−=Buck:Buck-boost:Boost:I out : output (load) current, f: switching frequency (f = 1/T)Capacitive Output Ripple Voltage of the BuckConverter2T 4I Q Δ=VC Q Δ=C8T I V Δ=Δ•andDTt(1 - D)TT/2ΔIQΔVi C (t)v C (t)Capacitive Output Ripple Voltage of the BoostConverter in CCMoutDTI V CΔ=When ΔI < 2I out (to avoid local maximum during the off time of the switch):-I outDTΔVVoutVoutEffect of the ESR of the Output Capacitor on the Output Ripple Voltage of the Boost ConverterNote: When ΔI < 2I out , the increasing inductor currentripple reduces the peak-to-peak output voltage ripple!I L(pk)I L(vl)I L(pk)ESRI L(vl)ESRout DTI C -I outVoutVoutSummary of Characteristics of the Buck, Boost,and Buck-Boost Converterstrapezoidal or clipped sawtooth triangular or clipped triangulartrapezoidal or clipped sawtooth Input ripple current trapezoidal or clipped sawtoothtrapezoidal or clipped sawtoothtriangular or clipped triangular Output ripple currentyespossiblefloating <>1, inverting Buck-boostyesnot possiblegrounded>1, noninverting Boost nopossiblefloating <1, noninverting Buck Load protect edagainst switch failure?Overload protectio nSwitch position and driveVoltage gain (V out /V in )Convert er typeTwo-Switch Non-InvertingBuck-Boost Converter •There is need for a nonisolatedconverter whose output voltage canbe either lower or higher than theinput voltage and at the same time the two voltages have the same polarity.•None of the three basic converters can do this.•Possible solutions–Isolated (transformer-coupled) converter with common output and input return →extra cost,reduced efficiency–2L-2C (SEPIC or zeta) converter; also cost and efficiency penalty plus other drawbacks –Optimal solution: Connect a buck and boost converter in cascade and eliminate theunnecessary components →two-switchnoninverting buck-boost converterCharacteristics•Voltage gain (in CCM; from the voltage balance of the inductor)D 1Vin= (1 –D2) Vout→Vout/Vin= D1/(1 –D2)i.e. Vout is either smaller or larger than Vin; polarity is the same•Control–Unison control: Gain (V out/V in) and dynamics are the same as those of the single-switch buck-boost converter (except for the sign of gain)–Buck-type control (D2= 0): Gain, waveforms, and dynamics same as those of the buck converter–Boost-type control (D1= 1): Gain, waveforms, and dynamics same as those of the boost converter•Efficiency–Two semiconductors conduct at the same time →increased conduction losses compared to the standard buck or boost converter–Buck mode or boost mode: Higher efficiency than in buck-boost mode due to reduced switching losses and reduced rms currents2L-2C Converter Topologies2L-2C buck 2L-2C boost 2L-2C buck-boost CukSEPICzetaV out < 0V inV inV inV inV inV inV in > V out > 0V out > V inV out < 0V out > 0V out > 0C cCRL 1L 2C c L 1L 2CRC c L 1L 2CRL 1L 1L 1L 2L 2L 2C cC c C c CRC RCRComments• • The coupling capacitor CC forces equal voltages on the two inductors. The 2L-2C buck, boost and buck-boost converters are not practical (no difference in stresses or waveforms from the parent converters, but more components). The Cuk, SEPIC and zeta converters have some practical value, however. The Cuk, SEPIC and zeta converters are related to the buck-boost converter. – – •Voltage gain in CCM: |Vout/Vin| = D/(1 − D)•Maximum switch stresses and power-processing capability: same as those of the buck-boost.Four reactive components and RHP (right-hand plane) zero in CCM → difficult to compensate the feedback loop for wide bandwidth Cuk: ground-referenced switch, nonpulsating input and output currents, inverted output SEPIC: ground-referenced switch, nonpulsating input current, noninverted output Zeta: floating switch, nonpulsating output current, noninverted output The two windings can be magnetically coupled (by placing them on the same core) → fewer components (size and cost saving), and also other benefits.• • • •41Confidential proprietaryCorp Pres/tm • May-07Inductors for DC-DC’s42Confidential proprietaryCorp Pres/tm • May-07Inductor Basics (1)• An inductor is a magnetic energy storage element which consists of a conducting coil surrounding a core, usually made of ferrite material• • • • • • • Air µ = 1.257x10-6 H/m Ferrite U M33 µ = 9.42x10-4 H/m Nickel µ = 7.54x10-4 H/m Iron µ = 6.28x10-3 H/m Ferrite T38 µ = 1.26x10-2 H/m Silicon GO steel µ = 5.03x10-2 H/m supermalloy µ = 1.26 H/mL( Henries) =μ ⋅n ⋅ A2µ = permeability of core, n = number of turns, A = cross-sectional area of core, l = effective length of core43Confidential proprietaryl• Larger core cross-sectional area, coil turns, permeability increase inductanceCorp Pres/tm • May-07Inductor Basics (2)I(L), AVLt, secondsdi V = dt L1 E ( joules) = ⋅ L ⋅ I 2 2• Inductor current increases at rate of V/L • If inductor current changes rapidly (inductor shorted), a large voltage will be generated • Energy stored is related to current and inductance44Confidential proprietaryCorp Pres/tm • May-07STEP-DOWNInput CurrentInductors in DC-DC’sSTEP-UPOutputOn-TimeLoadInputOutputOff-TimeCurrentLoadVOUT (VIN − VOUT ) ΔI L = ⋅ VIN fsw ⋅ L• • •45VIN (VOUT − VIN ) ΔI L = ⋅ VOUT fsw ⋅ L– –Increasing fsw, reduces ripple current for same VIN/VOUT conditions Higher fsw = smaller value inductor = smaller physical inductor, and lower DCR Use ΔI ≈ 0.3 IDC (Buck Iload, Boost Iin) as starting point –size vs. efficiency trade-offCorp Pres/tm • May-07However switching losses degrade efficiencyConfidential proprietaryTypical Inductor Datasheet (1) – What do specifications mean ?Part number DO3316P-682_L_ DO3316P-103_L_ DCR 2 SRF 5 4 L1 Percent max typ I sat I rms (µH) tol (Ohms) (MHz) (A) (A) 6.8 20,10 10 20,10 20 0.027 0.038 38 30 4.6 3.8 4.4 3.931. 2. 3. 4. 5.‹ Typically you don’t want to have inductor rising much more than 40˚C as saturation current level is further decreased.Inductances may vary 20-30% from the desired inductor value ! Current ripple could be increased 43 %. Coilcraft offer 10 and 20% tolerance. DCR – This is the DC resistance. Smaller inductors will have larger DCR due to reduced wire thickness. Efficiency loss. SRF – This is the resonant frequency of inductor and parasitic capacitance of inductor – typically not a concern for design ISAT – This is the inductor current level, for which the inductance falls 10% using coilcraft – for others it is -30% ! You don’t want to operate at -30% (-10% is OK) IRMS (Also called IMAX) – At this RMS current level the temperature of the inductor will rise 40˚C. Inductors are usually rated to 125C,46Confidential proprietaryCorp Pres/tm • May-07Saturation of Inductors12 107 6Current LimitInductor Current (A)6L (µH)8 65 4 3 2 1 0 0 1 2 3 4 5+85C4 2 0 0 1 2 3 4-40C5Current (Adc)Switc hing Cyc les• •The inductor core can become biased with too much current resulting in a sudden drop in inductance Operating IDC + ΔI / 2 at ISAT = L -30% will cause issues– – – – L = L -30%, ΔI / 2 = 1/0.7, Increase in ripple of > 40% May hit current limit for lower DC current than desired Core saturation results in core efficiency loss Greater di / dt results in increased EMI leakage•Over designing will result in physically large inductors– 10% Saturation for peak current, at max load and worst case conditions is a reasonable compromise – Check Inductor saturation curves vs. temperature – Don’t just read spec !Corp Pres/tm • May-0747Confidential proprietaryInductor Types and their CharacteristicsFerrite Core – Saturates quicklyIron Powder Core – Saturating Gradually• Natural air gaps in powdered iron core cause a more gradual saturation curve for same physical size • Suited to applications requiring large instantaneous current (i.e. camera flash, VRM power supplies) • More expensive, and higher core losses48Confidential proprietaryCorp Pres/tm • May-07Inductor Power 2Loss Model (1)PDISSDCR PDISS ≈ IDC2 · RDCR Usually Dominant L RCORE⎛ ΔI ⎞ =⎜ ⎟ ⋅ RAC ⎝ 2 RMS ⎠ACRPDISS = k ⋅ f x ⋅ B y ⋅ VCOREk = Core Loss Constant, F = Frequency (kHz) B= Peak Flux Density, kG (V*ΔT) * k1 V = Volume of Core (cm3)To calculate core loss use online tool: /apps/loss/loss_1.cfm49Confidential proprietaryCorp Pres/tm • May-07Shielded or Unshielded ?• Shielded inductors reduce EMI and potential interference– RF designs almost always use shielded inductors• Manufacturing cost is higher • Current rating per mm2 is reducedModel DO5022P-103ML_ DS5022P-103ML_ L, μH 10 10 DCR, Ω 0.031 0.04 SRF, MHz 30 30 ISAT, A 10 8 IRMS, A 4.3 3.9 Shielded Size, mm Price, $ 1k No 18 x 15 0.73 Yes 18 x 15 1.1150Confidential proprietaryCorp Pres/tm • May-07。

The AMC1200 and AMC1200B are fully specified over the extended industrial temperature range of –40°C to +105°C and are available in a wide-body SOIC-8 package (DWV) and a gullwing-8 package (DUB).
2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1
•2 ±250-mV Input Voltage Range Optimized for Shunt Resistors
• Very Low Nonlinearity: 0.075% max at 5 V • Low Offset Error: 1.5 mV max • Low Noise: 3.1 mVRMS typ • Low High-Side Supply Current:
Copyright © 2011–2013, Texas Instruments Incorporated
AMC1200 AMC1200B
SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

V(50 mV/div)OUTI(1A/div)OUT100s/divμG006TPS54329 SLVSAZ6A–SEPTEMBER2011–REVISED MARCH20124.5V to18V Input,3-A SYNCHRONOUS STEP DOWN CONVERTERCheck for Samples:TPS54329FEATURES DESCRIPTIONThe TPS54329is an adaptive on-time D-CAP2™•D-CAP2™Mode Enables Fast Transientmode synchronous buck converter.TheTPS54329 Responseenables system designers to complete the suite of •Low Output Ripple and Allows Ceramic Output various end equipment’s power bus regulators with a Capacitor cost effective,low component count,low standbycurrent solution.The main control loop for the •Wide V IN Input Voltage Range:4.5V to18VTPS54329uses the D-CAP2™mode control which •Output Voltage Range:0.76V to7.0Vprovides a fast transient response with no external •Highly Efficient Integrated FETs Optimized compensation components.The TPS54329also has for Lower Duty Cycle Applications a proprietary circuit that enables the device to adopt –100mΩ(High Side)and74mΩ(Low Side)to both low equivalent series resistance(ESR)outputcapacitors,such as POSCAP or SP-CAP,and ultra-•High Efficiency,Less Than10μA at Shutdownlow ESR ceramic capacitors.The device operates •High Initial Bandgap Reference Accuracyfrom4.5-V to18-V VIN input.The output voltage can •Adjustable Soft Start be programmed between0.76V and7V.The devicealso features an adjustable soft start time.The •Pre-Biased Soft StartTPS54329is available in the8-pin DDA package,•650-kHz Switching Frequency(f SW)and designed to operate from–40°C to85°C.•Cycle By Cycle Over Current LimitAPPLICATIONS•Wide Range of Applications for Low VoltageSystem–Digital TV Power Supply–High Definition Blu-ray Disc™Players–Networking Home Terminal–Digital Set Top Box(STB)Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.is a trademark of Texas Instruments.Blu-ray Disc is a trademark of Blu-ray Disc Association.PRODUCTION DATA information is current as of publication date.Copyright©2011–2012,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TPS54329SLVSAZ6A–SEPTEMBER2011–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled withappropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.ORDERING INFORMATION(1)TRANSPORT T A PACKAGE(2)(3)ORDERABLE PART NUMBER PINMEDIATPS54329DDA Tube –40°C to85°C DDA8TPS54329DDAR Tape and Reel(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.(3)All package options have Cu NIPDAU lead/ball finish.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)VALUEUNITMIN MAXVIN,EN–0.320VVBST–0.326VVBST(10ns transient)–0.328VInput voltage range VBST(vs SW)–0.3 6.5V VFB,SS–0.3 6.5VSW–220VSW(10ns transient)–322VVREG5–0.3 6.5V Output voltage rangeGND–0.30.3V Voltage from GND to thermal pad,V diff–0.20.2V Human Body Model(HBM)2kV Electrostatic dischargeCharged Device Model(CDM)500V Operating junction temperature,T J–40150°C Storage temperature,T stg–55150°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.THERMAL INFORMATIONTPS54329THERMAL METRIC UNITSDDA(8PINS)θJA Junction-to-ambient thermal resistance42.1θJCtop Junction-to-case(top)thermal resistance50.9θJB Junction-to-board thermal resistance31.8°C/WψJT Junction-to-top characterization parameter5ψJB Junction-to-board characterization parameter13.5θJCbot Junction-to-case(bottom)thermal resistance7.12Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):TPS54329TPS54329 SLVSAZ6A–SEPTEMBER2011–REVISED MARCH2012RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN MAX UNITV IN Supply input voltage range 4.518VVBST–0.124VBST(10ns transient)-0.127VBST(vs SW)–0.1 5.7SS–0.1 5.7V I Input voltage range EN–0.118VVFB–0.1 5.5SW–1.818SW(10ns transient)–321GND–0.10.1V O Output voltage range VREG5–0.1 5.7VI O Output Current range I VREG5010mAT A Operating free-air temperature–4085°CT J Operating junction temperature–40150°CELECTRICAL CHARACTERISTICSover operating free-air temperature range,V IN=12V(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENTV IN current,T A=25°C,EN=5V,I VIN Operating-non-switching supply current8001200μAV FB=0.8VI VINSDN Shutdown supply current V IN current,T A=25°C,EN=0V 4.310μA LOGIC THRESHOLDV ENH EN high-level input voltage EN 1.6VV ENL EN low-level input voltage EN0.45VR EN EN pin resistance to GND V EN=12V220440880kΩV FB VOLTAGE AND DISCHARGE RESISTANCEV FBTH V FB threshold voltage T A=25°C,V O=1.05V,continuous mode749765781mVI VFB V FB input current V FB=0.8V,T A=25°C0±0.1μAV REG5OUTPUTT A=25°C,6.0V<V IN<18V,V VREG5V REG5output voltage 5.5V0<I VREG5<5mAI VREG5Output current V IN=6V,V REG5=4.0V,T A=25°C(1)60mA MOSFETR DS(on)h High side switch resistance25°C,V BST-SW=5.5V(1)100mΩR DS(on)l Low side switch resistance25°C(1)74mΩCURRENT LIMITI ocl Current limit L out=1.5μH(1) 3.5 4.2 5.7A(1)Not production tested.Copyright©2011–2012,Texas Instruments Incorporated3Product Folder Link(s):TPS54329TPS54329SLVSAZ6A–SEPTEMBER2011–REVISED ELECTRICAL CHARACTERISTICS(continued)over operating free-air temperature range,V IN=12V(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWNShutdown temperature(2)165T SDN Thermal shutdown threshold°CHysteresis(2)35ON-TIME TIMER CONTROLt ON On time V IN=12V,V O=1.05V150nst OFF(MIN)Minimum off time T A=25°C,V FB=0.7V(2)260ns SOFT STARTI SSC SS charge current V SS=1V 4.2 6.07.8μAI SSD SS discharge current V SS=0.5V0.10.2mA UVLOWake up V REG5voltage 3.75UVLO UVLO threshold VHysteresis V REG5voltage0.33(2)Not production tested.4Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):TPS54329TPS54329 SLVSAZ6A–SEPTEMBER2011–REVISED MARCH2012DEVICE INFORMATIONDDA PACKAGE(TOP VIEW)PIN FUNCTIONSPINDESCRIPTIONNAME NO.Supply input for the high-side FET gate drive circuit.Connect0.1µF capacitor between VBST and SW VBST1pins.An internal diode is connected between VREG5and VBST.VIN2Input voltage supply pin.SW3Switch node connection between high-side NFET and low-side NFET.Ground pin.Power ground return for switching circuit.Connect sensitive SS and VFB returns to GND at GND4a single point.VFB5Converter feedback input.Connect to output voltage with feedback resistor divider.5.5V power supply output.A capacitor(typical0.47µF)should be connected to GND.VREG5is not VREG56active when EN is low.EN7Enable input control.EN is active high and must be pulled up to enable the device.SS8Soft-start control.An external capacitor should be connected to GND.Exposed Thermal Thermal pad of the package.Must be soldered to achieve appropriate dissipation.Must be connected to Back sidePad GND.Copyright©2011–2012,Texas Instruments Incorporated5Product Folder Link(s):TPS54329TPS54329SLVSAZ6A–SEPTEMBER2011–REVISED FUNCTIONAL BLOCK DIAGRAM6Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):TPS54329(nF)x V (nF)x 0.765 1.1REF SS SS t (ms)==SS I (A)SSC 1.1C 6´m ´TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012OVERVIEWThe TPS54329is a 3-A synchronous step-down (buck)converter with two integrated N-channel MOSFETs.It operates using D-CAP2™mode control.The fast transient response of D-CAP2™control reduces the output capacitance required to meet a specific level of performance.Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.DETAILED DESCRIPTIONPWM OperationThe main control loop of the TPS54329is an adaptive on-time pulse width modulation (PWM)controller that supports a proprietary D-CAP2™mode control.D-CAP2™mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors.It is stable even with virtually no ripple at the output.At the beginning of each cycle,the high-side MOSFET is turned on.This MOSFET is turned off after internal one shot timer expires.This one shot is set by the converter input voltage,VIN,and the output voltage,VO,to maintain a pseudo-fixed frequency over the input voltage range,hence it is called adaptive on-time control.The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage.An internal ramp is added to reference voltage to simulate output ripple,eliminating the need for ESR induced output ripple from D-CAP2™mode control.PWM Frequency and Adaptive On-Time ControlTPS54329uses an adaptive on-time control scheme and does not have a dedicated on board oscillator.The TPS54329runs with a pseudo-constant frequency of 650kHz by using the input voltage and output voltage to set the on-time one-shot timer.The on-time is inversely proportional to the input voltage and proportional to the output voltage,therefore,when the duty ratio is VOUT/VIN,the frequency is constant.Soft Start and Pre-Biased Soft StartThe soft start function is adjustable.When the EN pin becomes high,6μA current begins charging the capacitor which is connected from the SS pin to GND.Smooth control of the output voltage is maintained during start up.The equation for the slow start time is shown in Equation 1.VFB voltage is 0.765V and SS pin source current is 6μA.(1)The TPS54329contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased.When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage V FB ),the controller slowly activates synchronous rectification by starting the first low side FET gate driver pulses with a narrow on-time.It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D),where D is the duty cycle of the converter.This scheme prevents the initial sinking of the pre-bias output,and ensure that the out voltage (VO)starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.Current ProtectionThe output overcurrent protection (OCP)is implemented using a cycle-by-cycle valley detect control circuit.The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND.This voltage is proportional to the switch current.To improve accuracy,the voltage sensing is temperature compensated.During the on time of the high-side FET switch,the switch current increases at a linear rate determined by Vin,Vout,the on-time and the output inductor value.During the on time of the low-side FET switch,this current decreases linearly.The average value of the switch current is the load current I OUT .The TPS54329constantly monitors the low-side FET switch voltage,which is proportional to the switch current,during the low-side on-time.If the measured voltage is above the voltage proportional to the current limit,an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switchingCopyright ©2011–2012,Texas Instruments Incorporated7Product Folder Link(s):TPS54329TPS54329SLVSAZ6A–SEPTEMBER2011–REVISED cycle begins.In subsequent switching cycles,the on-time is set to a fixed value and the current is monitored in the same manner.If the over current condition exists for7consecutive switching cycles,the internal OCL threshold is set to a lower level,reducing the available output current.When a switching cycle occurs where the switch current is not above the lower OCL threshold,the counter is reset and the OCL limit is returned to the higher value.There are some important considerations for this type of over-current protection.The load current one half of the peak-to-peak inductor current higher than the over-current threshold.Also when the current is being limited,the output voltage tends to fall as the demanded load current may be higher than the current available from the converter.This may cause the output voltage to fall.When the over current condition is removed,the output voltage will return to the regulated value.This protection is non-latching.UVLO ProtectionUndervoltage lock out protection(UVLO)monitors the voltage of the V REG5pin.When the V REG5voltage is lower than UVLO threshold voltage,the TPS54329is shut off.This is protection is non-latching.Thermal ShutdownTPS54329monitors the temperature of itself.If the temperature exceeds the threshold value(typically165°C), the device is shut off.This is non-latch protection.8Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):TPS54329020040060080010001200Junction Temperature (°C)S u p p l y C u r r e n t (µA )G0010246810121416Junction Temperature (°C)S h u t d o w n C u r r e n t (µA )G00205101520253035404550EN Input Voltage (V)E N I n p u t C u r r e n t (µA )G0031.031.041.051.061.07Output Current (A)O u t p u t V o l t a g e (V )G004V (50 mV/div)OUT I (1A/div)OUT 100s/divμG0061.031.041.051.061.07Input Voltage (V)O u t p u t V o l t a g e (V )G005TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012TYPICAL CHARACTERISTICSV IN =12V,T A =25°C (unless otherwise noted).Figure 1.VIN CURRENT vs JUNCTION TEMPERATUREFigure 2.VIN SHUTDOWN CURRENT vsJUNCTION TEMPERATUREFigure 3.EN CURRENT vs EN VOLTAGEFigure 4.1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENTFigure 5.1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGEFigure 6.1.05-V,50-mA to 2-A LOAD TRANSIENTRESPONSECopyright ©2011–2012,Texas Instruments Incorporated 9Product Folder Link(s):TPS54329400 µs/divG007V (0.5 V/div)OUT EN (10 V/div)VREG5 (5 V/div)405060708090100E f f i c i e n c y (%)400450500550600650700750800850900Input Voltage (V)S w i t c h i n g F r e q u e n c y (k H z )G009400450500550600650700750800850900Output Current (A)S w i t c h i n g F r e q u e n c y (k H z )G010G012400 ns/divV = 1.05 VOUT SW (5 V/div)V (10 mV/div)OUT 0.7500.7550.7600.7650.7700.7750.780Junction Temperature (°C)V F B V o l t a g e (V )G011TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012TYPICAL CHARACTERISTICSV IN =12V,T A =25°C (unless otherwise noted).Figure 7.START-UP WAVE FORMFigure 8.EFFICIENCY vs OUTPUT CURRENTFigure 9.SWITCHING FREQUENCY vs INPUT VOLTAGEFigure 10.SWITCHING FREQUENCY vsOUTPUT CURRENTFigure 11.Vfb VOLTAGE vs JUNCTION TEMPERATUREFigure 12.VOLTAGE RIPPLE AT OUTPUT (I O =3A)10Copyright ©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):TPS54329G013400 ns/divV = 1.05 VOUT SW (5 V/div)V (50 mV/div)IN TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012TYPICAL CHARACTERISTICSV IN =12V,T A =25°C (unless otherwise noted).Figure 13.VOLTAGE RIPPLE AT INPUT (I O =3A)V =0.765x OUTR11+R2æö÷ç÷ç÷çèøF =P TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012DESIGN GUIDEStep By Step Design Procedure To begin the design process,you must know a few application parameters:•Input voltage range •Output voltage •Output current•Output voltage ripple •Input voltage rippleFigure 14.Shows the schematic diagram for this design example.Output Voltage Resistors SelectionThe output voltage is set with a resistor divider from the output node to the VFB pin.It is recommended to use 1%tolerance or better divider resistors.Start by using Equation 2to calculate V OUT .To improve efficiency at very light loads consider using larger value resistors,too high of resistance will be more susceptible to noise and voltage errors from the VFB input current will be more noticeable.(2)Output Filter SelectionThe output filter used with the TPS54329is an LC circuit.This LC filter has double pole at:(3)At low frequencies,the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54329.The low frequency phase is 180degrees.At the output filter pole frequency,the gain rolls off at a –40dB per decade rate and the phase drops rapidly.D-CAP2™introduces a high frequency zero that reduces the gain roll off to –20dB per decade and increases the phase to 90degrees one decade above the zero frequency.The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit.To meet this requirement use the values recommended in Table 1V V V IN(max)OUT OUT =xIPP V L x IN(max)O SW-I f lpp =+Ipeak O 2I II =Lo(RMS)I=Co(RMS)ITPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012Table 1.Recommended Component ValuesOutput Voltage (V)R1(k Ω)R2(k Ω)C4(pF)(1)L1(µH)C8+C9+C10(µF)1 6.8122.1 1.520-681.058.2522.1 1.520-681.212.722.1 1.520-681.521.522.1 1.520-681.830.122.15-22 2.220-682.549.922.15-22 2.220-683.373.222.15-22 2.220-68512422.15-22 3.320-686.516522.15-22 3.320-68(1)OptionalSince the DC gain is dependent on the output voltage,the required inductor value will increase as the output voltage increases.For higher output voltages at or above 1.8V,additional phase boost can be achieved by adding a feed forward capacitor (C4)in parallel with R1The inductor peak-to-peak ripple current,peak current and RMS current are calculated using Equation 4,Equation 5and Equation 6.The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS e 650kHz for f SW .Make sure the chosen inductor is rated for the peak current of Equation 5and the RMS current of Equation 6.(4)(5)(6)For this design example,the calculated peak current is 3.49A and the calculated RMS current is 3.01A.Theinductor used is a TDK CLF7045T-1R5M with a peak current rating of 7.3A and an RMS current rating of 4.9A.The capacitor value and ESR determines the amount of output voltage ripple.The TPS54329is intended for use with ceramic or other low ESR capacitors.Recommended values range from 20µF to 68µe Equation 7to determine the required RMS current rating for the output capacitor.(7)For this design three TDK C3216X5R0J106M 10µF output capacitors are used.The typical ESR is 2m Ωeach.The calculated RMS current is 0.284A and each output capacitor is rated for 4A.Input Capacitor SelectionThe TPS54229requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.A ceramic capacitor over 10μF is recommended for the decoupling capacitor.An additional 0.1µF capacitor (C3)is required to provide additional high frequency filtering and insure accurate current limit operation.This capacitor must be placed as close to the IC pins 2(VIN)and 4(GND)as possible.The capacitor voltage rating needs to be greater than the maximum input voltage.Bootstrap Capacitor SelectionA 0.1µF.ceramic capacitor must be connected between the VBST to SW pin for proper operation.It is recommended to use a ceramic capacitor.TPS54329SLVSAZ6A–SEPTEMBER2011–REVISED VREG5Capacitor SelectionA0.47µF.ceramic capacitor must be connected between the VREG5to GND pin for proper operation.It is recommended to use a ceramic capacitor.THERMAL INFORMATIONThis8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heartsick.The thermal pad must be soldered directly to the printed board(PCB).After soldering,the PCB can be used as a heartsick.In addition,through the use of thermal vias,the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device,or alternatively,can be attached to a special heartsick structure designed into the PCB.This design optimizes the heat transfer from the integrated circuit(IC).For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities,refer to Technical Brief,PowerPAD™Thermally Enhanced Package,Texas Instruments Literature No. SLMA002and Application Brief,PowerPAD™Made Easy,Texas Instruments Literature No.SLMA004.The exposed thermal pad dimensions for this package are shown in the following illustration.Figure15.Thermal Pad Dimensions(Top View)TPS54329 SLVSAZ6A–SEPTEMBER2011–REVISED MARCH2012LAYOUT CONSIDERATIONS1.Keep the input switching current loop as small as possible.2.Keep the SW node as physically small and short as possible to minimize parasitic capacitance andinductance and to minimize radiated emissions.Kelvin connections should be brought from the output to the feedback pin of the device.3.Keep analog and non-switching components away from switching components.4.Make a single point connection from the signal ground to power ground.5.Do not allow switching current to flow under the device.6.Keep the pattern lines for VIN and PGND broad.7.Exposed pad of device must be connected to PGND with solder.8.VREG5capacitor should be placed near the device,and connected PGND.9.Output capacitor should be connected to a broad pattern of the PGND.10.Voltage feedback loop should be as short as possible,and preferably with ground shield.11.Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog groundtrace.12.Providing sufficient vias for VIN,SW and PGND connection.13.VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible tothe device.14.Performance based on four layer printed circuit board.VIA to Power Ground PlaneVIN TPS54329SLVSAZ6A –SEPTEMBER 2011–REVISED MARCH 2012Figure 16.PCB LayoutTPS54329 SLVSAZ6A–SEPTEMBER2011–REVISED MARCH2012REVISION HISTORYChanges from Original(September2011)to Revision A Page•Removed(SWIFT™)from the data sheet title (1)•Deleted from ELECTRICAL CHARACTERISTICS table,V LN5and V LD5,deleted V VREG5MIN and MAX values (3)•Added in ELECTRICAL CHARACTERISTICS table,I VREG5,R DS(on)h,and R DS(on)l footnote references (3)•Added t OFF(MIN)footnote reference and deleted MAX value (4)•Deleted from ELECTRICAL CHARARACTERISTICS,UVLO MIN and MAX values (4)•Added TYPICAL CHARACTERISTICS Condition (9)PACKAGE OPTION ADDENDUM18-May-2012Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawing Pins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)Samples (Requires Login)TPS54329DDA ACTIVE SO PowerPAD DDA 875Green (RoHS & no Sb/Br)CU NIPDAUAGLevel-2-260C-1 YEARTPS54329DDARACTIVESO PowerPADDDA82500Green (RoHS & no Sb/Br)Call TILevel-2-260C-1 YEAR(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3)MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.。