CY74FCT541TQSOP中文资料

The IDT54/74FCT138T/AT/CT are 1-of-8 decoders built using an advanced dual metal CMOS technology. The IDT54/74FCT138T/AT/CT accepts three binary weighted inputs (A 0,A 1, A 2) and, when enabled, provides eight mutually exclusive active LOW outputs (O 0-O 7). The IDT54/74FCT138T/AT/CT features three enable inputs, two active LOW (E 1, E 2) and one active HIGH (E 3). All outputs will be HIGH unless E 1 and E 2 are LOW and E 3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four IDT54/74FCT138T/AT/CT devices and one inverter.FUNCTIONAL BLOCK DIAGRAM2570 drw 012570 drw 022570 drw 03PIN CONFIGURATIONSO 6O 2LCC TOP VIEWO 1NC O 3O 4O 7O 5G N D N CMILITARY AND COMMERCIAL TEMPERATURE RANGESAPRIL 1995O 7O 6O 5O 4O 3O 2O 1O 0A 2A 1A 0E 1E 2E 3GNDA 0O 0O 6V CC DIP/SOIC/QSOP/CERPACKTOP VIEWA 1A 2E 1E 2E 37O 1O 2O 3O 4O 5•Std., A and C speed grades•Low input and output leakage ≤1µA (max.)•CMOS power levels•True TTL input and output compatibility – V OH = 3.3V (typ.)– V OL = 0.3V (typ.)•High drive outputs (-15mA I OH , 48mA I OL )•Meets or exceeds JEDEC standard 18 specifications •Product available in Radiation Tolerant and Radiation Enhanced versions•Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)•Available in DIP, SOIC, QSOP, CERPACK and LCC packagesThe IDT logo is a registered trademark of Integrated Device Technology, Inc.FUNCTION TABLE2570 tbl 02(1)2570 tbl 011.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed V CC by +0.5V unless otherwise noted.2.Input and V CC terminals only.3.Outputs and I/O terminals only.1. This parameter is measured at characterization but not tested.DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGEFollowing Conditions Apply Unless Otherwise Specified:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at V CC = 5.0V, +25°C ambient.3.Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.4.The test limit for this parameter is ±5µA at T A = –55°C.1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at V CC = 5.0V, +25°C ambient.3.Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND.4.This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.5.Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested.6.I C = I QUIESCENT + I INPUTS + I DYNAMICI C = I CC + ∆I CC D H N T + I CCD (f o N o)I CC = Quiescent Current∆I CC = Power Supply Current for a TTL High Input (V IN = 3.4V)D H = Duty Cycle for TTL Inputs HighN T = Number of TTL Inputs at D HI CCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)f o = Output FrequencyN o = Number of Outputs at f oAll currents are in milliamps and all frequencies are in megahertz.2570 tbl 071.See test circuit and waveforms.2.Minimum limits are guaranteed but not tested on Propagation Delays.TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTSENABLE AND DISABLE TIMESPROPAGATION DELAY7.0V3V 1.5V 0V3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUTPRESET CLEAR ETC.1.5V1.5VSAME PHASE INPUT TRANSITION3V 1.5V 0V 1.5V V OH OUTPUTOPPOSITE PHASE INPUT TRANSITION3V 1.5V 0VV OL 3V1.5V 0V 3.5V 0VV OLENABLEDISABLEV OH PRESET CLEARCLOCK ENABLEETC.SET-UP, HOLD AND RELEASE TIMES PULSE WIDTHC L =Load capacitance: includes jig and probe capacitance.R T =Termination resistance: should be equal to Z OUT of the PulseGenerator.2570 drw 042570 drw 062570 drw 052570 drw 08NOTES:1.Diagram shown for input Control Enable-LOW and input Control Disable-HIGH2.Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t F ≤ 2.5ns; t R ≤ 2.5ns2570 drw 07ORDERING INFORMATIONIDT XX FCT138T138AT138CT1-of-8 Decoder54 74–55°C to +125°C 0°C to +70°CTemp. RangeXXXXDevice TypeXPackageXProcessBlankBPDSOELQCommercialMIL-STD-883, Class BPlastic DIPCERDIPSmall Outline ICCERPACKLeadless Chip CarrierQuarter-size Small Outline Package XFamilyBlankHigh Drive2570 drw 09。

The FCT16374T/AT/CT/ET and FCT162374T/AT/CT/ET 16-bit edge-triggered D-type registers are built using ad-vanced dual metal CMOS technology. These high-speed,low-power registers are ideal for use as buffer registers for data synchronization and storage. The Output Enable (x OE )and clock (xCLK) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins sim-plifies layout. All inputs are designed with hysteresis for improved noise margin.The FCT16374T/AT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.The FCT162374T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce,minimal undershoot, and controlled output fall times– reduc-ing the need for external series terminating resistors. The FCT162374T/AT/CT/ET are plug-in replacements for the FCT16374T/AT/CT/ET and ABT16374 for on-board bus inter-face applications.FUNCTIONAL BLOCK DIAGRAM1O 111CLK 1D 12542 drw 01O 122CLK2D 1TO 7 OTHER CHANNELS2542 drw 01The IDT logo is a registered trademark of Integrated Device Technology, Inc.MILITARY AND INDUSTRIAL TEMPERATURE RANGES FEBRUARY 1997•Common features:–0.5 MICRON CMOS Technology–High-speed, low-power CMOS replacement for ABT functions–Typical t SK (o) (Output Skew) < 250ps–Low input and output leakage ≤1µA (max.)–ESD > 2000V per MIL-STD-883, Method 3015;> 200V using machine model (C = 200pF, R = 0)–Packages include 25 mil pitch SSOP, 19.6 mil pitchTSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack –Extended commercial range of -40°C to +85°C –V CC = 5V ±10%•Features for FCT16374T/AT/CT/ET:–High drive outputs (-32mA I OH , 64mA I OL )–Power off disable outputs permit “live insertion”–Typical V OLP (Output Ground Bounce) < 1.0V at V CC = 5V, T A = 25°C•Features for FCT162374T/AT/CT/ET:–Balanced Output Drivers:±24mA (commercial),±16mA (military)–Reduced system switching noise–Typical V OLP (Output Ground Bounce) < 0.6V at V CC = 5V,T A = 25°CPIN CONFIGURATIONS1O 1GND1O 3V CC1OE GND2O 2GNDV CCGND1O 21O 41O 51O 61O 71O 82O 12O 32O 42O 52O 72O 82O 62OE1CLK 1D 11D 2GND1D 31D 4V CC1D 51D 61D 71D 82D 12D 22D 32D 4V CC2D 52D 72D 82D 62CLKGNDGNDGND2542 drw 04CERPACK TOP VIEW1O 1GND1O 3V CC1OE GND2O 2GNDV CCGND1O 21O 41O 51O 61O 71O 82O 12O 32O 42O 52O 72O 82O 621CLK 1D 11D 2GND1D 31D 4V CC1D 51D 61D 71D 82D 12D 22D 32D 4V CC2D 52D 72D 82D 62CLKGNDGNDGND2542 drw 03SSOP/TSSOP/TVSOP TOP VIEWPIN DESCRIPTIONFUNCTION TABLE (1)(1)CAPACITANCE (T A = +25°C, f = 1.0MHz)2542 tbl 02NOTE:1. This parameter is measured at characterization but not tested.2542 lnk 041.H = HIGH Voltage Level L = LOW Voltage Level X = Don’t CareZ = High Impedance↑ = LOW-to-HIGH TransitionNOTES:1.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2.All device terminals except FCT162XXXT Output and I/O terminals.3.Output and I/O terminals for FCT162XXXT.2542 lnk 03DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGEFollowing Conditions Apply Unless Otherwise Specified:NOTES:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at Vcc = 5.0V, +25°C ambient.3.Not more than one output should be tested at one time. Duration of the test should not exceed one second.4.Duration of the condition can not exceed one second.5.The test limit for this parameter is ± 5µA at T A = –55°C.NOTES:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at V CC = 5.0V, +25°C ambient.3.Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND.4.This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.5.Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested.6.I C = I QUIESCENT + I INPUTS + I DYNAMICI C = I CC + ∆I CC D H N T + I CCD (f CP N CP/2 + f i N i)I CC = Quiescent Current (I CCL, I CCH and I CCZ)∆I CC = Power Supply Current for a TTL High Input (V IN = 3.4V)D H = Duty Cycle for TTL Inputs HighN T = Number of TTL Inputs at D HI CCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)f CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)N CP = Number of Clock Inputs at f CPf i = Input FrequencyN i = Number of Inputs at f iSWITCHING CHARACTERISTICS OVER OPERATING RANGE1.See test circuit and waveforms.2.Minimum limits are guaranteed but not tested on Propagation Delays.3.Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.4.This limit is guaranteed but not tested.C L =Load capacitance: includes jig and probe capacitance.R T =Termination resistance: should be equal to Z OUT of the PulseGenerator.TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTSENABLE AND DISABLE TIMESPROPAGATION DELAYSET-UP, HOLD AND RELEASE TIMES PULSE WIDTHSWITCH POSITIONNOTES:1.Diagram shown for input Control Enable-LOW and input Control Disable-HIGH2.Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t F ≤ 2.5ns; t R ≤ 2.5ns2542 drw 097.0V3V 1.5V 0V3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUTPRESET CLEAR ETC.1.5V1.5VSAME PHASE INPUT TRANSITION3V 1.5V 0V 1.5V V OH OUTPUTOPPOSITE PHASE INPUT TRANSITION3V 1.5V 0VV OL 3V 1.5V0V 3.5V 0VV OLENABLEDISABLEV OHPRESET CLEARCLOCK ENABLEETC.2542 drw 052542 drw 062542 drw 082542 drw 07ORDERING INFORMATIONIDT XX XXXX X XBlank BPV PA PFE CommercialMIL-STD-883, Class BShrink Small Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Small Outline Package (SO48-3) CERPACK (E48-1)Non-Inverting 16-Bit Register54 74–55°C to +125°C –40°C to +85°CFCT2542 drw 10。

4-Bit Binary CounterCY54/74FCT163TSCCS015 - May 1994 - Revised February 2000Data sheet acquired from Cypress Semiconductor Corporation.Data sheet modified to remove devices not offered.Features•Function, pinout, and drive compatible with FCT and F logic•FCT-C speed at 5.8 ns max. (Com’l),•Reduced V OH (typically = 3.3V) versions of equivalent FCT functions•Edge-rate control circuitry for significantly improved noise characteristics •Power-off disable feature •ESD > 2000V•Matched rise and fall times•Fully compatible with TTL input and output logic levels •Extended commercial range of −40˚C to +85˚C•Sink current 64 mA (Com’l),32 mA (Mil)Source current32 mA (Com’l),12 mA (Mil)Functional DescriptionThe FCT163T is a high-speed synchronous modulo-16binary counter.It is synchronously presettable for application in pro-grammable dividers and has two types of count enable inputs plus a terminal count output for versatility in forming synchro-nous multi-staged counters.The FCT163T has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.The outputs are designed with a power-off disable feature to allow for live insertion of boards.Logic Block DiagramPin ConfigurationsDetail AQ 1P 0Detail AQ 2Detail AQ 3DQCP D QQ 0P 1P 2P 3TCCEP CP Q 0Q 0Detail ACPPECETCPSR4891011127651516171832120131419P 3CETPE NC CP N C N C V CC TCCEP GND SR Top ViewP 0LCC NC P 2P 1Q 3Q 0Q 2Q 112345678CPP 0P 1P 3CEP V CC GNDTop ViewSOIC/QSOP 161514131211109SR Q3CET PETC Q 0Q 1Q 2P 2Maximum Ratings [2,3](Above which the useful life may be impaired.For user guide-lines, not tested.)Storage T emperature .....................................−65°C to +150°C Ambient T emperature withPower Applied ..................................................−65°C to +135°C Supply Voltage to Ground Potential ..................−0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V DC Output Voltage ..............................................−0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin)......120 mAPower Dissipation..........................................................0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015)Function Table [1]InputsAction on the RisingClock Edge(s)SR PE CET CEP L H H H HX L H H HX X H L XX X H X LReset (Clear)Load (P n Q n )Count (Incremental)No Charge (Hold)No Charge (Hold)Pin DescriptionName DescriptionCEP Count Enable Parallel Input CET Count Enable T rickle InputCP Clock Pulse Input (Active Rising Edge)SR Synchronous Reset Input (Active LOW)P Parallel Data InputsPE Parallel Enable Input (Active LOW)Q Flip-Flop Outputs TCTerminal Count OutputOperating RangeRange Range Ambient Temperature V CC Commercial All −40°C to +85°C 5V ± 5%Military [4]All−55°C to +125°C5V ± 10%Electrical Characteristics Over the Operating RangeParameter DescriptionTest ConditionsMin.Typ.[5]Max.Unit V OHOutput HIGH VoltageV CC =Min., I OH =−32 mA Com’l 2.0V V CC =Min., I OH =−15 mA Com’l 2.4 3.3V V CC =Min., I OH =−12 mAMil 2.43.3V V OL Output LOW Voltage V CC =Min., I OL =64 mA Com’l 0.30.55V V CC =Min., I OL =32 mAMil0.30.55V V IH Input HIGH Voltage 2.0V V IL Input LOW Voltage 0.8V V H Hysteresis [6]All inputs0.2V V IK Input Clamp Diode Voltage V CC =Min., I IN =−18 mA −0.7−1.2V I I Input HIGH Current V CC =Max., V IN =V CC 5µA I IH Input HIGH Current V CC =Max., V IN =2.7V ±1µA I IL Input LOW CurrentV CC =Max., V IN =0.5V ±1µA I OS Output Short Circuit Current [7]V CC =Max., V OUT =0.0V −60−120−225mA I OFFPower-Off DisableV CC =0V , V OUT =4.5V±1µANotes:1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.2.Unless otherwise noted, these limits are over the operating free-air temperature range.3.Unused inputs must always be connected to an appropriate logic voltage level, preferably either V CC or ground.4.T A is the “instant on” case temperature.5.Typical values are at V CC =5.0V , T A =+25˚C ambient.6.This parameter is specified but not tested.7.Not more than one output should be shorted at a time.Duration of short should not exceed one second.The use of high-speed test apparatus and/or sampleand hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values.Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests.In any sequence of parameter tests, I OS tests should be performed last.Capacitance[6]Parameter Description Typ.[5]Max.Unit C IN Input Capacitance510pFC OUT Output Capacitance912pFPower Supply CharacteristicsParameter Description Test Conditions Typ.[5]Max.Unit I CC Quiescent Power Supply Current V CC=Max., V IN≤0.2V, V IN≥V CC−0.2V0.10.2mA∆I CC Quiescent Power Supply Current(TTL inputs HIGH)V CC=Max., V IN=3.4V,[8]f1=0, Outputs Open0.2 2.0mAI CCD Dynamic Power Supply Current[9]V CC=Max.,One Bit Toggling,Load Mode,50% Duty Cycle, Outputs Open,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V0.060.12mA/MHzI C Total Power Supply Current[10]V CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,One Bit T oggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V0.7 1.4mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,One Bit T oggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC,V IN=3.4V or V IN=GND1.2 3.4mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,Four Bits Toggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V1.6 3.2[11]mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,Four Bits Toggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC,V IN=3.4V or V IN=GND2.98.2[11]mANotes:8.Per TTL driven input (V IN=3.4V); all other inputs at V CC or GND.9.This parameter is not directly testable, but is derived for use in Total Power Supply calculations.10.I C=I QUIESCENT + I INPUTS+ I DYNAMICI C=I CC+∆I CC D H N T+I CCD(f0/2 + f1N1)I CC=Quiescent Current with CMOS input levels∆I CC=Power Supply Current for a TTL HIGH input (V IN=3.4V)D H=Duty Cycle for TTL inputs HIGHN T=Number of TTL inputs at D HI CCD=Dynamic Current caused by an input transition pair (HLH or LHL)f0=Clock frequency for registered devices, otherwise zerof1=Input signal frequencyN1=Number of inputs changing at f1All currents are in milliamps and all frequencies are in megahertz.11.Values for these conditions are examples of the I CC formula. These limits are specified but not tested.Document #: 38−00285−BSwitching Characteristics Over the Operating RangeParameter DescriptionCY54FCT163TCY74FCT163CT Unit Fig. No.[13]MilitaryCommercial Min.[12]Max.Min.[12]Max.t PLH t PHL Propagation Delay CP to Q (PE Input HIGH)2.011.5 1.5 5.8ns 1, 5t PLH t PHL Propagation Delay CP to TC (PE Input LOW)2.010.0 1.5 5.2ns 1, 5t PLH t PHL Propagation Delay CP to TC 2.016.5 1.57.8ns 1, 5t PLH t PHL Propagation Delay CET to TC 1.59.01.5 4.4ns 1, 5t S Set-Up Time, HIGH or LOW P to CP 5.5 3.5ns 4t H Hold Time, HIGH or LOW P to CP 2.0 1.5ns 4t SU Set-Up Time HIGH or LOW PE or SR to CP13.57.6ns 4t H Hold Time HIGH or LOW PE or SR to CP1.5 1.0ns 4t SU Set-Up Time HIGH or LOW CEP or CET to CP 13.07.6ns 4t H Hold Time HIGH or LOW CEP or CET to CP 00ns 4t W Clock Pulse Width (Load)HIGH or LOW5.0 4.0ns 5t WClock Pulse Width(Count)HIGH or LOW8.05.0ns5Notes:12.Minimum limits are specified but not tested on Propagation Delays.13.See “Parameter Measurement Information” in the General Information section.Ordering InformationSpeed (ns)Ordering CodePackage Name Package TypeOperating Range 5.8CY74FCT163CTQCT Q116-Lead (150-Mil) QSOP CommercialCY74FCT163CTSOC/SOCT S116-Lead (300-Mil) Molded SOIC 11.5CY54FCT163TLMBL6120-Square Leadless Chip CarrierMilitaryPackage Diagrams20-Pin Square Leadless Chip Carrier L61MIL−STD−1835 C−2A16-Lead Quarter Size Outline Q1Package Diagrams (continued)16-Lead Molded SOIC S1IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 2000, Texas Instruments Incorporated。

LOW POWER SCHOTTKYDevice Package Shipping SN74LS145N 16 Pin DIP 2000 Units/Box SN74LS145D16 PinSOIC D SUFFIX CASE 751B2500/T ape & ReelPLASTIC N SUFFIX CASE 648161161ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATIONASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone:303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong 800–4422–3781Email: ONlit–asia@JAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549Phone: 81–3–5487–8345Email: r14153@Fax Response Line:303–675–2167。