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MM54HC76中文资料

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MM54HC76󰁋MM74HC76

Dual

J-K

Flip-Flops

with

Preset

and

Clear

January1988

MM54HC76󰁋MM74HC76DualJ-KFlip-Flops

withPresetandClear

GeneralDescription

Thesehighspeed(30MHzminimum)J-KFlip-Flopsutilize

advancedsilicon-gateCMOStechnologytoachieve󰀷thelow

powerconsumptionandhighnoiseimmunityofstandard

CMOSintegratedcircuits󰀷alongwiththeabilitytodrive10

LS-TTLloads󰀟

Eachflip-flophasindependentJ󰀷K󰀷PRESET󰀷CLEAR󰀷and

CLOCKinputsandQandQoutputs󰀟Thesedevicesare

edgesensitivetotheclockinputandchangestateonthe

negativegoingtransitionoftheclockpulse󰀟Clearandpre-

setareindependentoftheclockandaccomplishedbyalow

logiclevelonthecorrespondinginput󰀟The54HC󰁋74HClogicfamilyisfunctionallyaswellaspin-

outcompatiblewiththestandard54LS󰁋74LSlogicfamily󰀟

Allinputsareprotectedfromdamageduetostaticdis-

chargebyinternaldiodeclampstoVCCandground󰀟

Features

YTypicalpropagationdelay󰀌16ns

YWideoperatingvoltagerange

YLowinputcurrent󰀌1mAmaximum

YLowquiescentcurrent󰀌40mAmaximum(74HCSeries)

YHighoutputdrive󰀌10LS-TTLloads

ConnectionandLogicDiagrams

Dual-In-LinePackage

TL󰁋F󰁋5074–1TopView

OrderNumberMM54HC76orMM74HC76TruthTable

InputsOutputs

PRCLRCLKJLQQ

LHXXXHL

HLXXXLH

LLXXXL󰀂L󰀂

HHvLLQ0Q0

HHvHLHL

HHvLHLH

HHvHHTOGGLE

HHHXXQ0Q0

󰀂Thisisanunstablecondition󰀷andisnotguaranteed

TL󰁋F󰁋5074–2(1of2)TL󰁋F󰁋5074–3

C1995NationalSemiconductorCorporationRRD-B30M105󰁋PrintedinU󰀟S󰀟A󰀟元器件交易网www.cecb2b.com

AbsoluteMaximumRatings(Notes1󰁅2)

IfMilitary󰁋Aerospacespecifieddevicesarerequired󰀷

pleasecontacttheNationalSemiconductorSales

Office󰁋Distributorsforavailabilityandspecifications󰀟

SupplyVoltage(VCC)b0󰀟5toa7󰀟0V

DCInputVoltage(VIN)b1󰀟5toVCCa1󰀟5V

DCOutputVoltage(VOUT)b0󰀟5toVCCa0󰀟5V

ClampDiodeCurrent(IIK󰀷IOK)g20mA

DCOutputCurrent󰀷perpin(IOUT)g25mA

DCVCCorGNDCurrent󰀷perpin(ICC)g50mA

StorageTemperatureRange(TSTG)b65󰀃Ctoa150󰀃C

PowerDissipation(PD)

(Note3)600mW

S󰀟O󰀟Packageonly500mW

LeadTemp󰀟(TL)(Soldering10seconds)260󰀃COperatingConditions

MinMaxUnits

SupplyVoltage(VCC)26V

DCInputorOutputVoltage0VCCV

(VIN󰀷VOUT)

OperatingTemp󰀟Range(TA)

MM74HCb40a85󰀃C

MM54HCb55a125󰀃C

InputRiseorFallTimes

VCCe2󰀟0V(tr󰀷tf)1000ns

VCCe4󰀟5V500ns

VCCe6󰀟0V400ns

DCElectricalCharacteristics(Note4)

TAe25󰀃C74HC54HC

SymbolParameterConditionsVCCTAeb40to85󰀃CTAeb55to125󰀃CUnits

TypGuaranteedLimits

VIHMinimumHighLevel2󰀟0V1󰀟51󰀟51󰀟5V

InputVoltage4󰀟5V3󰀟153󰀟153󰀟15V

6󰀟0V4󰀟24󰀟24󰀟2V

VILMaximumLowLevel2󰀟0V0󰀟50󰀟50󰀟5V

InputVoltage󰀂󰀂4󰀟5V1󰀟351󰀟351󰀟35V

6󰀟0V1󰀟81󰀟81󰀟8V

VOHMinimumHighLevelVINeVIHorVILOutputVoltagelIOUTls20mA2󰀟0V2󰀟01󰀟91󰀟91󰀟9V

4󰀟5V4󰀟54󰀟44󰀟44󰀟4V

6󰀟0V6󰀟05󰀟95󰀟95󰀟9V

VINeVIHorVILlIOUTls4󰀟0mA4󰀟5V4󰀟23󰀟983󰀟843󰀟7VlIOUTls5󰀟2mA6󰀟0V5󰀟75󰀟485󰀟345󰀟2V

VOLMaximumLowLevelVINeVIHorVILOutputVoltagelIOUTls20mA2󰀟0V00󰀟10󰀟10󰀟1V

4󰀟5V00󰀟10󰀟10󰀟1V

6󰀟0V00󰀟10󰀟10󰀟1V

VINeVIHorVILlIOUTls4󰀟0mA4󰀟5V0󰀟20󰀟260󰀟330󰀟4VlIOUTls5󰀟2mA6󰀟0V0󰀟20󰀟260󰀟330󰀟4V

IINMaximumInputVINeVCCorGND6󰀟0Vg0󰀟1g1󰀟0g1󰀟0mA

Current

ICCMaximumQuiescentVINeVCCorGND6󰀟0V44080mA

SupplyCurrentIOUTe0mA

Note1󰀌AbsoluteMaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur󰀟

Note2󰀌Unlessotherwisespecifiedallvoltagesarereferencedtoground󰀟

Note3󰀌PowerDissipationtemperaturederating󰁚plastic‘‘N’’package󰀌b12mW󰁋󰀃Cfrom65󰀃Cto85󰀃C󰀥ceramic‘‘J’’package󰀌b12mW󰁋󰀃Cfrom100󰀃Cto125󰀃C󰀟

Note4󰀌Forapowersupplyof5Vg10%theworstcaseoutputvoltages(VOH󰀷andVOL)occurforHCat4󰀟5V󰀟Thusthe4󰀟5Vvaluesshouldbeusedwhendesigningwiththissupply󰀟WorstcaseVIHandVILoccuratVCCe5󰀟5Vand4󰀟5Vrespectively󰀟(TheVIHvalueat5󰀟5Vis3󰀟85V󰀟)Theworstcaseleakagecurrent(IIN󰀷ICC󰀷andIOZ)occurforCMOSatthehighervoltageandsothe6󰀟0Vvaluesshouldbeused󰀟

󰀂󰀂VILlimitsarecurrentlytestedat20%ofVCC󰀟TheaboveVILspecification(30%ofVCC)willbeimplementednolaterthanQ1󰀷CY’89󰀟

2元器件交易网www.cecb2b.com

ACElectricalCharacteristicsVCCe5V󰀷TAe25󰀃C󰀷CLe15pF󰀷tretfe6ns

SymbolParameterConditionsTypGuaranteedLimitUnits

fMAXMaximumOperatingFrequency5030MHz

tPHL󰀷tPLHMaximumPropagationDelayClocktoQorQ1621ns

tPHL󰀷tPLHMaximumPropagationDelayCleartoQorQ2126ns

tPHL󰀷tPLHMaximumPropagationDelayPresettoQorQ2328ns

tREMMinimumRemovalTime1020ns

tsMinimumSetupTimeJorKtoClock1420ns

tHMinimumHoldTimeJorKtoClockb30ns

tWMinimumPulseWidthPreset󰀷ClearorClock1016ns

ACElectricalCharacteristicsCLe50pF󰀷tretfe6ns(unlessotherwisespecified)

TAe25󰀃C74HC54HC

SymbolParameterConditionsVCCTAeb40to85󰀃CTAeb55to125󰀃CUnits

TypGuaranteedLimits

fMAXMaximumOperating2󰀟0V9543MHz

Frequency4󰀟5V45272118MHz

6󰀟0V53312420MHz

tPHL󰀷tPLHMaximumPropagation2󰀟0V100126160183ns

DelayClocktoQorQ4󰀟5V20253137ns

6󰀟0V17212732ns

tPHL󰀷tPLHMaximumPropagation2󰀟0V126155191250ns

DelayCleartoQorQ4󰀟5V25313947ns

6󰀟0V21263340ns

tPHL󰀷tPLHMaximumPropagation2󰀟0V137165210240ns

Delay󰀷PresettoQorQ4󰀟5V27334150ns

合集下载

HCF4076B_02中文资料

HCF4076B_02中文资料

1/9September 2002sTHREE STATE OUTPUTSsINPUT DISABLE WITHOUT GATING THE CLOCKsGATED OUTPUT CONTROL LINES FOR ENABLING OR DISABLING THE OUTPUTSsBUFFERED INPUTS AND OUTPUTS s QUIESCENT CURRENT SPECIFIED UP TO 20Vs5V, 10V AND 15V PARAMETRIC RATINGSsINPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°Cs100% TESTED FOR QUIESCENT CURRENT sMEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"DESCRIPTIONHCF4076B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP and SOP packages. HCF4076B is a four bit register consisting ofD-TYPE flip-flops that feature three state outputs.Data Disable inputs are provided to control theentry of data into the flip-flops. When both DataDisable inputs are low, data at the D inputs areloaded into their respective flip-flops on the nextpositive transition of the clock input. OutputDisable inputs are also provided. When the OutputDisable inputs are both low, the normal logicstates of the four outputs are available to the load.The outputs are disabled independently of theclock by a high logic level at either Output Disableinput, and present a high impedance.HCF4076B4 BIT D TYPE REGISTERS

M74HC51中文资料

M74HC51中文资料

1/9August2001sHIGHSPEED:tPD=11ns(TYP.)atVCC=6VsLOWPOWERDISSIPATION:ICC=1µA(MAX.)atTA=25°CsHIGHNOISEIMMUNITY:VNIH=VNIL=28%VCC(MIN.)sSYMMETRICALOUTPUTIMPEDANCE:|IOH|=IOL=4mA(MIN)sBALANCEDPROPAGATIONDELAYS:tPLH≅tPHLsWIDEOPERATINGVOLTAGERANGE:VCC(OPR)=2Vto6VsPINANDFUNCTIONCOMPATIBLEWITH74SERIES51

DESCRIPTIONTheM74HC51isanhighspeedCMOSDUAL2WIDE2INPUTAND/ORINVERTGATEfabricatedwithsilicongateC2MOStechnology.Itcontainsa2-WIDE2-INPUTAND/ORINVERTGATEanda2-WIDE3-INPUTAND/ORINVERTGATE.Theinternalcircuitiscomposedof3stages(2INPUT)or5stages(3INPUT)includingbufferoutput,whichenableshighnoiseimmunityandstableoutput.Allinputsareequippedwithprotectioncircuitsagainststaticdischargeandtransientexcessvoltage.M74HC51

DUAL2WIDE2INPUTAND/ORINVERTGATE

PINCONNECTIONANDIECLOGICSYMBOLSORDERCODESPACKAGETUBET&RDIPM74HC51B1RSOPM74HC51M1RM74HC51RM13TRTSSOPM74HC51TTRTSSOPDIPSOP元器件交易网

74hc573完整中文资料

74hc573完整中文资料

74hc573中文资料参数-74hc573引脚图-功能原理-74hC573的作用-应用电路-74hC563-54hC57

高性能硅门 CMOS器件

SL74HC573跟 LS/AL573的管脚一样。器件的输入是和标准CMOS输出兼容的；加上拉电阻，他们能和 LS/ALSTTL输出兼容。

当锁存使能端为高时，这些器件的锁存对于数据是透明的（也就是说输出同步）。当锁存使能变低时，符合建立时间和保持时间的数据会被锁存。

×输出能直接接到CMOS，NMOS和 TTL接口上

×操作电压范围：2.0V~6.0V

×低输入电流：1.0uA

×CMOS器件的高噪声抵抗特性

·三态总线驱动输出

·置数全并行存取

·缓冲控制输入

·使能输入有改善抗扰度的滞后作用

原理说明：

M54HC563/74HC563/M54HC573/74HC573的八个锁存器都是透明的D 型锁存器，当使能（G）为高时，Q 输出

将随数据（D）输入而变。当使能为低时，输出将锁存在已建立的数据电平上。输出控制不影响锁存器的内部工作，即老数据可以保持，甚至当输出被关闭时，

新的数据也可以置入。这种电路可以驱动大电容或低阻抗负载，可以直接与系统总线接口并驱动总线，而不需要外接口。特别适用于缓冲寄存器，I/O 通道，双向总线驱动器和工作寄存器。

HC563引脚功能表：

PIN No 引脚号 SYMBOL符号 NAME AND FUNCTION名称及功能 1 OE 3 State output Enable Input (Active LOW)3态输出使能输入（低电平）

2, 3, 4, 5, 6, 7, 8, 9 D0 to D7 Data Inputs数据输入

12,13,14,15,16,17,18,19 Q0 to Q7 3 State Latch Outputs 3态锁存输出

11 LE Latch Enable Input 锁存使能输入

ST M74HC86 数据手册

ST M74HC86 数据手册

1/8July 2001sHIGH SPEED:tPD = 12ns (TYP.) at VCC = 6VsLOW POWER DISSIPATION:ICC = 1µA(MAX.) at TA=25°CsHIGH NOISE IMMUNITY:VNIH = VNIL = 28 % VCC (MIN.)sSYMMETRICAL OUTPUT IMPEDANCE:|IOH| = IOL = 4mA (MIN)sBALANCED PROPAGATION DELAYS:tPLH ≅ tPHL sWIDE OPERATING VOLTAGE RANGE:VCC (OPR) = 2V to 6VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 86

DESCRIPTIONThe M74HC86 is an high speed CMOS QUADEXCLUSIVE OR GATE fabricated with silicongate C2MOS technology.Input and output buffer are installed, whichenables high noise immunity and stable output.All inputs are equipped with protection circuitsagainst static discharge and transient excessvoltage.M74HC86

QUAD EXCLUSIVE OR GATE

PIN CONNECTION AND IEC LOGIC SYMBOLSORDER CODES PACKAGETUBET & RDIPM74HC86B1RSOPM74HC86M1RM74HC86RM13TRTSSOPM74HC86TTRTSSOPDIPSOPM74HC862/8INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION