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SP601 Hardware User GuideUG518 (v1.7) September 26, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. 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Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. Y ou may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at /warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:/warranty.htm#critapps.Revision HistoryThe following table shows the revision history for this document.Date Version Revision07/15/09 1.0Initial Xilinx release.08/19/09 1.1•Added Appendix B, VITA 57.1 FMC LPC Connector Pinout.•Updated Figure1-17.•Updated Table1-4, Table1-19, and Table1-22.•Added introductory paragraph to Appendix C, SP601 Master UCF.•Miscellaneous typographical edits and new user guide template.05/17/10 1.2•Updated Figure1-1, Figure1-2, Figure1-14, Figure1-18, Table1-9, Table1-1,Table1-11, and Table1-16.•Added Figure1-7, Figure1-8, and Table1-13.•Updated 9. VITA 57.1 FMC-LPC Connector, page25, Appendix B, VITA 57.1 FMCLPC Connector Pinout, and Appendix C, SP601 Master UCF.06/16/10 1.3Reversed order of 15. Configuration Options and 16. Power Management. Updated 1.Spartan-6 XC6SLX16-2CSG324 FPGA and 2. 128 MB DDR2 Component Memory. AddedTable1-26. Added UG394, Spartan-6 FPGA Power Management User Guide to Appendix D,References.09/24/10 1.4Added Power System Test Points, including Table1-25.02/16/11 1.5Added note and revised header description to indicate the I/Os support LVCMOS25signaling on page34. Revised oscillator manufacturer information from Epson to SiTimeon page page23 and page51.07/18/11 1.6Corrected wording from “PPM frequency jitter” to “PPM frequency stability” in sectionOscillator (Differential), page23. Added Table1-15, page27.09/26/12 1.7Added Regulatory and Compliance Information, page53.SP601 Hardware User Guide UG518 (v1.7) September 26, 2012SP601 Hardware User Guide 3UG518 (v1.7) September 26, 2012Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1: SP601 Evaluation BoardOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Related Xilinx Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101. Spartan-6 XC6SLX16-2CSG324 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11I/O Voltage Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122. 128 MB DDR2 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123. SPI x4 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154. Linear Flash BPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196. USB-to-UART Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228-Kb NV Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Oscillator Socket (Single-Ended, 2.5V or 3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SMA Connectors (Differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249. VITA 57.1 FMC-LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2510. Status LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811. FPGA Awake LED and Suspend Jumper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912. FPGA INIT and DONE LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3013. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3114. FPGA_PROG_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515. Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616. Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AC Adapter and 5V Input Power Jack/Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Onboard Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Power System Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table of ContentsAppendix A: Default Jumper and Switch SettingsAppendix B: VITA 57.1 FMC LPC Connector PinoutAppendix C: SP601 Master UCFAppendix D: ReferencesAppendix E: Regulatory and Compliance InformationDirectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SP601 Hardware User GuideUG518 (v1.7) September 26, 2012SP601 Hardware User Guide 5UG518 (v1.7) September 26, 2012PrefaceAbout This GuideThis manual accompanies the Spartan®-6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools.Guide ContentsThis manual contains the following chapters:•Chapter 1, SP601 Evaluation Board , provides an overview of the SP601 evaluation board and details the components and features of the SP601 board.•Appendix A, Default Jumper and Switch Settings .•Appendix B, VITA 57.1 FMC LPC Connector Pinout .•Appendix C, SP601 Master UCF .•Appendix D, References .Additional DocumentationThe following documents are available for download at /products/spartan6.•Spartan-6 Family OverviewThis overview outlines the features and product selection of the Spartan-6 family.•Spartan-6 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and switching characteristic specifications for the Spartan-6 family.•Spartan-6 FPGA Packaging and Pinout SpecificationsThis specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.•Spartan-6 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.•Spartan-6 FPGA SelectIO Resources User GuideThis guide describes the SelectIO™ resources available in all Spartan-6 devices.•Spartan-6 FPG A Clocking Resources User GuidePreface:About This GuideThis guide describes the clocking resources available in all Spartan-6 devices,including the DCMs and PLLs.•Spartan-6 FPGA Block RAM Resources User GuideThis guide describes the Spartan-6 device block RAM capabilities.•Spartan-6 FPGA DSP48A1 Slice User GuideThis guide describes the architecture of the DSP48A1 slice in Spartan-6FPGAs andprovides configuration examples.•Spartan-6 FPGA Memory Controller User GuideThis guide describes the Spartan-6 FPGA memory controller block, a dedicatedembedded multi-port memory controller that greatly simplifies interfacingSpartan-6FPGAs to the most popular memory standards.•Spartan-6 FPGA PCB Designer’s GuideThis guide provides information on PCB design for Spartan-6 devices, with a focus onstrategies for making design decisions at the PCB and interface level.Additional Support ResourcesTo search the database of silicon and software questions and answers or to create atechnical support case in WebCase, see the Xilinx website at:/support. SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter1 SP601 Evaluation BoardOverviewThe SP601 board enables hardware and software developers to create or evaluate designstargeting the Spartan®-6 XC6SLX16-2CSG324 FPGA.The SP601 provides board features for evaluating the Spartan-6 family that are common tomost entry-level development environments. Some commonly used features include aDDR2 memory controller, a parallel linear flash, a tri-mode Ethernet PHY, general-purposeI/O (GPIO), and a UART. Additional functionality can be added through the VITA 57.1.1expansion connector. Features, page8 provides a general listing of the board features withdetails provided in Detailed Description, page10.Additional InformationAdditional information and support material is located at:•/sp601This information includes:•Current version of this user guide in PDF format•Example design files for demonstration of Spartan-6 FPGA features and technology•Demonstration hardware and software configuration files for the SP601 linear and SPImemory devices•Reference Design Files•Schematics in PDF format and DxDesigner schematic format•Bill of materials (BOM)•Printed-circuit board (PCB) layout in Allegro PCB format•Gerber files for the PCB (Many free or shareware Gerber file viewers are available onthe internet for viewing and printing these files.)•Additional documentation, errata, frequently asked questions, and the latest newsFor information about the Spartan-6 family of FPGA devices, including product highlights,data sheets, user guides, and application notes, see the Spartan-6 FPGA website at/support/documentation/spartan-6.htm.SP601 Hardware User Guide 7 UG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardFeaturesThe SP601 board provides the following features (see Figure1-2 and Table1-1):• 1. Spartan-6 XC6SLX16-2CSG324 FPGA• 2. 128 MB DDR2 Component Memory• 3. SPI x4 Flash• 4. Linear Flash BPI• 5. 10/100/1000 Tri-Speed Ethernet PHY•7. IIC Bus•8Kb NV memory•External access 2-pin header•VITA 57.1 FMC-LPC connector•8. Clock Generation•Oscillator (Differential)•Oscillator Socket (Single-Ended, 2.5V or 3.3V)•SMA Connectors (Differential)•9. VITA 57.1 FMC-LPC Connector•10. Status LEDs•FPGA_AWAKE•INIT•DONE•13. User I/O•User LEDs•User DIP switch•User pushbuttons•GPIO male pin header•14. FPGA_PROG_B Pushbutton Switch•15. Configuration Options• 3. SPI x4 Flash (both onboard and off-board)• 4. Linear Flash BPI•JTAG Configuration•16. Power Management•AC Adapter and 5V Input Power Jack/Switch•Onboard Power Supplies SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Related Xilinx DocumentsBlock DiagramFigure1-1 shows a high-level block diagram of the SP601 and its peripherals.Figure 1-1:SP601 Features and BankingRelated Xilinx DocumentsPrior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.See the following locations for additional documentation on Xilinx tools and solutions:•ISE: /ise•Answer Browser: /support•Intellectual Property: /ipcenterSP601 Hardware User Guide 9 UG518 (v1.7) September 26, 2012SP601 Hardware User GuideUG518 (v1.7) September 26, 2012Chapter 1:SP601 Evaluation BoardDetailed DescriptionFigure 1-2 shows a board photo with numbered features corresponding to Table 1-1 and the section headings in this document.The numbered features in Figure 1-2 correlate to the features and notes listed in Table 1-1.Figure 1-2:SP601 Board PhotoUG518_02_09100912843126137115109141581316Table 1-1:SP601 FeaturesNumberFeatureNotesSchematic Page1 Spartan-6 FP G A XC6SLX16-2CS G 3242DDR2 Component Elpida EDE1116ACBG 1Gb DDR2SDRAM53SPI x4 Flash and Headers SPI select and External Headers 84Linear Flash BPIStrataFlash 8-bit (J3 device), 3 pins shared w/ SPI x481. Spartan-6 XC6SLX16-2CSG 324 FPGAA Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the SP601 Evaluation Board.ReferencesSee the Spartan-6 FPGA Data Sheet . [Ref 1]ConfigurationThe SP601 supports configuration in the following modes:•Master SPI x4•Master SPI x4 with off-board device •BPI•JTAG (using the included USB-A to Mini-B cable)For details on configuring the FPGA, see 15. Configuration Options .The Mode DIP switch SW2 is set to M[1:0] = 01 Master SPI default.ReferencesSee the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]510/100/1000 Ethernet PHY GMII Marvell Alaska PHY76RS232 UART (USB Bridge)Uses CP2103 Serial-to-USB connection 107IICGoes to Header and VITA 57.1 FMC 108Clock, socket, SMA Differential, Single-Ended, Differential 99VITA 57.1 FMC-LPC connector LVDS signals, clocks, PRSNT 610LEDs Ethernet PHY Status711LED, Header FPGA Awake LED, Suspend Header 812LEDs FPGA INIT, DONE 913LED User I/O (active-High)9DIP SwitchUser I/O (active-High)9PushbuttonUser I/O, CPU_RESET (active-High)912-pin (8 I/O) Header6 pins x 2 male header with 8 I/Os (active-High)1014Pushbutton FPGA_PROG_B915USB JTAG Cypress USB to JTAG download cable logic14, 1516Onboard PowerPower Management11,12,13Table 1-1:SP601 Features (Cont’d)NumberFeatureNotesSchematic PageSP601 Hardware User Guide I/O Voltage RailsThere are four available banks on the LX16-CSG324 device. Banks 0, 1, and 2 are connected for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6 FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by the SP601 board is summarized in Table 1-2.ReferencesSee the Spartan-6 FPGA documentation for more information at /support/documentation/spartan-6.htm .2. 128 MB DDR2 Component MemoryThere are 128MB of DDR2 memory available on the SP601 board. A 1-Gb ElpidaEDE1116ACBG (84-ball) DDR2 memory component is accessible through Bank 3 of the LX16 device. The Spartan-6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface’s 16-bit data path using SSTL18 signaling. The SP601 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 625Mb/s for DDR2 memory in a -2 speed grade device. Signal integrity is maintained through DDR2 resistor terminations and memory on-die terminations (ODT), as shown in Table 1-3 and Table 1-4.Table 1-2:I/O Voltage Rail of FPGA BanksFPGA BankI/O Voltage Rail0 2.5V 1 2.5V 2 2.5V 31.8VTable 1-3:Termination Resistor RequirementsSignal NameBoard TerminationOn-Die TerminationDDR2_A[14:0]49.9Ω to V TT DDR2_BA[2:0]49.9Ω to V TT DDR2_RAS_N 49.9Ω to V TT DDR2_CAS_N 49.9Ω to V TT DDR2_WE_N 49.9Ω to V TT DDR2_CS_N 100Ω to GND DDR2_CKE 4.7K Ω to GND DDR2_ODT 4.7K Ω to GNDDDR2_DQ[15:0]ODT DDR2_UDQS[P ,N], DDR2_LDQS[P ,N]ODT DDR2_UDM, DDR2_LDMODTTable 1-5 shows the connections and pin numbers for the DDR2 Component Memory.DDR2_CK[P ,N]100Ω differential at memorycomponentNotes:1.Nominal value of V TT for DDR2 interface is 0.9V .Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements FPGA U1 PinFPGA Pin NumberBoard Connection for OCTZIO L6No Connect RZQC2100Ω to GROUNDTable 1-5:DDR2 Component Memory ConnectionsFPGA U1 PinSchematic Net Name Memory U2Pin NumberPin NameJ7DDR2_A0M8A0J6DDR2_A1M3A1H5DDR2_A2M7A2L7DDR2_A3N2A3F3DDR2_A4N8A4H4DDR2_A5N3A5H3DDR2_A6N7A6H6DDR2_A7P2A7D2DDR2_A8P8A8D1DDR2_A9P3A9F4DDR2_A10M2A10D3DDR2_A11P7A11G6DDR2_A12R2A12L2DDR2_DQ0G8DQ0L1DDR2_DQ1G2DQ1K2DDR2_DQ2H7DQ2K1DDR2_DQ3H3DQ3H2DDR2_DQ4H1DQ4H1DDR2_DQ5H9DQ5J3DDR2_DQ6F1DQ6Table 1-3:Termination Resistor Requirements (Cont’d)Signal NameBoard Termination On-Die TerminationSP601 Hardware User Guide ReferencesSee the Elpida DDR2 SDRAM Specifications for more information. [Ref 11]Also, see the Spartan-6 FPGA Memory Controller User Guide . [Ref 3]J1DDR2_DQ7F9DQ7M3DDR2_DQ8C8DQ8M1DDR2_DQ9C2DQ9N2DDR2_DQ10D7DQ10N1DDR2_DQ11D3DQ11T2DDR2_DQ12D1DQ12T1DDR2_DQ13D9DQ13U2DDR2_DQ14B1DQ14U1DDR2_DQ15B9DQ15F2DDR2_BA0L2BA0F1DDR2_BA1L3BA1E1DDR2_BA2L1BA2E3DDR2_WE_B K3WE L5DDR2_RAS_B K7RAS K5DDR2_CAS_B L7CAS K6DDR2_ODT K9ODT G3DDR2_CLK_P J8CK G1DDR2_CLK_N K8CK H7DDR2_CKE K2CKE L4DDR2_LDQS_P F7LDQS L3DDR2_LDQS_N E8LDQS P2DDR2_UDQS_P B7UDQS P1DDR2_UDQS_N A8UDQS K3DDR2_LDM F3LDM K4DDR2_UDMB3UDMTable 1-5:DDR2 Component Memory Connections (Cont’d)FPGA U1 PinSchematic Net Name Memory U2Pin NumberPin Name3. SPI x4 FlashThe Xilinx Spartan-6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACTconfiguration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flashthrough a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing anexternal SPI flash memory device.The SP601 SPI interface has two parallel connected configuration options (see Figure1-4):an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flashprogramming header (J12). J12 supports a user-defined SPI mezzanine board. The SPIconfiguration source is selected via SPI select jumper J15. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-3:J12 SPI Flash Programming HeaderSP601 Hardware User Guide ReferencesSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref 12]See the XPS Serial Peripheral Interface Data Sheet for more information. [Ref 4]Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsFPGA U1 PinSchematic Net Name SPI MEM U17SPI HDR J12Pin #Pin NamePinNumberPin NameV2FPGA_PROG_B 1V14FPGA_D2_MISO31IO3_HOLD_B 2T14FPGA_D1_MISO2_R 9IO2_WP_B3V3SPI_CS_B4TMS T13FPGA_MOSI_CSI_B_MISO015DIN 5TDI R13FPGA_D0_DIN_MISO_MISO18IO1_DOUT6TDO R15FPGA_CCLK16CLK7TCK 8GND 9VCC3V3J15.2SPIX4_CS_B 7CS_B4. Linear Flash BPIAn 8-bit (16MB) Numonyx linear flash memory (TE28F128J3D-75) (J3D type) is used toprovide non-volatile bitstream, code, and data storage. The J3D devices operate at 3.0V; theSpartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels todirectly access the linear flash BPI through a 2.5V bank. For details on configuring theFPGA, see 15. Configuration Options.Figure 1-5:Linear Flash BPI InterfaceTable 1-7:BPI Memory ConnectionsFPGA U1 Pin Schematic Net Name BPI Memory U10Pin Number Pin Name K18FLASH_A032A0K17FLASH_A128A1J18FLASH_A227A2J16FLASH_A326A3G18FLASH_A425A4G16FLASH_A524A5H16FLASH_A623A6H15FLASH_A722A7H14FLASH_A820A8H13FLASH_A919A9F18FLASH_A1018A10F17FLASH_A1117A11K13FLASH_A1213A12K12FLASH_A1312A13E18FLASH_A1411A14E16FLASH_A1510A15G13FLASH_A168A16SP601 Hardware User Guide Note:Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made availablefor larger density devices.ReferencesSee the Numonyx Embedded Flash Memory Data Sheet for more information. [Ref 13]In addition, see the Spartan-6 FPGA Configuration User Guide for more information. [Ref 2]H12FLASH_A177A17D18FLASH_A186A18D17FLASH_A195A19G14FLASH_A204A20F14FLASH_A213A21C18FLASH_A221A22C17FLASH_A2330A23F16FLASH_A2456A24R13FPGA_D0_DIN_MISO_MISO133DQ0T14FPGA_D1_MISO235DQ1V14FPGA_D2_MISO338DQ2U5FLASH_D340DQ3V5FLASH_D444DQ4R3FLASH_D546DQ5T3FLASH_D649DQ6R5FLASH_D751DQ7M16FLASH_WE_B 55WE_B L18FLASH_OE_B 54OE_B L17FLASH_CE_B14CE0B3FMC_PWR_GOOD_FLASH_RST_B16RP_BTable 1-7:BPI Memory Connections (Cont’d)FPGA U1 PinSchematic Net NameBPI Memory U10Pin NumberPin Name5. 10/100/1000 T ri-Speed Ethernet PHYThe SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface fromthe FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through aHalo HFJ11-1G01E RJ-45 connector with built-in magnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table1-8. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-8:PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0V CC 2.5V PHYADR[2] = 1PHYADR[1] = 1PHYADR[0] = 1 CFG1Ground ENA_PAUSE = 0PHYADR[4] = 0PHYADR[3] = 0 CFG2V CC 2.5V ANEG[3] = 1ANEG[2] = 1ANEG[1] = 1 CFG3V CC 2.5V ANEG[0] = 1ENA_XC = 1DIS_125 = 1 CFG4V CC 2.5V HWCFG_MD[2] = 1HWCFG_MD[1] = 1HWCFG_MD[0] = 1 CFG5V CC 2.5V DIS_FC = 1DIS_SLEEP = 1HWCFG_MD[3] = 1 CFG6PHY_LED_RX SEL_BDT = 0INT_POL = 175/50Ω = 0 Table 1-9:Ethernet PHY ConnectionsFPGA U1 Pin Schematic Net NameU3 M88E111Pin Number Pin NameP16PHY_MDIO33MDIO N14PHY_MDC35MDC J13PHY_INT32INT_B L13PHY_RESET36RESET_B M13PHY_CRS115CRS L14PHY_COL114COL L16PHY_RXCLK7RXCLK P17PHY_RXER8RXER N18PHY_RXCTL_RXDV4RXDV M14PHY_RXD03RXD0 U18PHY_RXD1128RXD1 U17PHY_RXD2126RXD2 T18PHY_RXD3125RXD3 T17PHY_RXD4124RXD4 N16PHY_RXD5123RXD5SP601 Hardware User GuideReferencesSee the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.[Ref 16]Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide . [Ref 5]N15PHY_RXD6121RXD6P18PHY_RXD7120RXD7A9 PHY_TXC_G TPCLK 14G TXCLKB9 PHY_TXCLK 10TXCLK A8 PHY_TXER 13TXER B8 PHY_TXCTL_TXEN 16TXEN F8 PHY_TXD018TXD0G 8 PHY_TXD119TXD1A6 PHY_TXD220TXD2B6 PHY_TXD324TXD3E6 PHY_TXD425TXD4F7 PHY_TXD526TXD5A5 PHY_TXD628TXD6C5 PHY_TXD729TXD7Table 1-9:Ethernet PHY Connections (Cont’d)FPGA U1 PinSchematic Net NameU3 M88E111Pin NumberPin Name6. USB-to-UART BridgeThe SP601 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to SP601 connector J9). Table 1-10 details the SP601 J9 pinout.Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins, transmit (TX), receive (RX), Request to Send (RTS), and Clear to Send (CTS).Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the CP2103GM USB-to-UART bridge to appear as a COM port to host computercommunications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the SP601. Refer to the SP601 Getting Started Guide for driver installation instructions.ReferencesRefer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.In addition, see some of the Xilinx UART IP specifications at:•/support/documentation/ip_documentation/xps_uartlite.pdf •/support/documentation/ip_documentation/xps_uart16550.pdfTable 1-10:USB Type B Pin Assignments and Signal DefinitionsUSB ConnectorPinSignal NameDescription1VBUS +5V from host system (not used)2USB_DATA_N Bidirectional differential serial data (N-side)3USB_DATA_P Bidirectional differential serial data (P-side)4GROUNDSignal groundTable 1-11:CP2103GM ConnectionsFPGA U1 PinUART Functionin FPGA Schematic Net Name U4 CP2103GMPinUART Function in CP2103GM U10RTS, output USB_1_CTS 22CTS, input T5CTS, input USB_1_RTS 23RTS, output L12TX, data out USB_1_RX 24RXD, data in K14RX, data inUSB_1_TX25TXD, data out。

D/A D/A D/A D/A D/A T/A T/A T/A
T/A T/A D/A D/A D/A D/A D/A D/A
MTFC4GACAAAM-1M WT 32Gb MLC x 1 MTFC8GACAAAM-1M WT 32Gb MLC x 2
MTFC16GAKAECN-2M WTES 64Gb MLC x 2 16GB
4
Rockchip Solutions eMMC Support List
RK316X PKG size RK3036 RK3066 RK3026 RK328X RK318X RK3368 RK322X RK3028A (mm) RK312X RKPX2 RKPX3
Manufacturer
Part Number
Device Size (bits)
Byte Size
Process Version
Remark
Micron Micron Micron Micron Micron Micron Micron Micron
MTFC4GACAAEA-WT MTFC8GACAAEA-WT
32Gb MLC x 1 32Gb MLC x 2
2014.12.01 2015.01.05 2015.04.13
1. Add eMMC32G-S100 1. Add RK3368 SupportList。 2. Add THGBMBG5D1KBAIL,THGBM9G9T8KBAIG,SDIN9DS2-32G,SDIN9DS2-16G,KLMBG4WEBD-B031,KLMCG8WEBD-B031,etc 1. Add THGBMFG6C1LBAIL,THGBMFG7C1LBAIL,THGBMFG7C2LBAIL,THGBMFG8C2LBAIL,THGBMFG8C4LBAIL,SDIN9DS28G,H26M41103HPRL,S404100081B1B1W00, S404100161B1B1W01,EM100C-008GT-SS,EM100C-016GT-SS, etc 1. Add NCEFEM48-04G etc 1. Update RK3368 SupportList 1. Add RK3228 SupportList 1. Add MTFC8GLCDM-1M WT. 1. Add BWATGSC11C08G, NCEFAT28-08G, H26T55001FPR, THGBMBG7D2KBAIL, KLM8G1GEND-B031, KLMCG8GEND-B031, THGBMFG8C4LBAIR, NCEMAH59-16G, REMKDM104GSBB, REMKDM308GSBB, GD9E4MOOYNI, SP18A8G752-8GB 1. RK32XX -> RK328X 2. Add RKPX3 and RKPX2 3. Add MTFC4GACAJCN-1M WT, MTFC8GAKAJCN-1M WT, THGBMDG5D1LBAIL ， KLM4G1FEPD-B031，EMMC16G-M525，EMMC32GM525 and EMMC64G-M525.

RSLogix 5000 Release 17.00Copyright © 2008 Rockwell Automation, Inc. All rights reserved.Logix V17 Extensions• Software Extensions– Partial Import / Export of Routines and Programs – Full Project XML (L5X) Import/Export – Offline Partial Import of Modified UDT with Data Preservation – Runtime Partial Import of Routines, Programs, and NEW Add-On-Instructions – Multi-Lingual project documentation with Language Switching – Controller on-line project change logging• Reporting– Controller Organizer Report• Usability Extensions– – – – – – – – – – – – – – – – Forcing and Toggle Bit Added to Quick Watch Window Tag Monitor Enhancement - Alarm Grid Display Mode Search Item Browser Supports Tag Name Typeahead ControlFlash v7.0 Enhancements Coordinated System Time (CST) Master Existence Check On Download Tag’s Descriptions Length Extended Produced / Consumed Tag Status Verification Warning If Forces Are Present Verification Warning If AFI Are Present System Install Enhancements Start Page Enhancements Decorated Data Support in L5X Import/Export Files RSLogix 5000 Professional Concurrent RSLogix 5000 Standard Concurrent RSLogix 5000 Professional Changes Microsoft Windows Vista Support• Programming Languages Enhancements– LD Instruction Parameter Display Optimization Options – FBD Advanced Process Control Blocks (Smith Predictor, Coordinated Control, Multivariable control) – SFR Instruction Filters Routine Types and Step Names – Option to hold SFC Step / Action Timer “Acc” when chart is paused – SFC Chart Paused State Via GSV Instruction – Tag’s Description Added to Tooltips in FBD Editor – GuardLogix SIL 3 Instructions Extensions• Miscellaneouos• Motion Enhancements– Motion multi-axis programmable Jerk – MCD and MCCD Motion Instructions Enhancements• RSI Integration– FactoryTalk AssetCentre Archive Check-In/Out – RSLogix Architect Library Management2010/12/24Logix V17 Extensions Continued• New Network and I/O Module Profiles– Flex 1794-IJ2I Isolated Counter – Flex 1794- IF4XOF4I 4pt In / 4pt Out Combination Isolated Analog – Flex 1794-IG16, OG16, IH16, IV32, OV32, IM16, OM16 – Flex 1794-IT8/B, 1794-IR8/B, 1794-IF8I and 1794-OF8I – ControlLogix 1756-EN2F Major rev 2 – ControlLogix 1756-CFM Counter Major Rev 2 (Config output based on freq) – ControlLogix 1756-OB8I 8pt Isolated DC Output – 1768 Compact Generic Config Profile – 1757-FFLDC ControlNet to Foundation Fieldbus Linking Device – Adding PowerFlex 7 & 4 Drives On-line on EtherNet/IP and ControlNet – Thin profiles for Flex IO modules (1794IF8IH/B, 1794-OF8IH/B, 1794-IE8H/B, 1794OE8H/B, 1797-IE8H/B, 1797-OE8H/B) – 1797-ACNR15 Major rev 5• Controller Support– ControlLogix 1756-L65 32MB Memory Controller – GuardLogix 1756-L63S Controller – CompactLogix 1769-L2x Controllers – Removal of ControlLogix 1756-L55 and FlexLogix 1794-L34B Controller• Other– StratixTM Industrial Switch Portfolio – CIP Sync support on 1756-EN2T – Unicast Produced/Consumed Tags for EtherNet/IP Generic Modules – CIP Generic Module COMM Format of None – Cyclic EDT support for flex adapters (1794ACN, 1794-ACNR, 1794-AENT, 1797-ACNR)• Tools– Logix5000 Update Tool – DELMIA Automation Bi-Directional Synchronization Utility2010/12/24Program & Routine Partial Import / Export• V17 provides ability to export Programs, Phases and Routines– Similar to the V13 LD Rung Partial Import/Export – Includes support for FBD,SFC and ST• The export “.L5X” file includes all pertinent information– Program configuration, code, user defined data-types, tags and descriptions – XML formatted ASCII text file – Distribute code separately from the RSLogix 5000 Project “.ACD” file – The file can be manipulated and even created by other tools• Create larger libraries of reusable code– Provides more control over the scope of what will be extracted from the project – Useful for larger machine, cell or unit control – Promotes standardization and reuse2010/12/24Importing into a project• To import, select the previously exported Add-On Instruction, program, phase, routine, or UDT you wish to use in your running project and click on Import...2010/12/24Import Configuration dialog• Provides a listing of all components which will be imported and whether they conflict with existing components already in the running project. • Allows you to resolve conflicts when collisions occur.2010/12/24RSLogix 5000 Project “.L5X” Import/Export• Extends RSLogix 5000 to support import/export of a FULL project to an XML formatted file– Contains: processor / I/O / motion configuration, application logic, data / structures / tag definitions, comments and descriptions – Similar to ASCII Text L5K file but uses an XML Scheme – Open and fully documented in publication 1756-RM084E-EN-P• Useful for enhancing development productivity– Manipulate application source using text editing tools – Build tools to auto-generate projects – Extract / merge code fragments to build new projects2010/12/24Off-line Partial Import of Modified UDT with Data Preservation• With release V16, we allowed you to import/export a UDT to an XML file– However, only new UDTs could be importedOld UDT• With V17, we are extending this functionality by allowing existing UDTs to be imported while maintaining existing members’ data values– Data values will be maintained when: • Inserting/adding members • Deleting members • Rearranging (moving) members • Renaming members • Changing the data types of members – Data values for members renamed and moved will not be maintainedAdded Member member Added Added Member leaves existing data values unchanged• Improves user experience by allowing easy UDT maintenance off-lineUpdated UDT2010/12/24 Runtime Partial Import• V17 Provides ability to import Programs, Routines and NEW Add-on Instructions on-line with a running controller– – – – NEW programs, routines and add-on instructions can be added Existing Programs and routines can be replaced New tags and UDTs are created as needed Name collisions are detected automatically and user prompted to rename or bind to existing components – The data values in the controller are maintained and new tags will have their values initialized from the import fileNEW Add-on Tags Instruction User-Defined Routine Datatype Program Data “.L5X” File• Permits ability to manipulate code off-line and deliver to controller later– ...vs. on-line editing where you must be connected – With some extra effort, existing Add-on Instructions can be replaced• Must use the following versions of RSLinx to use this feature– RSLinx Classic V2.54.00 or greater – RSLinx Enterprise V5.17.00 or greater2010/12/24RSLogix 5000 Multi-Lingual Project Documentation with Language Switching• V17 Extends RSLogix 5000 to manage multiple local language documentation sets– User has control over how many are created – Supports both single (European) and double byte (Unicode / Asian) character sets – Translation can occur manually within RSLogix 5000 of externally via a Unicode Text (txt) file that is formatted with tab-separated values• RSLogix 5000 allows you to switch the documentation view to the desired language– This is independent from the language software displays on its menus and help• Valuable for companies with multi-national business– Standardize systems internationally – Use the same base project in multiple countries – Draw resources globally to develop and support2010/12/24Multi-Lingual Description / Comments in a RSLogix 5000 Project – Import/Export• Use export/import to manipulate project document outside of RSLogix 5000– Tab Separated Value (.txt) Unicode text file• Use off-the-shelf tools to do offline translation, like Microsoft Excel– Allows for easier translation process and spell checking• Share the project information with others– Valuable for 3rd party translation – Outsource translation2010/12/24Runtime Detection of Controller Modifications• With V17, the 1756 ControlLogix L6x1 and GuardLogix L6xS1 Controllers track on-line changes via an internal log and with change counters– Logs type of change and PC Identity of user making the change – Stores a list of changes to CompactFlash card for later review – Programmatically accessible (GSV Instruction) counters increment when a user modifies a running controller• Provide indication that changes have occurred and post mortem of where the changes are and by whom via the log • Valuable for FDA regulated applications that need to know the applications has been modified1Initially Limited to ControlLogix L6x and GuardLogix L6xS ControllersChange Change Change Change Log Counters Log Counters2010/12/24LD Instruction Parameter Display Optimization Options• New workstation options provide more control over how instructions are displayed in Ladder Diagram– Increases the amount of information that can fit on a display (reduced white space) – Improves readability• Four new options:– – – – Include* / hide instruction description line Show instruction parameters in a flat list* or inputs left and outputs right Control when left/right presentation is used for AOIs or all instructions Animate Boolean tags via highlighting or via separate value*• * Default today2010/12/24New Options Maximize Screen ContentLegacy faceplate style New optional faceplate style• • • •2010/12/24Reduced instruction display space Easily determine inputs from outputs InOut parameters use a different color from inputs Animation of BOOL tags via color rather than valuesNew Advanced Process Control Instructions• RSLogix 5000 V17 provides three new optional advanced process control (APC) instructions– Internal Model Control (IMC) – Compares actual process error against error calculated by an internal first order lag plus deadtime model – Coordinated Control (CC) - Controls a single process variable by manipulating as many as three different outputs – Modular Multivariable Control (MMC) - Controls two process variables to their setpoints using up to three controller outputs – Useful for applications with multiple interacting inputs/outputs or with long deadtimes0.0 PV 0.0 SPProg 0.0 SPCascade 0.0 0.0 0.0 0 00.0 0.0 0.0 0.0 0.0 0.0 0 0 0 0 0 0 ProgCV3AutoReq 0 ProgCV1ManualReq 0 ProgCV2ManualReq 0 ProgCV3ManualReq 0 ProgCV1OverrideReq 0 ProgCV2OverrideReq 0 ProgCV3OverrideReq CV3Override CV2Override 0 CV1Override 0 CV3Manual 0IMC_01 IMC Internal Model Control 0.0 CVEUCC_01 0.0...SPCC0ProgOperCoordinated Control 0...RatioProg 0.0PVCasRat 0 Auto 0 Manual 0 00.0 0.0 0.0CV1EU SPProg CV2EU0.0 0.0 0.0 CV3EU 0.0 SP 0 ProgOper 0 CV1Auto 0 CV2Auto 0 CV3Auto 0 0 0 0 CV1Override 0 CV2Override 0 CV3OverrideCVProg 0.00.0HandFB 0.0 MMC_01 CV1Prog• Instructions purchased separately and licensed per use– 9324-RLDAPCENE – provides a license to use the instructions in RSLogix 5000 and provides a license to use them in a single Logix controller - $3,000 US List Price – 9324-RLDAPCCLENE - provides a license to use the instructions in an additional controller (honor system for run-time license, may change in the future) - $1,000 US List Price0 CV3Prog Hand ProgOperReq Modular Multivariable Control 0 0 ProgProgReq ProgCasRatReq 0 CV1EU PV1 0 ProgOperReq 0 PV2 CV2EU ProgAutoReq ProgCV1AutoReq 0 0 SP1Prog CV3EU ProgManualReq ProgCV2AutoReq 0 0 SP2Prog SP1 ProgOverrideReq ProgCV3AutoReq 0 0CV1Prog SP2 ProgHandReq ProgCV1ManualReq 0 CV2Prog ProgOper ProgCV2ManualReq 0 CV3Prog CV1Auto ProgCV3ManualReq 0 ProgProgReq CV2Auto ProgCV1OverrideReq 0 ProgOperReq CV3Auto ProgCV2OverrideReq 0 ProgCV1AutoReq ProgCV3OverrideReq CV1ManualMMC ProgProgReq CV2Prog Override ...0.0 CV1Manual 0.0 CV2Manual 0 0 0 0 0 0 0CV3ManualProgCV2AutoReqCV2Manual2010/12/24Advanced Process Control Instructions Internal Model Control (IMC)• Controls a single process variable by manipulating a single output • Compares actual process error against error calculated by an internal first order lag plus deadtime model • Built-in autotuner makes setup easier • Suitable for long deadtime processes which are difficult to control with standard PID loopsIMC_01 IMC Internal Model Control 0.0 PV 0.0 SPProg 0.0 SPCascade 0.0 RatioProg 0.0 CVProg 0.0 HandFB 0 ProgProgReq 0 ProgOperReq 0 ProgCasRatReq 0 ProgAutoReq 0 ProgManualReq 0 ProgOverrideReq 0 ProgHandReq Hand Override 0 Manual 0 Auto 0 CasRat 0 ProgOper 0 SP 0 CVEU 0.0 0.0 ...2010/12/24Advanced Process Control Instructions Coordinated Control (CC)• Controls a single process variable by manipulating as many as three different outputs • Target values and priorities for outputs are used to optimize your process • Compares actual process error against error calculated by internal first order lag plus deadtime models for each output • Outputs not currently controlling (held at target or in manual) are used as feedforward signals • Built-in autotuners make setup easierCC_01 CC Coordinated Control 0.0 PV 0.0 SPProg 0.0 CV1Prog 0.0 CV2Prog 0 CV3Prog 0 ProgProgReq 0 ProgOperReq 0 ProgCV1AutoReq 0 ProgCV2AutoReq 0 ProgCV3AutoReq 0 ProgCV1ManualReq 0 ProgCV2ManualReq 0 ProgCV3ManualReq 0 ProgCV1OverrideReq 0 ProgCV2OverrideReq 0 ProgCV3OverrideReq CV3Override CV2Override 0 CV1Override 0 CV3Manual 0 CV2Manual 0 CV1Manual 0 CV3Auto 0 CV2Auto 0 CV1Auto 0 ProgOper 0 SP 0 CV3EU 0.0 CV2EU 0.0 CV1EU 0.0 0.0 ...2010/12/24Advanced Process Control Instructions Modular Multivariable Control (MMC)• Controls two process variables to their setpoints using up to three controller outputs. • Target values and priorities for outputs are used to optimize your process. • Compares actual process errors against errors calculated by internal first order lag plus deadtime models for each output-toinput relationship. • Outputs not currently controlling (held at target or in manual) are used as feedforward signals. • Built-in autotuners make setup easier.2010/12/24 MMC_01 MMC Modular Multivariable Control 0.0 PV1 0.0 PV2 0.0 SP1Prog 0.0 SP2Prog 0.0 CV1Prog 0.0 CV2Prog 0 CV3Prog 0 ProgProgReq 0 ProgOperReq 0 ProgCV1AutoReq 0 ProgCV2AutoReq 0 ProgCV3AutoReq 0 ProgCV1ManualReq 0 ProgCV2ManualReq 0 ProgCV3ManualReq 0 ProgCV1OverrideReq 0 ProgCV2OverrideReq 0 ProgCV3OverrideReq CV3Override CV2Override 0 CV1Override 0 CV3Manual 0 CV2Manual 0 CV1Manual 0 CV3Auto 0 CV2Auto 0 CV1Auto 0 ProgOper 0 SP2 0 SP1 0.0 CV3EU 0.0 CV2EU 0.0 CV1EU 0.0 0.0 ...SFR Instruction Filters Routine Types and Step Names• With V17, the SFR instruction (Sequential Function Chart Reset) operand selection pulldown menus have been enhanced to filter just SFC routine types and SFC_STEP tag types • Previously, customers had to browse through all routines and tag types, which was time consuming2010/12/24SFC Step Timer ACC time Chart Pause Management• Logix timers store a portion of the wall clock with each scan and compare to the value from the last scan, The ACC value is then updated by the difference– When an SFC chart is paused, and then released, all of the timers jump forward by the amount of time of the pause • This is valuable for operations that consider the pause time as part of the process • Application code could be used to buffer the timer ACC and restore it after a release to ignore the chart pause duration – Many applications want the timers to pick up where they were at the point of the pause (ignoring the pause time)• This release now provides an option to control how the step timers will treat the pause– Options to Ignore or count the pause time – Provides more flexibility to control a wider range of applications2010/12/24SFC Chart Paused State Via GSV Instruction• With release v17, we are giving the user the ability to determine via GSV instruction an SFC chart paused state programmatically • Customers can now have either:– The program detect the situation and take corrective action or – Send the state to an HMI for user interface display.2010/12/24Tag’s Description Added to Tooltips in FBD Editor• With V17, the tooltips in the FBD editor now always include the tags’ descriptions • Provides improved ease-of-use when customers turn off “Show Tag Descriptions” in the Workstation Options– Descriptions may be turned off to reduce clutter on FBD sheetsTag’s description added to tooltip2010/12/24 GuardLogix V17 Safety Enhancements• 20 TÜV / BG Certified Safety Application Instructions– – – – – 9 Metal Forming Instructions (BG) 3 Muting Instructions (Light Curtains) 6 New Dual Channel Instructions Safety Mat 8 Position Mode SwitchMore Information2010/12/24 Dual Channel Application Instructions• Next generation of certified application instructions– – – – – – DCI – Start DCI – Stop DCI – Stop with Test DCI – Stop with Test & Lock DCI – Stop with Test & Mute DCI - Monitor• Focused on three main safety “jobs”– Start – Stop – Monitor• Easier to use • Better diagnostics2010/12/24 Metal Forming Instruction Suite• BG Certified Mechanical Press Application Instructions– EN 692 – ANSI B11.1 – CSA Z142.02– 10 Metal Forming Instructions • Crankshaft Position Monitor • Clutch Brake Inch Mode • Clutch Brake Single Stroke Mode • Clutch Brake Continuous Mode • Camshaft Monitor • Main Valve Control • Auxiliary Valve Control • Manual Maintenance Valve Control • Two Hand Run Station • 8 Position Mode Selector2010/12/24 Muting Suite and Safety Mat• 3 Certified Muting Instructions– Two Sensor Asymmetrical – Two Sensor Symmetrical – Four Sensor Bidirectional– Superior Safety for Conveyor related applications• Light Curtains • Laser Scanners• Safety Mat Instruction– Eliminates the need for a safety mat controller. – Directly connect safety mats to 1791DS, 1791ES and 1732DS safety I/O.2010/12/24IA Safety Accelerator – System Design Guidelines/Tools• A safety control system methodology assisting in device configuration and supporting safety logic tasks. • A device selection guide based on safety requirements.2010/12/24IA Safety Toolkit Preconfigured Status and Diagnostic Faceplates/AOIs• FactoryTalk View Faceplates for GuardLogix Controller and Safety I/O Blocks including companion Logix Add-On Instructions.Preconfigured FaceplateCompanion Add-On Instruction2010/12/24Preconfigured Status and Diagnostic Faceplates General Faceplate Components• Faceplates are single on-top displays incorporating object visibility control to create multiple views based on toolbar buttons and device status.Header Object Group with configurable ASCII Display for application specific faceplate identification Close Button Operator toolbar for navigating to different views of the faceplateController or device status/diagnostic indicator objects including configurable description objects. Operator action button objects specific to faceplate view.2010/12/24Preconfigured Status and Diagnostic Faceplates Toolbar Components• Operator toolbar allows navigation to different views of the faceplate.Alarm button allows operator to view fault descriptions and action views. The button icon will flash yellow indicating an active fault/alarm event. Configuration button will allow operator to launch a configuration view or allow object description editing directly on current view. Faceplate specific buttons allow navigation to status/diagnostic views associated with the specific device. This example includes (3) buttons providing access to Safety I/O block inputs and outputs. The “IN 0-7” is grayed indicating button is currently inactive and status view section below is displaying Safety I/O block inputs 0 thru 7. Help button initiates navigation to a help view specific to current view providing operator with indicator color codes, description explanations, and button action information.2010/12/24 Controller Organizer Report• Extends RSLogix 5000’s printed output to include the contents of the controller organizer– – – – Provides an overview of the application structure and configuration Includes component and associated descriptions Serves as a sort of table of contents for the rest of the listing Helps to provide a more comprehensive project documentationController: my_controller This is my controller description Controller Fault Handler my_controller_fault_program This is my description for my controller fault program my_controller_fault_routine this is my description for my controller fault routine Power-Up Handler power_up_handler_program, This is my description power_up_handler_routine Tasks My_Event_Task, This is an event task aaaaa bbbbb ccccc ddddd eeeee fffff ggggg hhhhh iiiii jjjjj kkkkk lllll mmmmm nnnnnn ooooo ppppp qqqqq rrr my_event_task_program This is my description for my event task program my_event_routine MainTask This is my main task description MainProgram This is my description for my program My_Main_SFC_Routine This is my description for my_main_sfc_routine My_Fault_SFC_Routine This is my description for my_fault_sfc_routine My_RLL_Routine This is my description for my_rll_routine My_FBD_Routine This is my description for my_fbd_routine My_ST_Routine This is my description for my_st_routine MyEquipmentPhase2010/12/24Multi-Axis Programmable Jerk• Programmable jerk added in v16 is being extended in this release to also support multi-axes moves instructions (MCCM, MCLM & MCS)– Adds programmable jerk configuration on faceplates – Supported for termination types 0 through 3• Configurable Maximum jerk rates are accessible programmatically via GSV/SSV instructions • Allows user to optimize need for speed and smoothness by specifying acceleration and deceleration jerk rates on single and multi-axis moves2010/12/24 MCD and MCCD Motion Instructions Enhancements• Extended the functionality of the MCD instruction by allowing for the acceleration and deceleration jerk rates to be also changed for in process single-axis moves or jogs • Same extensions apply to the MCCD instruction allowing for the acceleration and deceleration jerk rates to be changed for multi-axis coordinated moves or jogs • Lastly, added enumeration to the MCCD instruction so that the "Active & Pending" motion can be changed dynamically2010/12/24Forcing and Toggle Bit Added to Quick Watch Window• In this version of RSLogix 5000, we have ported the Force Mask available in the Tag Monitor dialog also into the Quick Watch window • Additionally, we have added the ability to toggle bits in the Quick Watch window • Improves ease of use and reduces steps required to force and toggle tags2010/12/24Tag Monitor Enhancement - Alarm Grid Display Mode• Quickly evaluate alarm status and current values at-a-glance • Make faster decisions for Alarm Troubleshooting • Supports both ANALOG_DIGITAL and ALARM_ANALOG datatypesUse this button to select datatype2010/12/24Search Item Browser Supports Tag Name Typeahead/Autocompletion• With this release, the Search Item Browser supports tag name typeahead– Browser is available from Find and Replace dialogs• Improves ease-of-use by speeding-up tags selectionNew control supporting typeahead/autocompletion2010/12/24ControlFlash V7.0 – Simplifies Firmware Management• Allows ControlFlash to run with no GUI – Reduce training requirements of technicians – Improve time to commission a machine or performing field upgrades • Command Line Execution – Allows command line execution of ControlFlash for simple Batch File flashing or custom VB app • Script Execution – Allows creation of an ASCII script for ControlFlash to follow when commissioning or upgrading a machine – Script lists the Modules to flash, firmware revs, and path requirements – Multi- Threaded to allow ControlFlash to flash up to 5 modules simultaneously for improved performance • Success/Fail Programmatic Feedback – Return strings for command line execution as well as History Log file for interrogation of success/fail flash eventsExample of custom VB application2010/12/24Coordinated System Time (CST) Master Existence Check On Download• With v16 and earlier, only a verify warning was reported on download to users if the CST master was not designated • Without a designated CST master:– Axes in motion group would not function – Safety controller will fault on transition to RUN if a CST Master is not designatedSafety controller dialog– CST master is required for applications with Motion Groups and Safety controllersStandard controller dialog• With 17, users can designate target controller as the CST master directly from the download dialog– Supports standard and safety controllers• Improves user experience and reduces chances of configuration errors during start-up phase2010/12/24 Tag’s Descriptions Length Extended• Up to v16 of RSLogix 5000, tags’ description may have been represented with a maximum of 128 characters in length • With release v17, we are extending the maximum number of characters to 512– Maximum length applies also to Unicode characters• Allows for extended descriptions or descriptions in multiple localized languages for the same tag2010/12/24Produced/Consumed Tag Structures Status• With v17, users will be able to include status information when producing/consuming tags • P/C tags must be structures– First structure member must be of datatype CONNECTION_STATUS; this datatype includes: • RunMode • ConnectionFaulted• Provides for easy data quality validation by accessing included status data • Must use RSNetWorx v9.0 for ControlNet or greater to use this feature2010/12/24 Verification Warning If Forces Are Present• In release v17, we are adding the option in the software to warn the user during verification and download that forces are present in the project • The option is enabled by default • Provides users with more detailed information on application during debugging and maintenance2010/12/24 Verification Warning If AFI Are Present• In release v17, we are adding the option in the software to warn the user during verification and download that AFI (Always False Instruction) instructions are present in the project • The option is enabled by default • Provides users with more detailed information on application during debugging and maintenance2010/12/24 RSLogix 5000 System Install Enhancement• System install introduced in v16 is being enhanced in release v17 to allow for installation of other RS products– RSLogix 5000 label indicates that this is the first disc to install – Customer picks RS Products, components, firmware kits and tools to install and they are automatically installed in the right order• Reduces the total time to install and improves user experience2010/12/24。

Appendix I:Index to Video ExamplesAUs and combinations that are illustrated with MPEG video are sorted in AU order in the table below. Each video is cross-referenced to the filename of the video clip, the Manual page containing the scoring commentary, and the sequenceof the clip in the continuous MPEG master video (roughly the order of appearance in the Manual and in the table of scor-ing commentaries). (The digital transfer of the original film examples does not contain the newer examples.) The video clips are in the Examples/Video directory of the CD ROM. (An identical set of video clips in QuickTime® format can be found in the Examples/Video/QT directory.) The continuous MPEG is in the Manual directory. Online viewers can clickth e hyperlinks in the column “Filename of Video Clip” to see the video, and the links in the “Page Number of Scoring Commentary” to see the commentary.AUs Illustrated 11+21+2+41+2+51+4244+555+766+7 (i)6+7 (ii)6+7+126+12 (i)6+12 (ii)6+156+4E3, 7+43E Filename of VideoClipAU1.mpgAU1_2.mpgAU1_2_4.mpgAU1_2_5.mpgAU1_4.mpgAU2.mpgAU4.mpgAU4_5.mpgAU5.mpgAU5_7.mpgAU6only.mpgAU6_7.mpgAU6.mpgAU67_12AU6_12B.mpgAU6_12o.mpgAU6_15.mpgAU6_7_43.mpgPage Numberof ScoringCommentarypage 413page 416page 416page 416page 415page 413page 413page 415page 414page 415page 414page 414page 414page 423page 422page 422page 424page 416Sequence inMPEGMaster21112131031849--6-37-4614Index to Video Examples7 (i) 7 (ii) 7+12 8+26 9 AU7.mpgAU7only.mpgAU7_12o.mpgAU8_26.mpgAU9.mpgpage 414page 414page 422page 429page 4175--70159+16+25 AU9_16.mpg page 418 209+171010+12+16+25 10+12+2510+1410+1510+15+1710+16+2510+1710+17+2310+20+2510+22+2510+23+25 AU9_17.mpgAU10.mpgAU101216.mpgAU101225.mpgAU10_14.mpgAU10_15.mpgAU101517.mpgAU10_16.mpgAU10_17.mpgAU101723.mpgAU102025.mpgAU102225.mpgAU102325.mpgpage 418page 417page 423page 423page 420page 419page 419page 418page 419page 427page 421page 426page 4262216413931232621246133675311 AU11.mpg page 421 3512 (i)12 (ii)12+1512+15+17 12+16+25 12+1712+17+23 12+2312+2412+2612+27131414+17 AU12.mpgAU12only.mpgAU12_15.mpgAU121517.mpgAU121625.mpgAU12_17.mpgAU121723.mpgAU12_23.mpgAU12_24.mpgAU12_26.mpgAU12_27.mpgAU13.mpgAU14.mpgAU14_17.mpgpage 421page 422page 424page 424page 423page 424page 427page 426page 426page 423page 424page 422page 420page 42036-45474044605455424338283214+231515+1715+17+23 15+2316+20+25 16+22+25 16+23+25 16+25 (i) 16+25 (ii) 1717+2317+241818+23192020+23+25 20+2620+272122+23+25 22+252323+26242829303132333435 AU14_23.mpgAU15.mpgAU15_17.mpgAU151723.mpgAU15_23.mpgAU162025.mpgAU162225.mpgAU162325.mpgAU16.mpgAU16ii.mpgAU17.mpgAU17_23.mpgAU17_24.mpgAU18.mpgAU18_23.mpgAD19.mpgAU20.mpgAU202325.mpgAU20_26.mpgAU20_27.mpgAU21.mpgAU222325.mpgAU22_24.mpgAU23.mpgAU23_26.mpgAU24.mpgAU28.mpgAD29.mpgAD30.mpgAU31.mpgAD32.mpgAD33.mpgAD34.mpgAD35.mpgpage 426page 417page 419page 427page 428page 421page 429page 429page 418page 418page 417page 427page 427page 425page 428page 429page 419page 428page 420page 420page 429page 428page 425page 425page 428page 425page 425page 430page 430page 430page 430page 430page 431page 431561825576334686919-1758594862-2766293071654950645152-------Index to Video Examples3637 38; 39 46M55 M57 M59 M60 M61 M68 M69 M83 AD36.mpgAD37.mpgAU38_39.mpgAU46.mpgM55.mpgM57.mpgM59.mpgM60.mpgM61.mpgM68.mpgM69.mpgM83.mpgpage 431page 431page 431page 415page 432page 432page 433page 433page 433page 432page 432page 432--727--------Appendix II:Scores for ReferenceExample Images and VideosThe example images and videos portray AUs to illustrate AU descriptions1. Although every attempt was made to use examples that show only the AUs intended to be represented, this goal was not always achieved because of the difficulty of eliminating all other actions from the performance of the intended AUs. Below are complete FACS scores for each of the example images. These scores contain the intensity score, which is usually not emphasized in the AU descriptions of Section A, a unilateral prefix if unilateral or an asymmetry score (a scoring option) if asymmetrical. These scores allow the careful student to determine more precisely what causes certain appearances in the example images. An example may inadvertently contain a score for an AU that has not been previously discussed. If so, focus on the intended AUs and return to the example later when the as yet unfamiliar AU is discussed. The scores for the examples will help to under- stand the relevance of the examples for scoring decisions made in practical scoring situations after FACS training is com- plete. The commentaries present the evidence for the AUs scored and the intensity assigned, and discuss why other AUs were not scored. Any difficulties in scoring are highlighted. In the scoring of the video, the scores pertain to the maximum extent of the movement in the clip and include all the actions of significance, regardless of the complexities that might be introduced by the event scoring in Chapter 11.If you are reading online, click the thumbnail to view the image in an external viewer, click the page number link to move to the Manual page containing the image, or click on the “(Get Neutral)” link to see the neutral for the person in an exter- nal viewer.Image Name &Example Image Page Numberpage 465 FACS ScoreRationaleThe face is not showing any action, often called a neutral face. Theface is not actually at rest because the eyes are open, the jaw isclosed, etc., but no AU can be scored. This neural face is the base-line for scoring AUs in the example images of this person, andsimilar states of “neutral” faces are used most often as baselines inactual scoring situations, although other baselines can also be used,as discussed in Chapter 11.1. The images of the AU examples for FACS were photographed and scored for the first edition under the Minimum Requirements andCo-occurrence rules of the original FACS Manual. For this version of the Manual, these photos were scanned into digital images, re- cropped, and then re-scored using the Intensity Criteria approach. Differences in the scoring techniques, especially eliminating Min-imum Requirements, changed the rules that originally assessed the quality of the photos as examples. Minor deviations from the intended actions occur in the examples, but the portrayals do not contradict the AU’s description.Scores for Reference Example Images and Videos4i page 466(Get Neutral)4ii page 466(Get Neutral)w0 page 465(Get Neutral)w4 page 465(Get Neutral) V4C+38A4D4B+38ASlight to marked vertical wrinkles appear in the glabella and theeyebrows are pulled together markedly. The inner parts of the eye-brows are pulled down a trace on the right and slightly on the leftwith traces of wrinkling at the corners. Notice the skin bunchingthat begins above the middle of each eyebrow and continues moremedial making shallow waves, a sure sign of AU 4, and the bunch-ing of skin in the glabella. The 4 meets criteria for the C level onthe basis of the pulling together. Because the skin bunching abovethe eyebrows is a trace greater on the left, and the left eyebrow islowered a trace more, asymmetry is L1 and the V prefix isassigned to the 4. How about AU 1 because of the arch in the firsthorizontal wrinkle above the glabella? This change is due to thebunched skin in the glabella bending that wrinkle up. ConsideringAU 5 because of the harsh quality in the eye? There is no hard evi-dence for 5, which you can confirm by covering the eyebrows witha card. The trace of nostril flaring in the changed shape of thethinned nostril wings is sufficient for 38A.Severe vertical wrinkles and skin bunching between the eyebrows,severe drawing together of the eyebrows, and severe to extremeeyebrow lowering put this 4 at the D intensity. Both lowering anddrawing together of the eyebrows has increased from image 4i, butthe lowering has increased much more. Notice that the other signsof 4 listed for image 4i have also increased. The arch in the lowesthorizontal furrow of the forehead has straightened because of thelowering and pulling down of the glabella. Again, there is no evi-dence of AU 5 when looking closely at only the eyelid. The darkshadow between the lips should not entice the coder to score 25because 25 requires certainty, but they are certainly closed.The neutral face shows the appearance of a lowered, slanting eye-brow, a permanent feature. Also, note the furrows beyond the lipcorners, deepened parts of the nasolabial furrow. These furrowsand the wrinkling in the forehead are asymmetrical. The eye coverfold is virtually hidden, making action of 5 more difficult to detect.The eyebrows are slightly lowered and pulled together and slightvertical wrinkles form between the eyebrows, sufficient to score4B. The marked thinning and flaring of the nostrils is sufficient toscore 38A in a still image.1 page 466(Get Neutral)2 page 466(Get Neutral)5i page 467(Get Neutral)5ii page 467(Get Neutral)w5i page 467(Get Neutral)1B+38AV2C+38A5B5E5B+38AThe inner corners of the eyebrows are lifted slightly, the skin of theglabella and forehead above it is lifted slightly, and wrinklesdeepen slightly and a trace of new ones form in the center of theforehead. Someone might contend that either the wrinkling or theinner brow raise is marked, and therefore the score should be 1C,but compare these changes to those in the image 1+2 below andother images where AU 1 is at much greater intensity and re-cali-brate. There is no sign of AUs 2, 4, 5, 6, or 7 whatsoever. In thelower face, nostril flaring evident in the raised and thinned nostrilwing and increased nostril size is marked, A level in a still image.The outer part of the eyebrow raise is pronounced. The wrinklingabove the right outer eyebrow has increased markedly, and thewrinkling on the left is pronounced. Increased exposure of the eyecover fold and skin is pronounced. The score is 2C.There is nosign that the inner corners of the eyebrows are raised, althoughthey may be drawn laterally, and wrinkling in the center of theforehead has not changed in shape or position. Although thesewrinkles may have deepened somewhat, the changes in the outerpart of the wrinkles due to 2 can explain this change. Thus, AU 1 iseliminated.The greater number and depth of wrinkling on the leftmakes the asymmetry trace (L1), so assign the prefix V. The slightchanges in the nostril again indicate 38A.AU 5 is hard to see here because the eyebrows are set low and theeye cover fold has little exposure. The upper eyelid is pulled up,the medial part virtually disappearing into the revulsion margin ofthe eye cover fold. More sclera around the upper part of the iris isrevealed The inner corner of the eye shows more mucosa andsclera. In the neutral photo, no sclera is exposed and the upper eye-lid covers the top part of the iris, but here, we can extrapolate fromthe shape of the upper eyelid that virtually the entire iris isexposed, if we could see under the eye cover fold obscuring the topof the iris. This change is sufficient to score 5B on this person.The upper eyelid is raised to about the maximum and a maximumamount of sclera shows above the iris. The bulging, staring appear-ance is present without doubt. This evidence is sufficient to score5E. The lower eyelid is somewhat raised and straightened, cover-ing more of the iris, but this is due to the maximum 5 pulling up onthe lower eyelid; but there is no 7 in this item. (A 7 would wrinklethe lower eyelid and pull it up onto the eyeball, causing a bulgeand straightening it much more -- see item 7 below.)The upper eyelid is raised to reveal virtually the entire top of theiris, sufficient to score 5B as the top of the iris is covered in neu-tral. Slight flaring and thinning of the nostrils is sufficient to score38A.Scores for Reference Example Images and Videosw5ii page 467(Get Neutral)7 page 468(Get Neutral)6 page 468(Get Neutral)w7 page 468(Get Neutral)5E7CG7D+6C4A+7CThe upper eyelid is raised to reveal sclera in the maximum range,evident on the right side, sufficient to score 5E. Notice that themaximum 5 has stretched and lifted the lower eyelid a trace, butthere is no action of AU 7 in this item.The lower eyelid is raised markedly and straightened slightly, caus-ing slight bulging, and the narrowing of the eye aperture is markedto pronounced, sufficient to score 7C. No other actions are detect-able in this item.The infraorbital triangle is raised markedly, pushing skin below theeye up, slightly deepening the nasolabial furrow, and pulling up theskin of the upper lip a trace. Marked crow’s feet wrinkles form atthe eye corners as the lateral top of the infraorbital triangle israised and the lateral part of the eyebrow is lowered slightly,changing the shape of the eye cover fold as the outer ring of orbic-ular muscle constricts. This evidence is sufficient to score 6C.Even though the action of 6 is expected to push up skin below theeye and wrinkle the lower eyelid, the eyelid in this item is pulledfar up on the eyeball, beyond the effect that 6 alone can produce,causing severe bulging and wrinkling of the lower eyelid and nar-rowing of the eye aperture. Note how the skin of the lower eyelidis drawn markedly to the inner corner of the eye, narrowingseverely the angle around the lacrimal gland. The upper eyelid islowered, contributing to the changes in the eye cover fold pro-duced by the action of 6. This evidence is sufficient to score 7D.Both the wrinkling and the narrowing due to 7 are a trace greateron the right, or R1, so the prefix G is assigned. Even though thecorners of the lips are turned up a trace and the nasolabial furrowbeyond the lip corners is pulled laterally a trace, these effects areprobably due to the AU 6 pulling, and no AU 12 is scored here,lacking evidence from the movement.The lower lid is raised and straightened markedly on the eyeball,causing pronounced bulging and narrowing of the eye aperture,sufficient to score 7C. Notice how the skin of the lower eyelid isdrawn in towards the inner eye corners to affect the angle of theeyelid around the lacrimal duct. A trace of vertical wrinklingbetween the eyebrows, a trace of brow lowering, especially theright, is sufficient to score 4A.w6 page 468(Get Neutral)43i page 469(Get Neutral)43ii page 469(Get Neutral)43iii page 469(Get Neutral)7E page 469(Get Neutral) 6C+7D43B43D43E7EThe raise of the infraorbital triangle is pronounced, the deepeningof the nasolabial furrow is marked, and skin of the upper lip israised a trace. Pronounced crow’s feet wrinkles form at the eyecorners as the lateral top of the infraorbital triangle is raisedseverely, and the infraorbital furrow is deepened severely. This evi-dence is sufficient to score 6C. The action of 6 pushes up skinbelow the eye, but the eyelid in this item is pulled far up on theeyeball, beyond the effect that 6 alone can produce, causing severebulging and wrinkling of the lower eyelid and severely narrowingthe eye aperture. Note how the skin of the lower eyelid is drawnseverely to the inner corner of the eye, narrowing the angle aroundthe lacrimal gland. This evidence is sufficient to score 7D. Theeyebrows may be lowered a trace, but the 6 can explain this effect.The upper eyelid is relaxed and drooping down slightly, sufficientto score 43B. Note that the shape of the lower eyelid is littlechanged from neutral and there is no additional wrinkling. Be sureto compare the appearance of relaxing the upper eyelid in 43 tothat resulting from the tensing of the orbicular muscle that isapparent in the 6 and 7 items above.Again, this appearance results from relaxing the upper eyelid, andthe eyelids are almost together (closed), but the gap between themcan still be seen, especially in the medial parts and around the lac-rimal gland. This evidence is sufficient to score 43D. Compare thisappearance to the next item, which shows the eyelids closed.The eyes are closed in 43E. Notice that when the eyes are closed,you see the upper eyelashes laying on the skin of the lower lid andlittle or nothing of the lower eyelashes. No sclera or mucosa can beseen. No evidence of any other action is present in this example.The lower lid is pulled and stretched maximally on the eyeball,hiding most of the iris, and bulging and tensing of the lower eyelidis extreme. This evidence is sufficient to score 7E.Note that without a counteracting tension in the upper lid, the eyewould close and be scored 7E+43E, but the tension in the uppereyelid is always active to keep the eyes open, so there is no need toscore AU 5 in such an ordinary situation, and the appearancechanges here do not meet any of the guidelines for scoring AU 5.When both 7 and 5 act so that 5 is scored, the appearance is differ-ent from this item, as you can see in the 5+7 item below.Scores for Reference Example Images and Videos4+5 page 470(Get Neutral)w4+5 page 470(Get Neutral)5+7 page 470(Get Neutral)1+4i page 470(Get Neutral)1+4ii page 471(Get Neutral)4C+5C4C+5B+38A5D+7C1C+4C+38A1C+4D+38AThe inner parts of the eyebrows are pulled together slightly form-ing slight vertical wrinkling, and are pulled down markedly, form-ing slight horizontal wrinkles at the inner corners of the eyebrows,sufficient to score 4C. The upper eyelid is raised and tensed againstthe downward movement of the eye cover fold caused by the low-ered eyebrows, and more sclera shows at the upper, side parts ofthe iris, indicating AU 5. Because the 5 occurs with 4, the specialintensity guidelines for 5 with 4 are used to score intensity. We cansee that more of the top part of the iris is revealed than in neutraland the harsh stare is at least marked, so 5C is scored.The eyebrows are markedly lowered and marked vertical wrinklesform between the eyebrows, sufficient to score 4C. The upper eye-lid appears raised from the increased exposure of sclera around theiris. Tension of the upper lid against the eye cover fold is evidentas AU 4 pushes down and AU 5 pushes up. The eyes have a glarethat is not present in the w4 example (cover the eyebrows to com-pare). This evidence is sufficient to score 5B. The marked thinningand flaring of the nostrils is sufficient to score 38A in a still image.The upper eyelid is raised to reveal much more than a hairline ofsclera around the top of the iris, which is partially covered in neu-tral. At least a severe amount of sclera beyond the guideline for theB intensity (virtually all of the top of the iris) is revealed, but not amaximum, sufficient to score 5D. The lower eyelid is raised andstraightened markedly on the eyeball forming a marked bulge, andskin is drawn to the inner eye corner, sufficient to score 7C.The increase in wrinkling in the center of the forehead is marked topronounced, and the raising of the inner corners of the eyebrows ispronounced, sufficient to score 1C. The eyebrows are pulledtogether markedly, and marked vertical wrinkling and bulgingappears between them. Using the guidelines for AU 4 in the com-bination of 1+4, this evidence is sufficient to score 4C. Notice howstraight the eyebrows are compared to the example for AU 1, inthis table above, because the 4 is pulling down the center of eacheyebrow while the 1 is raising the inner corner, which decreasesthe curvature of the eyebrow. The markedly thinned and flarednostrils are sufficient to score 38A.The same signs are apparent in this items as in the previous, but theactions are more intense. The increase in horizontal wrinkling inthe center of the forehead and the raising of the inner corners of theeyebrows are pronounced, about the same as in the previous item.Yet, there is a more bulging, bunched, and knotted appearance tothe center of the forehead because the stronger AU 1 is counter-acted by a stronger AU 4, shown in the severe vertical wrinklingand bulging and wrinkling between the eyebrows, the severe draw-ing together of the eyebrows, and the greater lowering of the eye-brow centers. Also, notice the straightness of the eyebrow and eyecover fold. This evidence is sufficient to score 4D, and the 1remains in the C intensity range. The markedly thinned and flarednostrils are sufficient to score 38A.j0 page 465(Get Neutral) 0 This neutral image serves as a baseline for the j images. Note thepermanent wrinkles in the forehead and at or below the eye cor-ners. Note the greater exposure of the eye cover fold and skin ofthe upper eyelid, compared to the other faces, that makes changesin the upper eyelid easier to detect. There is also more permanentbulging in the glabella than the other faces seen thus far.j1+4 page 471(Get Neutral) 1C+4D+L11B The inner corners of the eyebrows are raised slightly, and the hori- zontal wrinkling in the center of the forehead is increased mark-edly, sufficient to score 1C. The eyebrows are markedly to severelypulled together, forming severe vertical wrinkles and bulgingbetween the eyebrows, sufficient to score 4D (barely) using the cri-teria for 4 in the 1+4 combination. This example shows clearly 1)the triangular shape of the eye cover fold that often appears in 1+4,and 2) how the inner corner of the eyebrow is pulled up by 1 andthe center is pulled down by 4. The middle part of the left nasola-bial furrow is deepened slightly and the skin of the left upper lip isstretched upward a trace, sufficient to score L11B.1+2 page 471(Get Neutral)1+2+4i page 472(Get Neutral)1D+W2D+25A+38A1C+W2C+4BIt should be immediately obvious from the eyebrow raise andwrinkling across the entire forehead that AUs 1 and 2 are involvedin this action, so use the Action Unit Combination description for1+2 to score these actions (or the section on combination 1+2+4,etc. if there were other AUs). This action is also asymmetrical. Theentire eyebrow is raised up extremely, wrinkles are extremely deep-ened and/or extended across the entire forehead, except on theouter right side where they are pronounced, and the eye cover foldis exposed extremely. There is no evidence whatsoever for 4, 5, 6,or 7, and although one might claim the upper eyelid is raised atrace, this change can be easily attributed to the lifting of the eyecover fold by 1+2. The lower face shows little change, except a slitof lip parting that is less than 2mm and a trace of nostril flaringevident in the thinned nostril wings and changed nostril opening.Because the 2 is C on the right and D on the left, and the differencein wrinkling is slight (asymmetry is L2), W is assigned as prefix to2.The raise of the entire brow, together with the flattening and pull-ing together of the eyebrows indicate the presence of 1, 2, and 4 sothe guidelines for scoring the combination 1+2+4 are appropriate.The entire brow is raised markedly, indicating the C intensity forboth 1 and 2, except that on the right side, the 2 is slight and thedifference between the sides is slight, indicating an asymmetryscore of 2 and a prefix of W. The slight pulling together appearsweaker than the raising, with only slight straightening and a traceof bulging between the brows, sufficient to score 4B.Scores for Reference Example Images and Videos1+2+4ii 1B+2B+4C+25A+ As in the previous item, the 1+2+4 scoring guidelines are used, butpage 472 (Get Neutral)j1+2+4 page 471(Get Neutral)1+2+5i page 472(Get Neutral)1+2+5ii page 472(Get Neutral)38A1B+2C+4C+5A+V11C1D+2D+5B1E+2E+5Ehere, the brow is less raised and more pulled together. The browraise, and the consequent deepening of the horizontal wrinkles isslight, indicating AUs 1 and 2 at the B intensity. Notice thatalthough the lateral parts of the eyebrows are not raised much morethan in neutral, the brow is very straight, indicating the tensionbetween a stronger AU 4 and AU 2. The pulling together of theeyebrows is pronounced with slight bulging between them, but amarked amount of knotting and twisting in the forehead. This evi-dence is sufficient for 4C. A slit of lip parting that is less than 2mmand a marked nostril flaring evident in the thinned nostril wingsand changed nostril opening is sufficient to score 25A+38A.Evidence of the raising of the entire brow is apparent in the slightto pronounced increase in horizontal wrinkling across the foreheadand the slight to marked raising of parts of the eyebrow. The eye-brows are drawn together slightly, forming marked wrinkling andbulging between the eyebrows, but the center of each eyebrow ispulled down at least markedly. Using the intensity guidelines in thedescription of the 1+2+4 combination, and weighing the evidencefor these AUs, the 1B+2C+4C intensity scores are assigned. Theraise of the upper eyelid is apparent in contrast to neutral, but notquite enough to score B, so 5A is scored. The nasolabial furrow isdeepened in the middle slightly to markedly, with some pulling ofthe skin in the upper lip, sufficient to score 11C. The 11 is strongeron the lefts, as the left lip is raised more and the left infraorbitalfurrow is deeper, a trace of a difference or the prefix V.The obvious eyebrow raise and wrinkling across the entire fore-head indicates AUs 1 and 2 are involved in this action, so the scor-ing guidelines for the 1+2 combination are appropriate. Theraising, wrinkling, exposure of the eye cover fold, and other signsof AUs 1 and 2 are severe to extreme, but not maximum, indicatingthe D intensity. The upper eyelid is raised to expose virtually theentire iris, which is covered in neutral, sufficient to score the Bintensity. Compare the effect of 5 in this item in exposing the iris tothe reveal of the iris in the previous two examples of 1+2+4 andthe item for 1+2, where 5 has not acted.As in the previous item, the guidelines for combination 1+2 areused, and the maximum raising, wrinkling, exposure of the eyecover fold, and other signs indicate AUs 1 and 2 at the E intensity.Likewise, the raising of the upper eyelid and exposure of scleraabove the iris is maximum, indicating 5E. Notice that the lowereyelid appears to have raised up in respect to the iris. This is attrib-utable to the effect of the maximum 5; no other sign of AU 7 ispresent.。