PCA85162TQ9001,1;中文规格书,Datasheet资料
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NXP Semiconductors
PCA85162
Universal LCD driver for low multiplex rates
7. Functional description
The PCA85162 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments.
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 18.
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NXP Semiconductors
2. Features and benefits
AEC-Q100 compliant for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 32 segment drives: Up to sixteen 7-segment alphanumeric characters Up to eight 14-segment alphanumeric characters Any graphics of up to 128 elements 32 4-bit RAM for display data storage Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption Extended temperature range up to 95 C 400 kHz I2C-bus interface No external components required Manufactured in silicon gate CMOS process
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SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16 A1 17 A2 18 SA0 19 VSS 20 VLCD 21 BP0 22 BP2 23 BP1 24
PCA85162T
Top view. For mechanical details, see Figure 26.
5. Block diagram
BP0 BP2 BP1 BP3 S0 to S31 32 VLCD BACKPLANE OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD VOLTAGE SELECTOR DISPLAY CONTROLLER
DISPLAY REGISTER
VSS
LCD BIAS GENERATOR
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NXP Semiconductors
PCA85162
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
S23 S24 S25 S26 S27 S28 S29 S30 S31
COMMAND DECODER
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
INPUT FILTERS
I2C-BUS CONTROLLER
SUBADDRESS COUNTER
SA0
A0
A1
A2
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Fig 1.
Block diagram of PCA85162
PCA85162
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rightRev. 2 — 16 June 2011
Table 3. Symbol SDA SCL SYNC CLK VDD OSC A0 to A2 SA0 VSS VLCD BP0 to BP3 S0 to S22, S23 to S31 Pin description Pin 10 11 12 13 14 15 16 to 18 19 20 21 22 to 25 26 to 48, 1 to 9 Type input/output input input/output input/output supply input input input supply supply output output Description I2C-bus serial data line I2C-bus serial clock cascade synchronization clock line supply voltage internal oscillator enable subaddress inputs I2C-bus address input ground supply voltage LCD supply voltage LCD backplane outputs LCD segment outputs
Product data sheet
Rev. 2 — 16 June 2011
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NXP Semiconductors
PCA85162
Universal LCD driver for low multiplex rates
6.2 Pin description
Fig 2.
Pinning diagram for TSSOP48 (PCA85162T)
PCA85162
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
PCA85162T/Q900/1 TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm
4. Marking
Table 2. Marking codes Marking code PCA85162T Type number PCA85162T/Q900/1
OUTPUT BANK SELECT AND BLINK CONTROL
CLK SYNC
PCA85162
CLOCK SELECT AND TIMING BLINKER TIMEBASE
DISPLAY RAM 40 × 4-BIT
OSC VDD SCL SDA
OSCILLATOR
POWER-ON RESET
PCA85162
Universal LCD driver for low multiplex rates
Rev. 2 — 16 June 2011 Product data sheet
1. General description
The PCA85162 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. It can be easily cascaded for larger LCD applications. The PCA85162 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes).