当前位置：文档之家 › PCF2127AT1,518;中文规格书,Datasheet资料

PCF2127AT1,518;中文规格书,Datasheet资料

  • 格式：pdf
  • 大小：515.87 KB
  • 文档页数：11

1. General descriptionThe PCF2127A is a CMOS 1 Real Time Clock (RTC) and calendar with an integratedTemperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768kHz quartz crystal optimized for very high accuracy and very low power consumption. The PCF2127A has 512bytes of general purpose static RAM, a selectable I 2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features.2. Features and benefitsTemperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy: ±3ppm from −15°C to +60°CIntegration of a 32.768kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, and seconds 512bytes of general purpose static RAMTimestamp functionwith interrupt capabilitydetection of two different events on one multilevel input pin (e.g. for tamper detection)Two line bidirectional 400kHz Fast-mode I 2C-bus interface (I OL =3mA at pin SDA/CE)3line SPI-bus with separate data input and output (maximum speed 6.5Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage pin Battery low detection functionExtra power fail detection function with input and output pins Power-On Reset Override (PORO) Oscillator stop detection functionInterrupt output and system reset pin (open-drain) Programmable 1second or 1minute interruptProgrammable countdown timer with interrupt capabilityProgrammable watchdog timer with interrupt and reset capability Programmable alarm function with interrupt capability Programmable square wave open-drain output pin Clock operating voltage: 1.2V to 4.2VLow supply current: typical 0.65μA at V DD =3.0V and T amb =25°CPCF2127AIntegrated RTC, TCXO and quartz crystalRev. 02 — 7 May 2010Product data sheet1.The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.Automatic leap year correction3. ApplicationsElectronic metering for electricity, water, and gasTimekeeping instruments with high precisionGPS equipment to reduce time to first fixApplications that require an accurate process timingProducts with long automated unattended operation time 4. Ordering information5. Marking Table 1.Ordering informationType number PackageName Description Version PCF2127AT/1SO20plastic small outline package; 20leads; body width 7.5mm SOT163-1Table 2.Marking codesType number Marking codePCF2127AT/1PCF2127AT6. Block diagram7. Pinning information7.1Pinning7.2Pin descriptionTable 3.Pin description of SO20 (PCF2127A)Symbol Pin DescriptionSCL1combined serial clock input for both I2C-bus and SPI-bus; mayfloat when SDA/CE inactiveSDI2serial data input for SPI-bus; may float when SDA/CE inactiveSDO3serial data output for SPI-bus, push-pullSDA/CE4combined serial data input and output for the I2C interface and chipenable input (active LOW) for the SPI-busIFS5interface selector inputconnect to pin V SS to select the SPI-busconnect to pin BBS to select the I2C interfaceTS6timestamp input (active LOW) with 200kΩ internal pull-up resistor(R PU)CLKOUT7clock output (open-drain)V SS8ground supply voltagen.c.9 to 12not connected; do not connect; do not use as feed throughTEST13do not connect; do not use as feed throughPFO14power fail output (open-drain; active LOW)PFI15power fail inputRST16reset output (open-drain; active LOW)INT17interrupt output (open-drain; active LOW)BBS18output voltage (battery backed)V BAT19battery supply voltage (backup)V DD20supply voltage8. Functional descriptionThe PCF2127A is a Real Time Clock (RTC) and calendar with an on-chip TemperatureCompensated Crystal (Xtal) Oscillator (TCXO) and a 32.768kHz quartz crystal integratedinto the same package.Address and data are transferred by a selectable 400kHz Fast-mode I2C-bus or a 3lineSPI-bus with separate data input and output (see Section9). The maximum speed of theSPI-bus is 6.5Mbit/s.The PCF2127A contains 30 8-bit registers that are used for many different functions, suchas clock, alarm, watchdog, timer, timestamp etc. (see Section8.1).The PCF2127A has an output reset pin: the output reset is activated on Power-On Reset(POR), and whenever the oscillator is stopped (see Section8.8).The PCF2127A features 512 bytes of general purpose static RAM, which is batterybacked and can be used independently of the RTC functionality (see Section8.5).The PCF2127A has a backup battery input pin and backup battery switch-over circuitwhich monitors the main power supply and automatically switches to the backup batterywhen a power failure condition is detected (see Section8.6.1). Accurate timekeeping ismaintained even when the main power supply is interrupted.A battery low detection circuit monitors the status of the battery (see Section8.6.3). Whenthe battery voltage goes below a certain threshold value, a flag is set to indicate that thebattery must be replaced. This can be used to ensure the integrity of the data duringperiods of battery backup. A power failure detection circuit monitors the voltage of thepower fail input pin PFI. When the voltage on the power fail input pin PFI goes below aninternal reference (1.25V), the power fail output pin PFO is activated (see Section8.6.4).8.1Register overviewThe PCF2127A contains 30 8-bit registers (see Table4) with an auto-incrementingaddress register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1Bh. After register 1Bh the auto-incrementing will wrap around to address 00h. The registers 1Ch and 1Dh must be addressed directly (see Figure3).•The first three registers (memory address 00h, 01h, and 02h) are used as control registers (see Section8.2).•The memory addresses 03h through to 09h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months withfewer than 31days, including corrections for leap years. The clock can operate in12-hour mode with an AM/PM indication or in 24-hour mode (see Section8.9).•Addresses 0Ah through 0Eh define the alarm function. It can be selected that an interrupt is generated when an alarm event occurs (see Section8.10).•The register 0Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4minutes (default)down to every 30seconds (see Table9). CLKOUT frequencies of 32.768kHz(default) down to 1Hz for use as a system clock, a microcontroller clock etc. can bechosen (see Table10).•Address registers 10h and 11h are used for the watchdog and countdown timer functions. The timer has four selectable source clocks allowing for timer periods fromless than 1ms to greater than 4hours (see Table36). Either the watchdog timer orthe countdown timer can be enabled (see Section8.11). For the watchdog timer it ispossible to select whether an interrupt or a pulse on the reset pin will be generatedwhen the watchdog times out. For the countdown timer it is only possible that aninterrupt will be generated at the end of the countdown.•Address registers 12h to 18h are used for the timestamp function. When the trigger-event happens the actual time is saved in the timestamp registers (seeSection8.12).•Address register 19h is used for the correction of the crystal aging effect (see Section8.4.1).•Address registers 1Ah and 1Bh define the RAM address. Address register 1Ch(RAM_wrt_cmd) is the RAM write command; address register 1Dh (RAM_rd_cmd) isthe RAM read command. Data is transferred to or from the RAM via the serialinterface (see Section8.5).•The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded inBinary Coded Decimal (BCD) format to simplify application use. Other registers areeither bit-wise or standard binary.When one of the RTC registers is written or read, the content of all counters is temporarilyfrozen. This prevents a faulty writing or reading of the clock and calendar during a carrycondition (see Section8.9.8).Table 4.Register overviewBit positions labeled as- are not implemented and will return a 0 when read. Bit T must always be written with logic0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets.Address Register name Bit Reset value76543210Control registers00h Control_1EXT_TEST T STOP TSF1POR_OVRD12_24MI SI0000000001h Control_2MSF WDTF TSF2AF CDTF TSIE AIE CDTIE00000000 02h Control_3PWRMNG[2:0]BTSE BF BLF BIE BLIE00000000 Time and date registers03h Seconds OSF SECONDS (0 to 59)1XXX XXXX 04h Minutes-MINUTES (0 to 59)-XXX XXXX 05h Hours--AMPM HOURS (1 to 12) in 12h mode--XX XXXXHOURS (0 to 23) in 24h mode--XX XXXX 06h Days--DAYS (1 to 31)--XX XXXX 07h Weekdays-----WEEKDAYS (0 to 6)-----XXX 08h Months---MONTHS (1 to 12)---X XXXX 09h Years YEARS (0 to 99)XXXX XXXX Alarm registers0Ah Second_alarm AE_S SECOND_ALARM (0 to 59)1XXX XXXX 0Bh Minute_alarm AE_M MINUTE_ALARM (0 to 59)1XXX XXXX 0Ch Hour_alarm AE_H-AMPM HOUR_ALARM (1 to 12) in 12h mode1-XX XXXX-HOUR_ALARM (0 to 23) in 24h mode1-XX XXXX 0Dh Day_alarm AE_D-DAY_ALARM (1 to 31)1-XX XXXX 0Eh Weekday_alarm AE_W----WEEKDAY_ALARM (0 to 6)1----XXX CLKOUT control register0Fh CLKOUT_ctl TCR[1:0]---COF[2:0]00---000 Watchdog registers10h Watchdg_tim_ctl WD_CD[1:0]TI_TP---TF[1:0]000---11 11h Watchdg_tim_val WATCHDG_TIM_VAL[7:0]XXXX XXXX Timestamp registers12h Timestp_ctl TSM TSOFF-1_O_16_TIMESTP[4:0]00-X XXXX 13h Sec_timestp-SECOND_TIMESTP (0 to 59)-XXX XXXXTable 4.Register overview …continuedBit positions labeled as- are not implemented and will return a 0 when read. Bit T must always be written with logic0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets.Address Register name Bit Reset value7654321014h Min_timestp-MINUTE_TIMESTP (0 to 59)-XXX XXXX 15h Hour_timestp--AMPM HOUR_TIMESTP (1 to 12) in 12h mode--XX XXXXHOUR_TIMESTP (0 to 23) in 24h mode--XX XXXX 16h Day_timestp--DAY_TIMESTP (1 to 31)--XX XXXX 17h Mon_timestp---MONTH_TIMESTP(1to12)---X XXXX 18h Year_timestp YEAR_TIMESTP (0 to 99)XXXX XXXX Aging offset register19h Aging_offset----AO[3:0]----1000 RAM registers1Ah RAM_addr_MSB-------RA8-------0 1Bh RAM_addr_LSB RA[7:0]00000000 1Ch RAM_wrt_cmd X X X X X X X X XXXX XXXX 1Dh RAM_rd_cmd X X X X X X X X XXXX XXXX8.2Control registersPCF2127A has 30 8-bit registers. The first 3 registers with the addresses 00h, 01h, and 02h are used as control registers.8.2.1Register Control_1[1]Default value.[2]When writing to the register this bit has always to be set logic 0.Table 5.Control_1 - control and status register 1 (address 00h) bit descriptionBit Symbol Value Description Reference 7EXT_TEST 0[1]normal modeSection 8.141external clock test mode6T 0[2]unused-5STOP0[1]RTC source clock runs Section 8.151RTC clock is stopped;RTC divider chain flip-flops are asynchronously set logic 0;CLKOUT at 32.768kHz, 16.384kHz, or 8.192kHz is still available4TSF10[1]no timestamp interrupt generated Section 8.12.11flag set when TS input is driven to an intermediate level between power supply and ground;flag must be cleared to clear interrupt3POR_OVRD 0[1]Power-On Reset Override (PORO) facility disabled;set logic 0 for normal operation Section 8.8.21PORO enabled212_240[1]24hour mode selected Table 22112hour mode selected 1 MI 0[1]minute interrupt disabled Section 8.131minute interrupt enabled 0SI0[1]second interrupt disabled 1second interrupt enabled8.2.2Register Control_2[1]Default value.Table 6.Control_2 - control and status register 2 (address 01h) bit descriptionBit Symbol Value DescriptionReference 7MSF0[1]no minute or second interrupt generated Section 8.131flag set when minute or second interrupt generated;flag must be cleared to clear interrupt6WDTF 0[1]no watchdog timer interrupt or reset generatedSection 8.13.41flag set when watchdog timer interrupt or reset generated;flag cannot be cleared by using the interface (read-only)5TSF20[1]no timestamp interrupt generated Section 8.12.11flag set when TS input is driven to ground;flag must be cleared to clear interrupt4AF 0[1]no alarm interrupt generated Section 8.10.61flag set when alarm triggered;flag must be cleared to clear interrupt3CDTF 0[1]no countdown timer interrupt generated Section 8.11.41flag set when countdown timer interrupt generated;flag must be cleared to clear interrupt2TSIE 0[1]no interrupt generated from timestamp flag Section 8.13.61interrupt generated when timestamp flag set 1AIE 0[1]no interrupt generated from the alarm flag Section 8.13.51interrupt generated when alarm flag setCDTIE0[1]no interrupt generated from countdown timer flagSection 8.13.21interrupt generated when countdown timer flag set分销商库存信息: NXPPCF2127AT/1,518。

合集下载

EML17T2R;中文规格书,Datasheet资料

EML17T2R;中文规格书,Datasheet资料

Transistors1/3General purpose transistor (isolated transistor and diode)EML17DTA144E and a RB520G-30 are housed independently in a EMT package.z ApplicationsDC / DC converter Motor driverz Features1) Tr : Degital Transistor Di : Low V F 2) Small packagez StructureSilicon epitaxial planar degital transistor Schottky barrier diodez External dimensions (Unit : mm)z Equivalent circuitz Packaging specificationsType EML17EMT5L17T2R 8000Package Marking CodeBasic ordering unit (pieces)Transistors 2/3z Absolute maximum ratings (T a=25°C) Tr2Parameter Symbol V CC V IN I O I C(MAX)TjLimits −50−40 to +10−30−100150Unit V V mA °CSupply voltage Input voltage Output current Junction temperaturePd 120mW Power dissipationDi1, Tr2Parameter SymbolPd Tstg Limits150−55 to +125Unit mW ∗∗ Each terminal mounted on a recommended land.°CPower dissipationRange of storage temperaturez Electrical characteristics (T a=25°C) Di1ParameterSymbol Min.Typ.Max.Unit Conditions−0.45V F −V I F =10mA V R =10VForward voltage I R−−0.5µAReverse current∗ Please pay attention to static electricity when handling.Tr2ParameterSymbol Min.Typ.Max.Unit ConditionsV CE = −10V, I E =5mA, f =100MHz∗∗ Transition frequency of the deviceResistance ratio R 2/R 10.81 1.2−−V I(off)−−−0.5I C = −5V, I O = −100µA Input voltage V I(on)−3.0−−V V O = −0.3V, I O = −2mA V O(on)−−0.1−0.3V I O /I I = −10mA/ −0.5mA Output voltage I I −−−0.18mA V I = −5VInput current I O(off)−−−0.5µA V CC = −50V, V I =0V Output current G 168−−−V O = −5V, I O = −5mADC current gain R 132.94761.1k Ω−Input resistance f T −250−MHz Transition frequencyTransistors 3/3z Electrical characteristic curves Di1R E V E R S E C U R R E N T : I R (n A )REVERSE VOLTAGE : V R (V)Fig.2 Reverse characteristicsF O R W A R D C U R R E N T : I F (m A )FORWARD VOLTAGE : V F (mV)Fig.1 Forward characteristics101525520110100REVERSE VOLTAGE : V R (V)C A P A C I T A N C E B E T W E E N T E R M I N A L S : C T (p F )Fig. 3 Capacitance between terminals characteristics30Tr2I N P U T V O L T A G E : V I (o n ) (V )OUTPUT CURRENT : I O (A)−−−−−−−−−−−Fig.4 Input voltage vs. output current (ON characteristics)−−1−−−−200−500−100−20−50−10−2−5INPUT VOLTAGE : V I(off) (V)O U T P U T C U R R E N T : I o (A )Fig.5 Output current vs. Input voltage (OFF characteristics)−D C C U R R E N T G A I N : G IOUTPUT CURRENT : I O (A)Fig.6 DC current gain vs. output current−−−−−−−−−−−OUTPUT CURRENT : I O (A)O U T P U T V O L T A G E : V O (o n ) (V )Fig.7 Output voltage vs. output currentAppendixAbout Export Control Order in JapanProducts described herein are the objects of controlled goods in Annex 1 (Item 16) of Export T rade ControlOrder in Japan.In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.Appendix1-Rev1.1分销商库存信息: ROHMEML17T2R。

pcf2129数据手册

pcf2129数据手册


Fig 2. Table 3. Symbol SCL
Pin configuration SO20
Pin description PCF2129 Pin 1 Description combined serial clock input for both I2C-bus and SPI-bus; may float when CE inactive serial data input for SPI-bus; may float when CE inactive serial data output for SPI-bus, push-pull combined serial data input/output for the I2C interface and chip enable input (active LOW) for the SPI-bus interface selector input Symbol VDD Pin 20 Description positive supply voltage
FT A R D
FT A R D
NXP Semiconductors
PCF2129
A R D D FT A R FT FT A R D R D FT A A R D A R D
FT A R D
FT A R D
FT A R D
Integrated RTC/TCXO/Crystal
R D
D FT A R
IFS
5
n.c.
16
• •
TS CLKOUT VSS n.c. n.c. 6 7 8 9 10
connect to ground to select the SPI-bus connect to BBS (pin 18) to select the I2C interface n.c. n.c. n.c. n.c. n.c. 15 14 13 12 11
IRS2127PbF中文资料

IRS2127PbF中文资料

Features•Floating channel designed for bootstrap operationFully operational to +600 V Tolerant to negative transient voltage dV/dt immune •Application-specific gate drive range:Motor Drive: 12 V to 20 V (IRS2127/IRS2128)Automotive: 9 V to 20 V (IRS21271/IRS21281)•Undervoltage lockout•3.3 V, 5 V, and 15 V input logic compatible • lead indicates shutdown has occured•Output in phase with input (IRS2127/IRS21271)•Output out of phase with input (IRS2128/IRS21281)CURRENT SENSING SINGLE CHANNEL DRIVERV OFFSET 600 V max. I O +/-200 mA / 420 mA V OUT 12 V - 20V 9 V - 20 V (IRS2127/IR2128) (IRS21271/IR21281) V CSth 250 mV or 1.8 V ton/off (typ.)150 ns & 150 nsTypical Connection 1Packages8-Lead PDIP 8-Lead SOICIRS212(7, 71, 8, 81)(S)PbFData Sheet No. PD 60299DescriptionThe IRS2127/IRS2128/IRS21271/IRS21281 arehigh voltage, high speed power MOSFET and IGBT drivers. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construc-tion. The logic input is compatible with standard CMOS or LSTTL outputs, down to 3.3 V. The protec-tion circuity detects over-current in the driven power transistor and terminates the gate drive voltage. Anopen drain FAULT signal is provided to indicate that an over-current shutdown has occurred. The outputProduct Summarydriver features a high pulse current buffer stage designed for minimum cross-conduction. The floating chan-nel can be used to drive an N-channel power MOSFET or IGBT in the high-side or low-side configuration which operates up to 600 V.• RoHS compliantIRS212(7, 71, 8, 81)(S)PbF 2Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured Note 1: L ogic operational for V S of -5 V to +600 V. L ogic state held for V S of -5 V to -V BS . (Please refer to the Design Tip DT97-3 for more details).Recommended Operating ConditionsThe input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at 15 V differential. 3IRS212(7, 71, 8, 81)(S)PbFDynamic Electrical CharacteristicsV BIAS (V CC , V BS ) = 15 V, C L = 1000 pF and T A = 25 °C unless otherwise specified. The dynamic electrical characteristics are measured using the test circuit shown in Fig. 3.Static Electrical CharacteristicsV BIAS (V CC , V BS ) = 15 V and T A = 25 °C unless otherwise specified. The V IN , V TH, and I IN parameters are referenced toIRS212(7, 71, 8, 81)(S)PbF 4Functional Block Diagram IRS2127/IRS21271Functional Block Diagram IRS2128/IRS21281IRS212(7, 71, 8, 81)(S)PbF5IRS212(7, 71, 8, 81)(S)PbF 6Figure 4. CS Shutdown Waveform DefinitionsFigure 5. CS to FAULT Waveform DefinitionsFigure 2. Switching Time Waveform DefinitionFigure 1. Input/Output Timing DiagramHOCSFAULTIRS21271)Figure 3. Start-U p Blanking Time WaveformDefinitionsFAULTIRS212(7, 71, 8, 81)(S)PbF7IRS212(7, 71, 8, 81)(S)PbF 80102030405060708090-50-25255075100Temperature (°C)Figure 9A. Turn-Off Fall Time vs.T u r n -O f f F a l l T i m e (n s )TemperatureIRS212(7, 71, 8, 81)(S)PbF9IRS212(7, 71, 8, 81)(S)PbF 10IRS212(7, 71, 8, 81)(S)PbF11IRS212(7, 71, 8, 81)(S)PbF 12IRS212(7, 71, 8, 81)(S)PbF13IRS212(7, 71, 8, 81)(S)PbF 14IRS212(7, 71, 8, 81)(S)PbF15IRS212(7, 71, 8, 81)(S)PbF 16IRS212(7, 71, 8, 81)(S)PbF 17IRS212(7, 71, 8, 81)(S)PbF18Case outlinesIRS212(7, 71, 8, 81)(S)PbF20CTape & Reel 8-lead SOIC 21IRS212(7, 71, 8, 81)(S)PbFORDER INFORMATION8-Lead PDIP IRS2127PbF 8-Lead PDIP IRS21271PbF 8-Lead SOIC IRS2127SPbF 8-Lead SOIC IRS21271SPbF8-Lead SOIC Tape & Reel IRS2127STRPbF 8-Lead SOIC Tape & Reel IRS21271STRPbFLEADFREE PART MARKING INFORMATIONPer SCOP 200-002The SOIC-8 is MSL2 qualified.This product has been designed and qualified for the industrial level.Qualification standards can be found at IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105Data and specifications subject to change without notice. 6/27/20078-Lead PDIP IRS2128PbF 8-Lead PDIP IRS21281PbF 8-Lead SOIC IRS2128SPbF 8-Lead SOIC IRS21281SPbF8-Lead SOIC Tape & Reel IRS2128STRPbF 8-Lead SOIC Tape & Reel IRS21281STRPbF元器件交易网。

R5F21274KXXXFP资料

R5F21274KXXXFP资料

R8C/26 Group, R8C/27 GroupSINGLE-CHIP 16-BIT CMOS MCU1.OverviewThese MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.Furthermore, the R8C/27 Group has on-chip data flash (1 KB × 2 blocks).The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash.Their peripheral functions are the same.1.1ApplicationsElectronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.REJ03B0168-0130Rev.1.30May 25, 2007J and K versions are under development. Specifications may be changed without prior notice.1.2Performance OverviewTable 1.1 outlines the Functions and Specifications for R8C/26Group and Table 1.2 outlines the Functions and Specifications for R8C/27 Group.NOTES:1.I 2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D, K version if D, K version functions are to be used.Table 1.1Functions and Specifications for R8C/26GroupItemSpecificationCPUNumber of fundamental instructions89 instructionsMinimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)Operating mode Single-chip Address space 1 MbyteMemory capacity Refer to Table 1.3 Product Information for R8C/26 Group Peripheral FunctionsPortsI/O ports: 25 pins, Input port: 3 pins LED drive ports I/O ports: 8 pins (N, D version)TimersTimer RA: 8 bits × 1 channel Timer RB: 8 bits × 1 channel(Each timer equipped with 8-bit prescaler)Timer RC: 16 bits × 1 channel(Input capture and output compare circuits)Timer RE: With real-time clock and compare match function(For J, K version, compare match function only.)Serial interfaces 2 channels (UART0, UART1)Clock synchronous serial I/O, UART Clock synchronous serial interface 1 channelI 2C bus Interface (1)Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0)A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits × 1 channel (with prescaler)Start-on-reset selectableInterrupts Internal: 15 sources, External: 4 sources, Software: 4 sources, Priority levels: 7 levels Clock generation circuits3 circuits•XIN clock generation circuit (with on-chip feedback resistor)•On-chip oscillator (high speed, low speed)High-speed on-chip oscillator has a frequency adjustment function •XCIN clock generation circuit (32 kHz) (N, D version)•Real-time clock (timer RE) (N, D version)Oscillation-stopped detectorXIN clock oscillation stop detection function Voltage detection circuitOn-chipPower-on reset circuit On-chipElectricalCharacteristicsSupply voltageVCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)Current consumption (N, D version)Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)Typ. 0.7 µA (VCC = 3.0 V, stop mode)Flash MemoryProgramming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure endurance100 timesOperating Ambient Temperature-20 to 85°C (N version)-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)Package 32-pin molded-plastic LQFPNOTES:1.I 2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D, K version if D, K version functions are to be used.Table 1.2Functions and Specifications for R8C/27 GroupItem SpecificationCPU Number of fundamental instructions89 instructionsMinimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information of R8C/27 GroupPeripheral Functions Ports I/O ports: 25 pins, Input port: 3 pins LED drive ports I/O ports: 8 pins (N, D version)Timers Timer RA: 8 bits × 1 channelTimer RB: 8 bits × 1 channel(Each timer equipped with 8-bit prescaler)Timer RC: 16 bits × 1 channel(Input capture and output compare circuits)Timer RE: With real-time clock and compare match function(For J, K version, compare match function only.)Serial interfaces 2 channels (UART0, UART1)Clock synchronous serial I/O, UARTClock synchronous serial interface 1 channel I 2C bus Interface (1)Clock synchronous serial I/O with chip selectLIN module Hardware LIN: 1 channel (timer RA, UART0)A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits × 1 channel (with prescaler)Start-on-reset selectableInterrupts Internal: 15 sources, External: 4 sources,Software: 4 sources, Priority levels: 7 levelsClock generation circuits 3 circuits •XIN clock generation circuit (with on-chip feedback resistor)•On-chip oscillator (high speed, low speed)High-speed on-chip oscillator has a frequency adjustment function •XCIN clock generation circuit (32 kHz) (N, D version)•Real-time clock (timer RE) (N, D version)Oscillation-stopped detectorXIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chipElectrical Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)Current consumption (N, D version)Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)Typ. 0.7 µA (VCC = 3.0 V, stop mode)Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 VProgramming and erasure endurance 10,000 times (data flash)1,000 times (program ROM)Operating Ambient Temperature -20 to 85°C (N version)-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)Package 32-pin molded-plastic LQFP1.3 Block DiagramFigure 1.1 shows a Block Diagram.1.4Product InformationTable 1.3 lists Product Information for R8C/26 Group and Table 1.4 lists Product Information for R8C/27 Group.(D): Under development NOTES:1.These versions are under development. Specifications may be changed without prior notice.2.The user ROM is programmed before shipment.Table 1.3Product Information for R8C/26 Group Current of May. 2007 Part No.ROM Capacity RAM Capacity Package Type RemarksR5F21262SNFP 8 Kbytes 512 bytes PLQP0032GB-A N versionR5F21264SNFP 16 Kbytes 1 Kbyte PLQP0032GB-A R5F21265SNFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21266SNFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21262SDFP 8 Kbytes 512 bytes PLQP0032GB-A D versionR5F21264SDFP 16 Kbytes 1 Kbyte PLQP0032GB-A R5F21265SDFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21266SDFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21264JFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A J version (1)R5F21266JFP (D)32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21264KFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A K version (1)R5F21266KFP (D)32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21262SNXXXFP (D) 8 Kbytes 512 bytes PLQP0032GB-A N version (1)Factoryprogramming product (2)R5F21264SNXXXFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A R5F21265SNXXXFP (D)24 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21266SNXXXFP (D)32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21262SDXXXFP (D) 8 Kbytes 512 bytes PLQP0032GB-A D version (1)R5F21264SDXXXFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A R5F21265SDXXXFP (D)24 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21266SDXXXFP (D)32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21264JXXXFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A J version (1)R5F21266JXXXFP (D)32 Kbytes 1.5 Kbytes PLQP0032GB-A R5F21264KXXXFP (D)16 Kbytes 1 Kbyte PLQP0032GB-A K version (1)R5F21266KXXXFP (D)32 Kbytes1.5 KbytesPLQP0032GB-A(D): Under development NOTES:1.These versions are under development. Specifications may be changed without prior notice.2.The user ROM is programmed before shipment.Table 1.4Product Information for R8C/27 GroupCurrent of May. 2007Part No.ROM Capacity RAM Capacity Package Type RemarksProgramROMData flashR5F21272SNFP 8 Kbytes 1 Kbyte × 2512 bytes PLQP0032GB-A N versionR5F21274SNFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A R5F21275SNFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21276SNFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21272SDFP 8 Kbytes 1 Kbyte × 2512 bytes PLQP0032GB-A D versionR5F21274SDFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A R5F21275SDFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21276SDFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21274JFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version (1)R5F21276JFP (D)32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21274KFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version (1)R5F21276KFP (D)32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21272SNXXXFP (D) 8 Kbytes 1 Kbyte × 2512 bytes PLQP0032GB-A N version (1)Factoryprogramming product (2)R5F21274SNXXXFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A R5F21275SNXXXFP (D)24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21276SNXXXFP (D)32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21272SDXXXFP (D) 8 Kbytes 1 Kbyte × 2512 bytes PLQP0032GB-A D version (1)R5F21274SDXXXFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A R5F21275SDXXXFP (D)24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21276SDXXXFP (D)32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21274JXXXFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version (1)R5F21276JXXXFP (D)32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A R5F21274KXXXFP (D)16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version (1)R5F21276KXXXFP (D)32 Kbytes 1 Kbyte × 21.5 KbytesPLQP0032GB-A1.5Pin AssignmentsFigure 1.4 shows Pin Assignments (Top View).1.6Pin FunctionsTable 1.5 lists Pin Functions.I: InputO: OutputI/O: Input and outputTable 1.5Pin FunctionsTypeSymbolI/O TypeDescriptionPower supply input VCC, VSS I Apply 2.2 V to 5.5 V (J, K version are 2.7 V to 5.5 V) to the VCC pin. Apply 0 V to the VSS pin.Analog power supply input AVCC, AVSS I Power supply for the A/D converter.Connect a capacitor between AVCC and AVSS.Reset input RESET I Input “L” on this pin resets the MCU.MODE MODE I Connect this pin to VCC via a resistor.XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open.XIN clock output XOUT O XCIN clock input (N, D version)XCIN I These pins are provided for XCIN clock generation circuit I/O.Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open.XCIN clock output (N, D version)XCOUTO INT interrupt input INT0, INT1, INT3I INT interrupt input pins Key input interrupt KI0 to KI3I Key input interrupt input pins Timer RA TRAO O Timer RA output pin TRAIO I/O Timer RA I/O pin Timer RB TRBO O Timer RB output pin Timer RCTRCCLK I External clock input pin TRCTRGI External trigger input pinTRCIOA, TRCIOB, TRCIOC, TRCIODI/O Sharing output-compare output / input-capture input / PWM / PWM2 output pins Timer RE TREO O Timer RE output pin Serial interfaceCLK0, CLK1I/O Clock I/O pinRXD0, RXD1I Receive data input pin TXD0, TXD1O Transmit data output pin I 2C bus interfaceSCL I/O Clock I/O pin SDAI/O Data I/O pin Clock synchronous serial I/O with chip selectSSI I/O Data I/O pinSCS I/O Chip-select signal I/O pin SSCKI/O Clock I/O pin SSOI/O Data I/O pinReference voltage input VREF I Reference voltage input pin to A/D converter A/D converter AN0 to AN11I Analog input pins to A/D converterI/O portP0_0 to P0_7, P1_0 to P1_7, P3_1, P3_3 to P3_7,P4_5,P5_3, P5_4I/OCMOS I/O ports. Each port has an I/O select direction register,allowing each pin in the port to be directed for input or output individually.Any port set to input can be set to use a pull-up resistor or not by a program.P1_0 to P1_7 also function as LED drive ports. (N, D version)Input port P4_2, P4_6, P4_7IInput-only portsR8C/26 Group, R8C/27 Group1. OverviewNOTES:1.This can be assigned to the pin in parentheses by a program.2.XCIN, XCOUT can be used only for N or D version.Table 1.6Pin Name Information by Pin NumberPin Number Control Pin PortI/O Pin Functions for of Peripheral ModulesInterruptTimerSerial Interface ClockSynchronous Serial I/O with Chip Select I 2C busInterface A/D Converter1P3_5(TRCIOD)(1)SSCK SCL 2P3_7TRAO RXD1/(TXD1)(1)SSO3RESET 4XOUT/XCOUT (2)P4_75VSS/AVSS 6XIN/XCIN (2)P4_67VCC/AVCC 8MODE9P4_5INT0(RXD1)(1)10P1_7INT1TRAIO11P3_6(INT1)(1)(TXD1)/(RXD1)(1)12P3_1TRBO 13P5_4TRCIOD 14P5_3TRCIOC 15P1_6CLK0(SSI)(1)16P1_5(INT1)(1)(TRAIO)(1)RXD017P1_4TXD018P1_3KI3(TRBO)AN1119P1_2KI2TRCIOB AN1020VRFFP4_221P1_1KI1TRCIOA/TRCTRGAN922P1_0KI0AN823P3_3INT3TRCCLK SSI 24P3_4(TRCIOC)(1)SCSSDA25P0_7AN026P0_6AN127P0_5CLK1AN228P0_4TREOAN329P0_3AN430P0_2AN531P0_1AN632P0_0(TXD1)(1)AN72.Central Processing Unit (CPU)Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.2.1Data Registers (R0, R1, R2, and R3)R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.2.2Address Registers (A0 and A1)A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used as a 32-bit address register (A1A0).2.3Frame Base Register (FB)FB is a 16-bit register for FB relative addressing.2.4Interrupt Table Register (INTB)INTB is a 20-bit register that indicates the start address of an interrupt vector table.2.5Program Counter (PC)PC is 20 bits wide and indicates the address of the next instruction to be executed.2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch betweenUSP and ISP.2.7Static Base Register (SB)SB is a 16-bit register for SB relative addressing.2.8Flag Register (FLG)FLG is an 11-bit register indicating the CPU state.2.8.1Carry Flag (C)The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.2.8.2Debug Flag (D)The D flag is for debugging only. Set it to 0.2.8.3Zero Flag (Z)The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.2.8.4Sign Flag (S)The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.2.8.5Register Bank Select Flag (B)Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.2.8.6Overflow Flag (O)The O flag is set to 1 when an operation results in an overflow; otherwise to 0.2.8.7Interrupt Enable Flag (I)The I flag enables maskable interrupts.Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.2.8.8Stack Pointer Select Flag (U)ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.2.8.9Processor Interrupt Priority Level (IPL)IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has higher priority than IPL, the interrupt is enabled.2.8.10Reserved BitIf necessary, set to 0. When read, the content is undefined.3.Memory3.1R8C/26 GroupFigure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses 00000h to FFFFFh.The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged.Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.3.2R8C/27 GroupFigure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses 00000h to FFFFFh.The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged.Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.4.Special Function Registers (SFRs)An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers.Table 4.1SFR Information (1)(1)X: Undefined NOTES:1.The blank regions are reserved. Do not access locations in these regions.2.The CSPROINI bit in the OFS register is set to 0.3.In J, K version these regions are reserved. Do not access locations in these regions.Address RegisterSymbolAfter reset0000h 0001h 0002h 0003h 0004h Processor Mode Register 0PM000h 0005h Processor Mode Register 1PM100h0006h System Clock Control Register 0CM001101000b 0007h System Clock Control Register 1CM100100000b0008h 0009h 000Ah Protect RegisterPRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh000Fh Watchdog Timer Control Register WDC 00X11111b 0010h Address Match Interrupt Register 0RMAD000h 0011h 00h 0012h 00h 0013h Address Match Interrupt Enable Register AIER 00h 0014h Address Match Interrupt Register 1RMAD100h 0015h 00h 0016h 00h0017h 0018h 0019h 001Ah 001Bh 001ChCount Source Protection Mode Register CSPR00h10000000b (2)001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0FRA000h0024h High-Speed On-Chip Oscillator Control Register 1FRA1When shipping 0025h High-Speed On-Chip Oscillator Control Register 2FRA200h0026h 0027h 0028h Clock Prescaler Reset Flag CPSRF 00h0029h High-Speed On-Chip Oscillator Control Register 4(3)FRA4When shipping 002Ah 002Bh High-Speed On-Chip Oscillator Control Register 6(3)FRA6When shipping002Ch 002Dh 002Eh 002FhTable 4.2SFR Information (2)(1)X: Undefined NOTES:1.The blank regions are reserved. Do not access locations in these regions.2.(N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register.3.The LVD0ON bit in the OFS register is set to 1 and hardware reset.4.Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.5.(N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.6.(N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.(J, K version) These regions are reserved. Do not access locations in these regions.7.The LVD1ON bit in the OFS register is set to 1 and hardware reset.8.Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.9.Selected by the IICSEL bit in the PMR register.Address RegisterSymbolAfter reset0030h 0031h Voltage Detection Register 1 (2)VCA100001000b0032hVoltage Detection Register 2 (2)VCA2•N, Dversion 00h (3)00100000b (4)•J, K version 00h (7)01000000b (8)0033h 0034h 0035h 0036hVoltage Monitor 1 Circuit Control Register (5)VW1C•N, D version 00001000b •J, K version 0000X000b (7)0100X000b (8)0037h Voltage Monitor 2 Circuit Control Register (5)VW2C 00h0038h Voltage Monitor 0 Circuit Control Register (6)VW0C0000X000b (3)0100X001b (4)0039h 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register TRCIC XXXXX000b0048h 0049h 004Ah Timer RE Interrupt Control Register TREIC XXXXX000b004Bh 004Ch 004Dh Key Input Interrupt Control RegisterKUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADICXXXXX000b 004Fh SSU / IIC Interrupt Control Register (9)SSUIC / IICIC XXXXX000b 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h 0056h Timer RA Interrupt Control Register TRAIC XXXXX000b 0057h 0058h Timer RB Interrupt Control Register TRBIC XXXXX000b 0059h INT1 Interrupt Control Register INT1IC XX00X000b 005Ah INT3 Interrupt Control RegisterINT3ICXX00X000b005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC XX00X000b005Eh 005Fh 0060h 006Fh 0070h 007FhTable 4.3SFR Information (3)(1)Address Register Symbol After reset 0080h0081h0082h0083h0084h0085h0086h0087h0088h0089h008Ah008Bh008Ch008Dh008Eh008Fh0090h0091h0092h0093h0094h0095h0096h0097h0098h0099h009Ah009Bh009Ch009Dh009Eh009Fh00A0h UART0 Transmit/Receive Mode Register U0MR00h00A1h UART0 Bit Rate Register U0BRG XXh00A2h UART0 Transmit Buffer Register U0TB XXh00A3h XXh00A4h UART0 Transmit/Receive Control Register 0U0C000001000b 00A5h UART0 Transmit/Receive Control Register 1U0C100000010b 00A6h UART0 Receive Buffer Register U0RB XXh00A7h XXh00A8h UART1 Transmit/Receive Mode Register U1MR00h00A9h UART1 Bit Rate Register U1BRG XXh00AAh UART1 Transmit Buffer Register U1TB XXh00ABh XXh00ACh UART1 Transmit/Receive Control Register 0U1C000001000b 00ADh UART1 Transmit/Receive Control Register 1U1C100000010b 00AEh UART1 Receive Buffer Register U1RB XXh00AFh XXh00B0h00B1h00B2h00B3h00B4h00B5h00B6h00B7h00B8h SS Control Register H / IIC bus Control Register 1(2)SSCRH / ICCR100h00B9h SS Control Register L / IIC bus Control Register 2(2)SSCRL / ICCR201111101b 00BAh SS Mode Register / IIC bus Mode Register(2)SSMR / ICMR00011000b 00BBh SS Enable Register / IIC bus Interrupt Enable Register(2)SSER / ICIER00h00BCh SS Status Register / IIC bus Status Register(2)SSSR / ICSR00h / 0000X000b 00BDh SS Mode Register 2 / Slave Address Register(2)SSMR2 / SAR00h00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2)SSTDR / ICDRT FFh00BFh SS Receive Data Register / IIC bus Receive Data Register(2)SSRDR / ICDRR FFhX: UndefinedNOTES:1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.Table 4.4SFR Information (4)(1)Address Register Symbol After reset 00C0h A/D Register AD XXh00C1h XXh00C2h00C3h00C4h00C5h00C6h00C7h00C8h00C9h00CAh00CBh00CCh00CDh00CEh00CFh00D0h00D1h00D2h00D3h00D4h A/D Control Register 2ADCON200h00D5h00D6h A/D Control Register 0ADCON000h00D7h A/D Control Register 1ADCON100h00D8h00D9h00DAh00DBh00DCh00DDh00DEh00DFh00E0h Port P0 Register P000h00E1h Port P1 Register P100h00E2h Port P0 Direction Register PD000h00E3h Port P1 Direction Register PD100h00E4h00E5h Port P3 Register P300h00E6h00E7h Port P3 Direction Register PD300h00E8h Port P4 Register P400h00E9h Port P5 Register P500h00EAh Port P4 Direction Register PD400h00EBh Port P5 Direction Register PD500h00ECh00EDh00EEh00EFh00F0h00F1h00F2h00F3h00F4h00F5h Pin Select Register 1PINSR100h00F6h Pin Select Register 2PINSR200h00F7h Pin Select Register 3PINSR300h00F8h Port Mode Register PMR00h00F9h External Input Enable Register INTEN00h00FAh INT Input Filter Select Register INTF00h00FBh Key Input Enable Register KIEN00h00FCh Pull-Up Control Register 0PUR000h00FDh Pull-Up Control Register 1PUR100h00FEh Port P1 Drive Capacity Control Register(2)P1DRR00h00FFhX: UndefinedNOTES:1.The blank regions are reserved. Do not access locations in these regions.2.In J, K version these regions are reserved. Do not access locations in these regions.Table 4.5SFR Information (5)(1)Address Register Symbol After reset 0100h Timer RA Control Register TRACR00h0101h Timer RA I/O Control Register TRAIOC00h0102h Timer RA Mode Register TRAMR00h0103h Timer RA Prescaler Register TRAPRE FFh0104h Timer RA Register TRA FFh0105h0106h LIN Control Register LINCR00h0107h LIN Status Register LINST00h0108h Timer RB Control Register TRBCR00h0109h Timer RB One-Shot Control Register TRBOCR00h010Ah Timer RB I/O Control Register TRBIOC00h010Bh Timer RB Mode Register TRBMR00h010Ch Timer RB Prescaler Register TRBPRE FFh010Dh Timer RB Secondary Register TRBSC FFh010Eh Timer RB Primary Register TRBPR FFh010Fh0110h0111h0112h0113h0114h0115h0116h0117h0118h Timer RE Second Data Register / Counter Data Register TRESEC00h0119h Timer RE Minute Data Register / Compare Data Register TREMIN00h011Ah Timer RE Hour Data Register(2)TREHR00h011Bh Timer RE Day of Week Data Register(2)TREWK00h011Ch Timer RE Control Register 1TRECR100h011Dh Timer RE Control Register 2TRECR200h011Eh Timer RE Clock Source Select Register TRECSR00001000b 011Fh0120h Timer RC Mode Register TRCMR01001000b 0121h Timer RC Control Register 1TRCCR100h0122h Timer RC Interrupt Enable Register TRCIER01110000b 0123h Timer RC Status Register TRCSR01110000b 0124h Timer RC I/O Control Register 0TRCIOR010001000b 0125h Timer RC I/O Control Register 1TRCIOR110001000b 0126h Timer RC Counter TRC00h0127h00h0128h Timer RC General Register A TRCGRA FFh0129h FFh012Ah Timer RC General Register B TRCGRB FFh012Bh FFh012Ch Timer RC General Register C TRCGRC FFh012Dh FFh012Eh Timer RC General Register D TRCGRD FFh012Fh FFh0130h Timer RC Control Register 2TRCCR200011111b 0131h Timer RC Digital Filter Function Select Register TRCDF00h0132h Timer RC Output Master Enable Register TRCOER01111111b 0133h0134h0135h0136h0137h0138h0139h013Ah013Bh013Ch013Dh013Eh013FhX: UndefinedNOTES:1.The blank regions are reserved. Do not access locations in these regions.2.In J, K version these regions are reserved. Do not access locations in these regions.。