时序电路VHDL程序
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4位二进制减计数器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GKY07P9 IS
PORT(clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END GKY07P9;
ARCHITECTURE struc OF GKY07P9 IS
SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
IF reset='0'THEN
q_temp<="1111";
ELSIF q_temp<="0000" THEN
q_temp<="1111";
ELSE
q_temp<=q_temp-1;
END IF;
END IF;
END PROCESS;
q<=q_temp;
END struc;
从状态‘1111’到状态‘0000’，然后再跳回‘1111’。异步复位不需要跟随脉冲变化，要立即复位。
8421码十进制计数器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GKY07P10 IS
PORT(clk,reset:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END GKY07P10;
ARCHITECTURE struc OF GKY07P10 IS
SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')THEN
IF reset='1'THEN
q_temp<="0000";
ELSIF q_temp="1001"THEN
q_temp<="0000";
ELSE
q_temp<=q_temp+1;
END IF;
END IF;
END PROCESS;
q<=q_temp;
END struc;
从状态‘0000’到状态‘1001’，然后再跳回‘0000’，异步复位要立即复位。
4位环形计数器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GKY07P11 IS
PORT(clk,reset:IN STD_LOGIC;
countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END GKY07P11;
ARCHITECTURE behave OF GKY07P11 IS
SIGNAL nextcount: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk,reset)
BEGIN
IF RESET='1' THEN nextcount<="0001";
ELSIF(clk'EVENT AND clk='1')THEN
CASE nextcount IS
WHEN"0001"=> nextcount <="0010";
WHEN"0010"=> nextcount <="0100";
WHEN"0100"=> nextcount <="1000";
WHEN OTHERS=>nextcount<="0001";
END CASE;
END IF;
END PROCESS;
countout<=nextcount;
END behave;
计数状态在‘0001’，‘0010’，‘0100’，‘1000’四个之间转换，由于需要能够自启动，对别状态的处
理是全部引到那四个计数状态上。
8位二进制寄存器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GKY07P12 IS
PORT(d:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
oe,clk:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END GKY07P12;
ARCHITECTURE struc OF GKY07P12 IS
SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk,oe)
BEGIN
IF oe='1' THEN
IF clk'EVENT AND clk='1' THEN
temp<=d;
END IF;
ELSE
temp<="ZZZZZZZZ";
END IF;
q<=temp;
END PROCESS;
END struc;
和书上的例子基本一样，将低电平控制改成高电平控制即可。
分频器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GKY07P13 IS
PORT(clk,clear:IN STD_LOGIC;
clk_out:OUT STD_LOGIC);
END GKY07P13;
ARCHITECTURE struc OF GKY07P13 IS
SIGNAL temp:INTEGER RANGE 0 TO 11;
BEGIN
p1:PROCESS(clear,clk)
BEGIN
IF clear='0' THEN
temp<=0;
ELSIF clk'EVENT AND clk='1' THEN
IF temp=11 THEN
temp<=0;
ELSE
temp<=temp+1;
END IF;
END IF;
END PROCESS p1;
p2:PROCESS(temp)
BEGIN
IF temp<6 THEN
clk_out<='0';
ELSE
clk_out<='1';
END IF;
END PROCESS p2;
END struc;
很重要的一个器件，但是设计难度并不很高，首先是模为12的计数，然后是占空比50%。
