IDT54FCT162374ATPFB中文资料

4-Bit Binary CounterCY54/74FCT163TSCCS015 - May 1994 - Revised February 2000Data sheet acquired from Cypress Semiconductor Corporation.Data sheet modified to remove devices not offered.Features•Function, pinout, and drive compatible with FCT and F logic•FCT-C speed at 5.8 ns max. (Com’l),•Reduced V OH (typically = 3.3V) versions of equivalent FCT functions•Edge-rate control circuitry for significantly improved noise characteristics •Power-off disable feature •ESD > 2000V•Matched rise and fall times•Fully compatible with TTL input and output logic levels •Extended commercial range of −40˚C to +85˚C•Sink current 64 mA (Com’l),32 mA (Mil)Source current32 mA (Com’l),12 mA (Mil)Functional DescriptionThe FCT163T is a high-speed synchronous modulo-16binary counter.It is synchronously presettable for application in pro-grammable dividers and has two types of count enable inputs plus a terminal count output for versatility in forming synchro-nous multi-staged counters.The FCT163T has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.The outputs are designed with a power-off disable feature to allow for live insertion of boards.Logic Block DiagramPin ConfigurationsDetail AQ 1P 0Detail AQ 2Detail AQ 3DQCP D QQ 0P 1P 2P 3TCCEP CP Q 0Q 0Detail ACPPECETCPSR4891011127651516171832120131419P 3CETPE NC CP N C N C V CC TCCEP GND SR Top ViewP 0LCC NC P 2P 1Q 3Q 0Q 2Q 112345678CPP 0P 1P 3CEP V CC GNDTop ViewSOIC/QSOP 161514131211109SR Q3CET PETC Q 0Q 1Q 2P 2Maximum Ratings [2,3](Above which the useful life may be impaired.For user guide-lines, not tested.)Storage T emperature .....................................−65°C to +150°C Ambient T emperature withPower Applied ..................................................−65°C to +135°C Supply Voltage to Ground Potential ..................−0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V DC Output Voltage ..............................................−0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin)......120 mAPower Dissipation..........................................................0.5W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015)Function Table [1]InputsAction on the RisingClock Edge(s)SR PE CET CEP L H H H HX L H H HX X H L XX X H X LReset (Clear)Load (P n Q n )Count (Incremental)No Charge (Hold)No Charge (Hold)Pin DescriptionName DescriptionCEP Count Enable Parallel Input CET Count Enable T rickle InputCP Clock Pulse Input (Active Rising Edge)SR Synchronous Reset Input (Active LOW)P Parallel Data InputsPE Parallel Enable Input (Active LOW)Q Flip-Flop Outputs TCTerminal Count OutputOperating RangeRange Range Ambient Temperature V CC Commercial All −40°C to +85°C 5V ± 5%Military [4]All−55°C to +125°C5V ± 10%Electrical Characteristics Over the Operating RangeParameter DescriptionTest ConditionsMin.Typ.[5]Max.Unit V OHOutput HIGH VoltageV CC =Min., I OH =−32 mA Com’l 2.0V V CC =Min., I OH =−15 mA Com’l 2.4 3.3V V CC =Min., I OH =−12 mAMil 2.43.3V V OL Output LOW Voltage V CC =Min., I OL =64 mA Com’l 0.30.55V V CC =Min., I OL =32 mAMil0.30.55V V IH Input HIGH Voltage 2.0V V IL Input LOW Voltage 0.8V V H Hysteresis [6]All inputs0.2V V IK Input Clamp Diode Voltage V CC =Min., I IN =−18 mA −0.7−1.2V I I Input HIGH Current V CC =Max., V IN =V CC 5µA I IH Input HIGH Current V CC =Max., V IN =2.7V ±1µA I IL Input LOW CurrentV CC =Max., V IN =0.5V ±1µA I OS Output Short Circuit Current [7]V CC =Max., V OUT =0.0V −60−120−225mA I OFFPower-Off DisableV CC =0V , V OUT =4.5V±1µANotes:1.H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.2.Unless otherwise noted, these limits are over the operating free-air temperature range.3.Unused inputs must always be connected to an appropriate logic voltage level, preferably either V CC or ground.4.T A is the “instant on” case temperature.5.Typical values are at V CC =5.0V , T A =+25˚C ambient.6.This parameter is specified but not tested.7.Not more than one output should be shorted at a time.Duration of short should not exceed one second.The use of high-speed test apparatus and/or sampleand hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values.Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests.In any sequence of parameter tests, I OS tests should be performed last.Capacitance[6]Parameter Description Typ.[5]Max.Unit C IN Input Capacitance510pFC OUT Output Capacitance912pFPower Supply CharacteristicsParameter Description Test Conditions Typ.[5]Max.Unit I CC Quiescent Power Supply Current V CC=Max., V IN≤0.2V, V IN≥V CC−0.2V0.10.2mA∆I CC Quiescent Power Supply Current(TTL inputs HIGH)V CC=Max., V IN=3.4V,[8]f1=0, Outputs Open0.2 2.0mAI CCD Dynamic Power Supply Current[9]V CC=Max.,One Bit Toggling,Load Mode,50% Duty Cycle, Outputs Open,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V0.060.12mA/MHzI C Total Power Supply Current[10]V CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,One Bit T oggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V0.7 1.4mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,One Bit T oggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC,V IN=3.4V or V IN=GND1.2 3.4mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,Four Bits Toggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC, V IN≤0.2V or V IN≥V CC−0.2V1.6 3.2[11]mAV CC=Max., f0=10 MHz, Load Mode,50% Duty Cycle, Outputs Open,Four Bits Toggling at f1=5 MHz,CEP=CET=PE=GND,SR=V CC,V IN=3.4V or V IN=GND2.98.2[11]mANotes:8.Per TTL driven input (V IN=3.4V); all other inputs at V CC or GND.9.This parameter is not directly testable, but is derived for use in Total Power Supply calculations.10.I C=I QUIESCENT + I INPUTS+ I DYNAMICI C=I CC+∆I CC D H N T+I CCD(f0/2 + f1N1)I CC=Quiescent Current with CMOS input levels∆I CC=Power Supply Current for a TTL HIGH input (V IN=3.4V)D H=Duty Cycle for TTL inputs HIGHN T=Number of TTL inputs at D HI CCD=Dynamic Current caused by an input transition pair (HLH or LHL)f0=Clock frequency for registered devices, otherwise zerof1=Input signal frequencyN1=Number of inputs changing at f1All currents are in milliamps and all frequencies are in megahertz.11.Values for these conditions are examples of the I CC formula. These limits are specified but not tested.Document #: 38−00285−BSwitching Characteristics Over the Operating RangeParameter DescriptionCY54FCT163TCY74FCT163CT Unit Fig. No.[13]MilitaryCommercial Min.[12]Max.Min.[12]Max.t PLH t PHL Propagation Delay CP to Q (PE Input HIGH)2.011.5 1.5 5.8ns 1, 5t PLH t PHL Propagation Delay CP to TC (PE Input LOW)2.010.0 1.5 5.2ns 1, 5t PLH t PHL Propagation Delay CP to TC 2.016.5 1.57.8ns 1, 5t PLH t PHL Propagation Delay CET to TC 1.59.01.5 4.4ns 1, 5t S Set-Up Time, HIGH or LOW P to CP 5.5 3.5ns 4t H Hold Time, HIGH or LOW P to CP 2.0 1.5ns 4t SU Set-Up Time HIGH or LOW PE or SR to CP13.57.6ns 4t H Hold Time HIGH or LOW PE or SR to CP1.5 1.0ns 4t SU Set-Up Time HIGH or LOW CEP or CET to CP 13.07.6ns 4t H Hold Time HIGH or LOW CEP or CET to CP 00ns 4t W Clock Pulse Width (Load)HIGH or LOW5.0 4.0ns 5t WClock Pulse Width(Count)HIGH or LOW8.05.0ns5Notes:12.Minimum limits are specified but not tested on Propagation Delays.13.See “Parameter Measurement Information” in the General Information section.Ordering InformationSpeed (ns)Ordering CodePackage Name Package TypeOperating Range 5.8CY74FCT163CTQCT Q116-Lead (150-Mil) QSOP CommercialCY74FCT163CTSOC/SOCT S116-Lead (300-Mil) Molded SOIC 11.5CY54FCT163TLMBL6120-Square Leadless Chip CarrierMilitaryPackage Diagrams20-Pin Square Leadless Chip Carrier L61MIL−STD−1835 C−2A16-Lead Quarter Size Outline Q1Package Diagrams (continued)16-Lead Molded SOIC S1IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 2000, Texas Instruments Incorporated。

© 2002 Fairchild Semiconductor Corporation DS500678October 2001Revised August 200274ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs74ALVC16245Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and OutputsGeneral DescriptionThe ALVC16245 contains sixteen non-inverting bidirec-tional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device.The OE inputs disable both the A and B ports by placing them in a high impedance state.The 74ALVC16245 is designed for low voltage (1.65V to 3.6V) V CC applications with I/O compatibility up to 3.6V.The 74ALVC16245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ing low CMOS power dissipation.Featuress 1.65V–3.6V V CC supply operation s 3.6V tolerant inputs and outputs s t PD3.0 ns max for 3.0V to 3.6V V CC 3.5 ns max for 2.3V to 2.7V V CC 6.0 ns max for 1.65V to 1.95V V CCs Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1)s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78s ESD performance:Human body model > 2000V Machine model >200Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.Ordering Code:Note 2: Ordering code “G ” indicates Trays.Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Logic SymbolOrder Number Package NumberPackage Description74ALVC16245G (Note 2)(Note 3)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide74ALVC16245MTD (Note 3)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274A L V C 16245Connection DiagramsPin Assignment of TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH = HIGH Voltage Level L = LOW Voltage LevelX = Immaterial (HIGH or LOW, inputs and I/O ’s may not float)Z = High ImpedanceLogic DiagramPin Names DescriptionOE n Output Enable Input (Active LOW)T/R n Transmit/Receive InputA 0–A 15Side A Inputs or 3-STATE OutputsB 0–B 15Side B Inputs or 3-STATE Outputs NCNo Connect123456A B 0NC T/R 1OE 1NC A 0B B 2B 1NC NC A 1A 2C B 4B 3V CC V CC A 3A 4D B 6B 5GND GND A 5A 6E B 8B 7GND GND A 7A 8F B 10B 9GND GND A 9A 10G B 12B 11V CC V CC A 11A 12H B 14B 13NC NC A 13A 14JB 15NCT/R 2OE 2NCA 15InputsOutputsOE 1T/R 1L L Bus B 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7H XHIGH Z State on A 0–A 7, B 0–B 7Inputs OutputsOE 2T/R 2L L Bus B 8–B 15 Data to Bus A 8–A 15L H Bus A 8–A 15 Data to Bus B 8–B 15HXHIGH Z State on A 8–A 15, B 8–B 1574ALVC16245Absolute Maximum Ratings (Note 4)Recommended Operating Conditions (Note 6)Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.Note 5: I O Absolute Maximum Rating must be observed.Note 6: Floating or unused control inputs must be held HIGH or LOW.DC Electrical CharacteristicsSupply Voltage (V CC )−0.5V to +4.6V DC Input Voltage (V I )−0.5V to 4.6V Output Voltage (V O ) (Note 5)−0.5V to V CC +0.5VDC Input Diode Current (I IK ) V I < 0V−50 mA DC Output Diode Current (I OK )V O < 0V−50 mA DC Output Source/Sink Current (I OH /I OL )±50 mA DC V CC or GND Current per Supply Pin (I CC or GND)±100 mAStorage Temperature Range (T STG )−65°C to +150°CPower Supply Operating 1.65V to 3.6VInput Voltage 0V to V CC Output Voltage (V O )0V to V CCFree Air Operating Temperature (T A )−40°C to +85°CMinimum Input Edge Rate (∆t/∆V)V IN = 0.8V to 2.0V, V CC = 3.0V10 ns/VSymbol ParameterConditionsV CC Min MaxUnits(V)V IHHIGH Level Input Voltage1.65 - 1.950.65 x V CCV2.3 - 2.7 1.72.7 -3.62.0V ILLOW Level Input Voltage1.65 - 1.950.35 x V CCV 2.3 - 2.70.72.7 - 3.60.8V OHHIGH Level Output VoltageI OH = −100 µA 1.65 - 3.6V CC - 0.2VI OH = −4 mA 1.65 1.2I OH = −6 mA 2.3 2.0I OH = −12 mA2.3 1.72.7 2.23.02.4I OH = −24 mA3.02V OLLOW Level Output VoltageI OL = 100 µA 1.65 - 3.60.2V I OL = 4 mA 1.650.45I OL = 6 mA 2.30.4I OL = 12 mA 2.30.72.70.4I OL = 24 mA3.00.55I I Input Leakage Current 0 ≤ V I ≤ 3.6V 3.6±5.0µA I OZ 3-STATE Output Leakage 0 ≤ V O ≤ 3.6V3.6±10µA I CC Quiescent Supply Current V I = V CC or GND, I O = 0 3.640µA ∆I CCIncrease in I CC per InputV IH = V CC − 0.6V3 - 3.6750µA 474A L V C 16245AC Electrical CharacteristicsCapacitanceSymbolParameterT A = −40°C to +85°C, R L = 500ΩUnitsC L = 50 pFC L = 30 pFV CC = 3.3V ± 0.3V V CC = 2.7V V CC = 2.5V ± 0.2VV CC = 1.8V ± 0.15V MinMax Min Max Min Max Min Max t PHL , t PLH Propagation Delay 1.33 1.5 3.5 1.0 3.0 1.5 6.0ns t PZL , t PZH Output Enable Time 1.3 4.3 1.5 5.4 1.0 4.9 1.59.3ns t PLZ , t PHZOutput Disable Time1.34.21.54.71.04.21.57.6ns Symbol ParameterConditionsT A = +25°C Units V CC Typical C IN Input Capacitance V I = 0V or V CC 3.36pF C IO Input, Output Capacitance V O = 0V or V CC3.37pF C PDPower Dissipation CapacitanceOutputs Enabled f = 10 MHz, C L = 50 pF3.320pF2.52074ALVC16245AC Loading and WaveformsFIGURE 1. AC Test CircuitTABLE 1. Values for Figure 1 TABLE 2. Variable Matrix(Input Characteristics: f = 1MHz; t r = t f = 2ns; Z O = 50Ω)FIGURE 2. Waveform for Inverting and Non-inverting FunctionsFIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Open t PZL , t PLZ V L t PZH , t PHZGNDSymbol V CC3.3V ± 0.3V2.7V 2.5 ± 0.2V 1.8V ± 0.15VV mi 1.5V 1.5V V CC /2V CC /2V mo 1.5V 1.5V V CC /2V CC /2V X V OL + 0.3V V OL + 0.3V V OL + 0.15V V OL + 0.15V V Y V OH − 0.3VV OH − 0.3VV OH − 0.15V V OH − 0.15V V L6V6VV CC *2V CC *2 674A L V C 16245Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A774ALVC16245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

© 2005 Fairchild Semiconductor Corporation DS012021January 1999Revised June 200574LVT16373 • 74LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs74LVT16373 • 74LVTH16373Low Voltage 16-Bit Transparent Latch with 3-STATE OutputsGeneral DescriptionThe LVT16373 and LVTH16373 contain sixteen non-invert-ing latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.The LVTH16373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These latches are designed for low-voltage (3.3V) V CC applications, but with the capability to provide a TTL inter-face to a 5V environment. The LVT16373 and LVTH16373are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16373),also available without bushold feature (74LVT16373)s Live insertion/extraction permitteds Power Up/Power Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/ 64 mAs Functionally compatible with the 74 series 16373s Latch-up performance exceeds 500 mA s ESD performance:Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000Vs Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)Ordering Code:Note 1: BGA package available in Tape and Reel only.Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.Logic SymbolOrder Number Package Number Package Description74LVT16373GX (Note 1)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]74LVT16373MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT16373MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH16373GX (Note 1)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL]74LVTH16373MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVTH16373MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 274L V T 16373 • 74L V T H 16373Connection DiagramsPin Assignment for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin Assignments Truth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ HIGH ImpedanceO o Previous output prior to HIGH-to-LOW transition of LEPin Names DescriptionOE nOutput Enable Input (Active LOW)LE nLatch Enable Input I 0–I 15 Inputs O 0–O 15 3-STATE Outputs NC No Connect123456A O 0NC OE 1LE 1NC I 0BO 2O 1NCNC I 1I 2C O 4O 3V CC V CC I 3I 4D O 6O 5GND GND I 5I 6E O 8O 7GND GND I 7I 8F O 10O 9GND GND I 9I 10G O 12O 11V CC V CC I 11I 12H O 14O 13NC NC I 13I 14JO 15NCOE 2LE 2NCI 15InputsOutputs LE 1OE 1 I 0–I 7 O 0–O 7X H X ZH LL L H L H H LL XO o InputsOutputs LE 2OE 2 I 8–I 15 O 8–O 15X H XZ H L L L HL H H LLXO o74LVT16373 • 74LVTH16373Functional DescriptionThe LVT16373 and LVTH16373 contain sixteen D-typelatches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but inde-pendent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n ) input is HIGH, data on the D n enters the latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes. When LE n is LOW,the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE n . The 3-STATE standard outputs are controlled by the Output Enable (OE n ) input. When OE n is LOW, the standard outputs are in the 2-state mode. When OE n is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.Logic DiagramsPlease note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L V T 16373 • 74L V T H 16373Absolute Maximum Ratings (Note 3)Recommended Operating ConditionsNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.Note 4: I O Absolute Maximum Rating must be observed.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 4.6V V I DC Input Voltage 0.5 to 7.0VV O DC Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to 7.0Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA I O DC Output Current64V O ! V CC Output at HIGH State mA 128V O ! V CCOutput at LOW StateI CC DC Supply Current per Supply Pin r 64mA I GND DC Ground Current per Ground Pin r 128mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH Level Output Current 32mA I OL LOW Level Output Current 64mAT AFree-Air Operating Temperature4085q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax V IK Input Clamp Diode Voltage 2.7 1.2V I I 18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O d 0.1V or V IL Input LOW Voltage 2.7–3.60.8VV O t V CC 0.1V V OHOutput HIGH Voltage2.7–3.6V CC 0.2VI OH 100 P A 2.7 2.4I OH 8 mA 3.02.0I OH 32 mA V OLOutput LOW Voltage2.70.2V I OL 100 P A 2.70.5I OL 24 mA3.00.4I OL 16 mA 3.00.5I OL 32 mA 3.00.55I OL 64 mA I I(HOLD)Bushold Input Minimum Drive3.075P A V I 0.8V (Note 5) 75V I 2.0V I I(OD)Bushold Input Over-Drive 3.0500P A (Note 6)(Note 5)Current to Change State 500(Note 7)I IInput Current3.610P AV I 5.5V Control Pins 3.6r 1V I 0V or V CC Data Pins3.6 5V I 0V 1V I V CCI OFF Power Off Leakage Current 0r 100P A 0V d V I or V O d 5.5V I PU/PD Power Up/Down 3-STATE 0–1.5V r 100P A V O 0.5V to 3.0V Output CurrentV I GND or V CC I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.5V I OZH 3-STATE Output Leakage Current 3.65P A V O 3.0V I OZH3-STATE Output Leakage Current 3.610P A V CC V O d 5.5V74LVT16373 • 74LVTH16373DC Electrical Characteristics (Continued)Note 5: Applies to bushold versions only (74LVTH16373).Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 9)Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.AC Electrical CharacteristicsNote 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Capacitance (Note 12)Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.Symbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ Power Supply Current3.60.19mA V CC d V O d 5.5V,Outputs Disabled 'I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC 0.6V (Note 8)Other Inputs at V CC or GNDSymbol ParameterV CC T A 25q C Units Conditions (V)MinTyp MaxC L 50 pF, R L 500:V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 10)V OLVQuiet Output Minimum Dynamic V OL3.30.8V(Note 10)Symbol ParameterT A 40q C to 85q C, C L 50pF, R L 500:UnitsV CC 3.3V r 0.3V V CC 2.7VMin Max Min Max t PHL Propagation Delay 1.5 3.9 1.5 4.3ns t PLH D n to O n1.5 3.8 1.5 4.2t PHL Propagation Delay 1.9 4.2 1.9 4.4ns t PLH LE to O n1.6 4.3 1.6 4.8t PZL Output Enable Time1.3 4.3 1.3 4.9ns t PZH 1.0 4.3 1.0 5.1t PLZ Output Disable Time1.5 4.7 1.5 4.8ns t PHZ2.0 5.02.0 5.4t S Setup Time, D n to LE 1.00.8ns t H Hold Time, D n to LE 1.0 1.1ns t W LE Pulse Width3.03.0ns t OSHL Output to Output Skew (Note 11) 1.0 1.0ns t OSLH1.0 1.0Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC Open, V I 0V or V CC 4pF C OUTOutput CapacitanceV CC 3.0V, V O 0V or V CC8pF 674L V T 16373 • 74L V T H 16373Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54APreliminary74LVT16373 • 74LVTH16373Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A874L V T 16373 • 74L V T H 16373 L o w V o l t a g e 16-B i t T r a n s p a r e n t L a t c h w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

—
—
0.7
V
VCC = 2.7V to 3.6V
—
—
0.8
IIH
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IIL
IOZH
High Impedance Output Current VCC = 3.6V
IOZL
(3-State Output pins)
L
L
L
H
H
X
NOTES: 1. H = HIGH Voltage Level
X = Don’t Care L = LOW Voltage Level Z = High-Impedance
Bus B Data to Bus A Bus A Data to Bus B Z
2
元器件交易网
VCC = 3.3V
ICCL
Quiescent Power Supply Current VCC = 3.6V
VIN = GND or VCC
ICCH
Iห้องสมุดไป่ตู้CZ
3.6 ≤ VIN ≤ 5.5V(2)
∆ICC
Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND
V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to +6.5
V
TSTG Storage Temperature
–65 to +150