第6章 EDA仿真技术应用实例
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带异步清零端的4位二进制全加器设计--实体部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;带异步清零端的4位二进制全加器设计--结构体部分architecture art of adder4b isbeginprocess(clr,a,b,cin)variable sint:std_logic_vector(4 downto 0);variable aa,bb:std_logic_vector(4 downto 0);beginif clr='1' thensint:="00000";elseaa:='0'&a;bb:='0'&b;sint:=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;4位二进制全加器的仿真波形图图6-10 12位全加器电路原理12位二进制全加器的仿真波形图12位二进制全加器的逻辑图形符号1.8位串入/并出移位寄存器--实体部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shift_r isport(clr,clk,en,din:in std_logic;dout:out std_logic_vector(7 downto 0)); end;结构体部分architecture art of shift_r issignal temp:std_logic_vector(7 downto 0);beginprocess(clr,clk)beginif clr='0' thentemp<=(others=>'0');elsif(clk'event and clk='1') thenif (en='1') thentemp<=shl(temp,"1");temp(0)<=din;end if;end if;end process;dout<=temp;end art;仿真波形图10011000982.8位并入/串出移位寄存器--实体部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shift_p isport(clr,clk,en,load:in std_logic;din:in std_logic_vector(7 downto 0)；dout:out std_logic);end;结构体部分architecture art of shift_p issignal temp:std_logic_vector(7 downto 0);beginprocess(clr,clk)beginif clr='0' thentemp<=(others=>'0');elsif(clk'event and clk='1') thenif (load='1') thentemp<=din;elsif en=‘1’ thentemp<=shl(temp,"1");temp(0)<=‘0’;end if;end if;end process;dout<=temp(7);end art;仿真波形图10111100图6-23 Moore状态机框图表6-4 Moore 状态机的功能表1110S3S0S31100S3S2S21001S2S1S10010S0S1S01现态决定的输出值输入信号和现态S n+1现态S n图6-24 Moore 状态机的状态转移图实体部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity moore_state isport(clk,clr,input:in std_logic;output:out std_logic_vector(3 downto 0));end;结构体部分architecture art of moore_state istype state_type is (s0,s1,s2,s3);--状态说明signal state:state_type;beginprocess1:process(clk,clr) --主控时序进程beginif clr='1' thenstate<=s0;elsif(clk'event and clk='1') thencase state iswhen s0=>if input='0' thenstate<=s1;end if;when s1=>if input='1' thenstate<=s2;end if;when s2=>if input='1' thenstate<=s3;end if;when s3=>if input='0' then state<=s0; end if;end case;end if;end process;结构体部分(续)process2:process(state) --组合进程begincase state iswhen s0=>output<="0010";when s1=>output<="1001";when s2=>output<="1100";when s3=>output<="1110";end case;end process;end art;仿真波形图s0s1s1s2s2s3s0Moore 状态机输出只与当前状态有关，与输入信号的当前值无关。
图6-28 Mealy 状态机框图表6-5 Mealy 状态机功能表110011110110011000010S3S0S31001S3S2S20010S2S1S11001S0S1S01由输入和现态同时决定的输出值输入信号和现态S n+1现态S n图6-29 Mealy 状态机的状态转移图实体部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity mealy_state isport(clk,clr,input:in std_logic;output:out std_logic_vector(3 downto 0));end;结构体部分architecture art of mealy_state istype state_type is (s0,s1,s2,s3);signal state:state_type;beginprocess1:process(clk,clr)beginif clr='1' thenstate<=s0;elsif(clk'event and clk='1') thencase state iswhen s0=>if input='0' thenstate<=s1;end if;when s1=>if input='1' then state<=s2;end if;when s2=>if input='1' thenstate<=s3;end if;when s3=>if input='0' thenstate<=s0;end if;end case;end if;end process;结构体部分(续)process2:process(state,input)begincase state iswhen s0=>if input='0' thenoutput<="1001";elseoutput<="1100";end if;when s1=>if input='1' thenoutput<="1100";elseoutput<="0010";end if;when s2=>if input='1' thenoutput<="1110";elseoutput<="1001";end if;when s3=>if input='0' thenoutput<="0010";elseoutput<="1001";end if;end case;end process;end art;仿真波形图s0s1s0s0s0s1s1s2s3Mealy 状态机的输出是现态与所有输入的函数，随输入变化而随时发生变化。
