Distributed Interactive Video Arrays for Event Based Analysis of Incidents The Distributed

High Level Programming for Real TimeFPGA Based Image ProcessingD Crookes, K Benkrid, A Bouridane, K Alotaibi and A BenkridSchool of Computer Science, The Queen‟s University of Belfast, Belfast BT7 1NN, UK ABSTRACTReconfigurable hardware in the form of Field Programmable Gate Arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such us Image Processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution.However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, we present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Our approach is to provide a very high level Image Processing Coprocessor (IPC) with a core instruction set based on the operations of Image Algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations.1. INTRODUCTIONImage Processing application developers require high performance systems for computationally intensive Image Processing (IP) applications, often under real time requirements. In addition, developing an IP application tends to be experimental and interactive. This means the developer must be able to modify, tune or replace algorithms rapidly and conveniently.Because of the local nature of many low level IP operations (e.g. neighbourhood operations), one way of obtaining high performance in image processing has been to use parallel computing [1]. However, multiprocessor IP systems have generally speaking not yet fulfilled their promise. This is partly a matter of cost, lack of stability and software support for parallel machines; it is also a matter of communications overheads particularly if sequences of images are being captured and distributed across the processors in real time.A second way of obtaining high performance in IP applications is to use Digital Signal Processing (DSP) processors [2,3]. DSP processors provide a performance improve-ment over standard microprocessors while still maintaining a high level programming model. However, because of the software based control, DSP processors have still difficulty in coping with real time video processing.At the opposite end of the spectrum lie the dedicated hardware solutions. Application Specific Integrated Circuits (ASICs) offer a fully customised solution to a particular algorithm [4]. However, this solution suffers from a lack of flexibility, plus the high manufacturing cost and the relatively lengthy development cycle.Reconfigurable hardware solutions in the form of FPGAs [5] offer high performance, with the ability to be electrically reprogrammed dynamically to perform other algorithms. Though the first FPGAs were only capable of modest integration levels and were thus usedmainly for glue logic and system control, the latest devices [6] have crossed the Million gate barrier hence making it possible to implement an entire System On a Chip. Moreover, the introduction of the latest IC fabrication techniques has increased the maximum speed at which FPGAs can run. Design‟s performance exceeding 150MHz are no longer outside the realm of possibilities in the new FPGA parts, hence allowing FPGAs to address high bandwidth applications such as video processing.A range of commercial FPGA based custom computing systems includes: the Splash-2 system [7]; the G-800 system [8] and VCC‟s HOTWorks HOTI & HOTII development [9]. Though this solution seems to enjoy the advantages of both the dedicated solution and the software based one, many people are still reluctant to move toward this new technology because of the low level programming model offered by FPGAs. Although behavioural synthesis tools have made enormous progress [10, 11], structural design techniques (including careful floorplanning) often still result in circuits that are substantially smaller and faster than those developed using only behavioural synthesis tools [12].In order to bridge the gap between these two levels, this paper presents a high level software environment for an FPGA-based Image Processing machine, which aims to hide the hardware details from the user. The environment generates optimised architectures for specific user-defined operations, in the form of a low level netlist. Our system uses Prolog as the basic notation for describing and composing the basic building blocks. Our current implementation of the IPC is based on the Xilinx 4000 FPGA series [13].The paper first outlines the programming environment at the user level (the programming model). This includes facilities for defining low level Image Processing algorithms based on the operators of Image Algebra [14], without any reference to hardware details. Next, the design of the basic building blocks necessary for implementing the IPC instruction set are presented. Then, we describe the runtime execution environment.2. THE USER’S PROGRAMMING MODELAt its most basic level, the programming model for our image processing machine is a host processor (typically a PC programmed in C++) and an FPGA-based Image Processing Coprocessor (IPC) which carries out complete image operations (such as convolution, erosion etc.) as a single coprocessor instruction. The instruction set of the IPC provides a core of instructions based on the operators of Image Algebra. The instruction set is also extensible in the sense that new compound instructions can be defined by the user, in terms of the primitive operations in the core instruction set. (Adding a new primitive instruction is a task for an architecture designer).The coprocessor core instruction setMany IP neighbourhood operations can be described by a template (a static window with user defined weights) and one of a set of Image Algebra operators. Indeed, simple neighbourhood operations can be split in two stages:∙ A …local‟ operato r applied between an image pixel and the corresponding window coefficient.∙ A …global‟ operator applied to the set of intermediate results of the local operation, to reduce this set to a single result pixel.The set of local operators contains …Add‟ (…+‟) and …multiplication‟ (…*‟), whereas the global operator contains …Accumulation‟ (…∑‟), …Maximum‟ (…Max‟) and …Minimum‟ (…Min‟). With these local and global operators, the following neighbourhood operations can be built:For instance, a simple Laplace operation would be performed by doing convolution (i.e. Local Operation = …∑‟ and Global operation= …*‟) with the following template:The programmer interface to this instruction set is via a C++ class. First, the programmer creates the required instruction object (and its FPGA configuration), and subsequently applies it to an actual image. Creating an instruction object is generally in two phases: firstly build an object describing the operation, and then generate the configuration, in a file. For neighbourhood operations, these are carried out by two C++ object constructors:image_operator (template & operator details)image_instruction (operator object, filename)For instructions with a single template operator, these can be conveniently combined in a single constructor:Neighbourhood_instruction (template, operators, filename)The details required when building a new image operator object include:∙The dimension of the image (e.g. 256 ⨯ 256)∙The pixels size (e.g. 16 bits).∙The size of the window (e.g. 3⨯3).∙The weights of the neighbourhood window.∙The target position within the window, for aligning it with the image pixels (e.g. 1,1).∙The …local‟ and …global‟ operations.Later, to apply an instruction to an actual image, the apply method of the instruction object is used:Result = instruction_object.apply (input image)This will reconfigure the FPGA (if necessary), download the input pixel data and store the result pixels in the RAM of the IPC as they are generated.The following example shows how a programmer would create and perform a 3 by 3 Laplace operation. The image is 256 by 256; the pixel size is 16 bits.2.1 Extending the Model for Compound OperationsIn practical image processing applications, many algorithms comprise more than a single operation. Such compound operations can be broken into a number of primitive core instructions.Instruction Pipelining: A number of basic image operations can be put together in series. A typical example of two neighbourhood operations in series is the …Open‟ operation. To do an …Open‟ operation, an …Erode‟ neighbourhood operation is first performed, and the resulting image is fed into a …Dilate‟ neighbourhood operation as shown in Figure 1.Figure 1 ‘Open’ complex operationThis operation is described as follows in our high level environment:Task parallel: A number of basic image operations can be put together in parallel.For example, the Sobel edge detection algorithm can be performed (approximately) by adding the absolute results of two separate convolutions. Assuming that the FPGA has enough computing resources available, the best solution is to implement the operations in parallel using separate regions of the FPGA chip.Figure 2 Sobel complex operationThe following is an example of the code, based on our high level instruction set, to define and use a Sobel edge detection instruction. The user defines two neighbourhood operators(horizontal and vertical Sobel), and builds the image instruction by summing the absolute results from the two neighbourhood operations.The generation phase will automatically insert the appropriate delays to synchronise the two parallel operations.3. ARCHITECTURES FROM OPERATIONSWhen a new Image_instruction object(e.g. Neighbourhood_instruction) is created (by new), the corresponding FPGA configuration will be generated dynamically. In this section, we will present the structure of the FPGA configurations necessary to implement the high level instruction set for the neighbourhood operations described above. As a key example, the structure of a general 2-D convolver will be presented. Other neighbourhood operations are essentially variations of this, with different local and global operators sub-blocks.A general 2D convolverAs mentioned earlier, any neighbourhood image operation involves passing a 2-D window over an image, and carrying out a calculation at each window position.To allow each pixel to be supplied only once to the FPGA, internal line delays are required. These synchronise the supply of input values to the processing elements, ensuringthat all the pixel values involved in a particular neighbourhood operation are processed at the same instant[15, 16]. Assuming a vertical scan of the image, Figure 3 shows the architecture of a generic 2-D convolver with a P by Q template. Each Processing Element (PE) performs the necessary Multiply/Accumulate operation.Figure 3 Architecture of a generic 2-D, P by Q convolution operation Architecture of a Processing ElementBefore deriving the architecture of a Processing Element, we first have to decide which type of arithmetic to be used- either bit parallel or bit serial processing.While parallel designs process all data bits simultaneously, bit serial ones process input data one bit at a time. The required hardware for a parallel implementation is typically …n‟ times the equivalent serial implementation (for an n-bit word). On the other hand, the bit serial approach requires …n… clock cycles to process an n-bit word while the equivalent parallel one needs only one clock cycle. However, bit serial architectures operates at a higher clock frequency due to their smaller combinatorial delays. Also, the resulting layout in a serial implementation is more regular than a parallel one, because of the reduced number of interconnections needed between PEs (i.e. less routing stress). This regularity feature means that FPGA architectures generated from a high level specification can have more predictable layout and performance. Moreover, a serial architecture is not tied to a particular processing word length. It is relatively straightforward to move from one word length to another withvery little extra hardware (if any). For these reasons, we decided to implement the IPC hardware architectures using serial arithmetic.Note, secondly, that the need to pipeline the bit serial Maximum and Minimum operations common in Image Algebra suggests we should process data Most Significant Bit first (MSBF). Following on from this choice, because of problems in doing addition MSBF in 2‟s complement, there are certain advantages in using an alternative number representation to 2‟s complement. For the p urposes of the work described in this paper, we have chosen to use a redundant number representation in the form of a radix-2 Signed Digit Number system (SDNR) [17]. Because of the inherent carry-free property of SDNR add/subtract operations, the corresponding architectures can be clocked at high speed. There are of course several alternative representations which could have been chosen, each with their own advantages. However, the work presented in this paper is based on the following design choices:∙Bit serial arithmetic∙Most Significant Bit First processing∙Radix-2 Signed Digit Number Representation (SDNR) rather than 2‟s complement.Because image data may have to be occasionally processed on the host processor, the basic storage format for image data i s still, however, 2‟s complement. Therefore, processing elements first convert their incoming image data to SDNR. This also reduces the chip area required for the line buffers (in which data is held in 2‟s complement). A final unit to convert a SDNR resu lt into 2‟s complement will be needed before any results can be returned to the host system. With these considerations, a more detailed design of a general Processing Element (in terms of a local and a global operation) is given in Figure 4.Figure 4 Architecture of a standard Processing ElementDesign of the Basic Building BlocksIn what follows, we will present the physical implementation of the five basic building blocks stated in section 2 (the adder, multiplier, accumulator and maximum/ minimum units). These basic components were carefully designed in order to fit together with as little wastage as possible.The ‘multiplier’ unitThe multiplier unit used is based on a hybrid serial-parallel multiplier outlined in [18]. It multiplies a serial SDNR input with a two‟s complement parallel coefficient B=b N b N-1…b1 as shown in Figure 5. The multiplier has a modular, scaleable design, and comprises four distinct basic building components [19]: Type A, Type B, Type C and Type D. An N bit coefficient multiplier is constructed by:Type A → Type B→ (N-3)*TypeC → Type DThe coefficient word length may be varied by varying the number of type C units. On the Xilinx 4000 FPGA, Type A, B and C units occupy one CLB, and a Type D unit occupies 2 CLBs. Thus an N bit coefficient multiplier is 1 CLB wide and N+1 CLBs high. The online delay of the multiplier is 3.In+In-Figure 5 Design of an N bit hybrid serial-parallel multiplierThe ‘accumulation’ g lobal operation unitThe accumulation unit is the global operation used in the case of a convolution. It adds two SDNR operands serially and outputs the result in SDNR format as shown in Figure 6. The accumulation unit is based on a serial online adder presented in [20]. It occupies 3 CLBs laid out vertically in order to fit with the multiplier unit in a convolver design.Figure 6Block diagram and floorplan of an accumulation unitThe ‘Addition’ local operation unitThis unit is used in additive/maximum and additive/minimum operations. It takes a single SDNR input value and adds it to the corresponding window template coefficient. The coefficient is stored in 2‟s complement format into a RAM addressed by a counter whose period is the pixel word length. To keep the design compact, we have implemented the counter using Linear Feedback Shift Registers (LFSRs). The coefficient bits are preloaded into the appropriate RAM cells according to the counter output sequence. The input SDNR operand is added to the coefficient in bit serial MSBF.+-+-Figure 7. Block diagram and floorplan of an …Addition‟ local operation unitOut-Out+The adder unit occupies 3 CLBs. The whole addition unit occupies 9 CLBs laid out in a 3x3 array. The online delay of this unit is 3 clock cycles.The Maximum/Minimum unitThe Maximum unit selects the maximum of two SDNR inputs presented to its input serially, most significant bit first. Figure 10 shows the transition diagram of the finite state machine performing the maximum …O‟ of two SDNRs …X‟ and ‟Y‟. The physical impl ementation of this machine occupies an area of 13 CLBs laid out in 3 CLBs wide by 5 high. Note that this will allow this unit to fit the addition local operation in an Additive/Maximumneighbourhood operation. The online delay of this unit is 3, compatible with the online delay of the accumulation global operation.*(O=X)*(O=Y)X +X --+Figure 8. State diagram and floorplan of a Maximum unitThe minimum of two SDNRs can be determined in a similar manner knowing that Min(X,Y)=- Max(-X,-Y).5. THE COMPLETE ENVIRONMENTThe complete system is given in Figure 11. For internal working purposes, we have developed our own intermediate high level hardware description notation called HIDE4k [21]. This is Prolog-based [22], and enables highly scaleable and parameterised component descriptions to be written.In the front end, the user programs in a high level software environment (typically C++) or can interact with a Dialog-based graphical interface, specifying the IP operation to be carried out on the FPGA in terms of Local and Global operators, window template coefficients etc. The user can also specify:The desired operating speed of the circuit.∙The input pixel bit-length.∙Whether he or she wants to use our floorplanner to place the circuit or leave this task to the FPGA vendor‟s Placement and Routing tools.The system provides the option of two output circuit description formats: EDIF netlist (the normal), and VHDL at RTL level.Behind the scenes, when the user gives all the parameters needed for the specific IP operation, the intermediate HIDE code is generated. Depending on the choice of the output netlist format, the HIDE code will go through either the EDIF generator tool to generate an EDIF netlist, or the VHDL generator tool to generate a VHDL netlist. In the latter case, the resulting VHDL netlist needs to be synthesised into an EDIF netlist by a VHDL synthesiser tool. Finally, the resulting EDIF netlist will go through the FPGA vendor‟s specific tools to generate the configuration bitstream file. The whole process is invisible to the user, thus making the FPGA completely hidden from the user‟s point of view. Note that the resulting configuration is stored in a library, so it will not be regenerated if exactly the same operation happens to be defined again.Complete and efficient configurations have been produced from our high level instruction set for all the Image Algebra operations and for a variety of complex operations including…Sobel‟, …Open‟ and …Close‟. They have been successfully simulat ed using the Xilinx Foundation Project Manager CAD tools.Figure 10 presents the resulting layout for a Sobel edge detection operation on XC4036EX-2 for 256x256 input image of 8-bits pixels. An EDIF configuration file, with all the placement information, has been generated automatically by our tools from the high level description in 2.1. Note that the generator optimises the design, and uses just a single shared line buffer area for the two (task parallel) neighbourhood operations. The resulting EDIF file is fed to Xilinx PAR tools to generate the FPGA configuration bitstream. The circuit occupies 475 CLBs. Timing simulation shows that the circuit can run at a speed of 75MHz which leads to a theoretical frame rate of 143 frames per second.Figure 10 Physical configuration of Sobel operation on XC4036EX-2 Figure 11 presents the resulting layout for an 'Open' operation on XC4036EX-2 for 256x256 input image of 8-bits pixels. As previously, EDIF configuration file with all the placement information has been generated, automatically by our tools from the correspondinghigh level description presented in section 2.1. The resulting EDIF file is then fed to Xilinx PAR tools to generate the FPGA configuration bitstream. The circuit occupies 962 CLBs. Timing simulation shows that the circuit can run at a speed of 75MHz which leads to a theoretical frame rate of 133 frames per second.Figure 11 Physical configuration of Open operation on XC4036EX-26. CONCLUSIONSIn this paper, we have presented the design of an FPGA-based Image Processing Coprocessor (IPC) along with its high level programming environment. The coprocessor instruction set is based on a core level containing the operations of Image Algebra. Architectures for user-defined compound operations can be added to the system. Possibly the most significant aspect of this work is that it opens the way to image processing application developers toexploit the high performance capability of a direct hardware solution, while programming in an application-oriented model. Figures presented for actual architectures show that real time video processing rates can be achieved when staring from a high level design.The work presented in this paper is based specifically on Radix-2 SDNR, bit serial MSBF processing. In other situations, alternative number representations may be more appropriate. Sets of alternative representations are being added to the environment, including a full bit parallel implementation of the IPC [23]. This will give the user a choice when trying to satisfy competing constraints.Although our basic approach is not tied to a particular FPGA, we have implemented our system on XC4000 FPGA series. However, the special facilities provided by the new Xilinx VIRTEX family (e.g. large on-chip synchronous memory, built in Delay Locked Loops etc.) make it a very suitable target architecture for this type of application. Upgrading our system to operate on this new series of FPGA chips is underway.REFERENCES[1] Webber, H C (ed.), …Image processing and transputers‟, IOS Press, 1992.[2] Rajan, K, Sangunni, K S and Ramakrishna, J, …Dual-DSP systems for signal and image-processing‟, Microprocessing & Microsystems, Vol 17, No 9, pp 556-560, 1993.[3] Akiyama, T, Aono, H, Aoki, K, et al,…MPEG2 video codec using Image compressionDSP‟, IEEE Transactions on Consumer Electronics, Vol 40, No 3, pp 466-472, 1994. [4] L.A. Christopher, W.T. Mayweather and S.S. Perlman, …VLSI median filter for impulsenoi se elimination in composite or component TV signals‟, IEEE Transactions on Consumer Electronics, Vol 34, no. 1, pp. 263-267, 1988.[5] J. Rose and A. Sangiovanni-Vincentelli, …Architecture of Field Programmable GateArrays‟, Proceedings of the IEEE Volume 81, No7, pp 1013-1029, 1993.[6] /products/virtex/ss_vir.htm[6] Arnold, J M, Buell, D A and Davis, E G, …Splash-2‟, Proceedings of the 4th AnnualACM Symposium on Parallel Algorithms and Architectures, ACM Press, pp 316-324, June 1992.[7] Gigaops Ltd., The G-800 System, 2374 Eunice St. Berkeley, CA 94708.[8] Chan, S C, Ngai, H O and Ho, K L, …A programmable image processing system usingFPGAs‟, International Journal of Electronics, Vol 75, No 4, pp 725-730, 1993.[9] /[10] /news/pubs/snug/snug99_papers/Jaffer_Final.pdf[11] FPL99.[12] Hutchings.[13] Xilinx 4000.[14] Ritter G X, Wilson J N and Davidson J L, …Image Algebra: an overview‟, ComputerVision, Graphics and Image Processing, No 49, pp 297-331, 1990.[15] Shoup, R G, …Parameterised Convolution Filtering in an FPGA‟, More FPGAs, WMoore and W Luk (editors), Abington, EE&CS Books, pp 274, 1994.[16] Kamp, W, Kunemund, H, Soldner and Hofer, H, …Programmable 2D linear filter forvideo applications‟, IEEE Journal of Solid State Circuits, pp 735-740, 1990.[17] Avizienis A, …Signed Digit Number Representation for Fast Parallel Arithmetic”, IRETransactions on Electronic Computer, Vol. 10, pp 389-400, 1961.[18] Moran, J, Rios, I and Mene ses, J, …Signed Digit Arithmetic on FPGAs‟, More FPGAs, WMoore and W Luk (editors), Abington, EE&CS Books, pp 250, 1994.[19] Donachy, P, …Design and implementation of a high level image processing machineusing reconfigurable hardware‟, PhD Thesis, Depar tment of Computer Science, The Queen‟s University of Belfast, 1996.[20] Duprat, J, Herreros, Y and Muller, J, …Some results about on-line computation offunction‟, 9th Symposium on Computer Arithmetic, Santa Monica, September 1989. [21]D Crookes, K Alota ibi, A Bouridane, P Donachy and A Benkrid, 1998, …An Environmentfor Generating FPGA Architectures for Image Algebra-based Algorithms‟, ICIP98, Vol.3, pp. 990-994.[22]Clocksin W F and Melish C S, 1994, …Programming in Prolog‟, Springer-Verlag.。

Structural Systems to resist lateral loads Commonly Used structural SystemsWith loads measured in tens of thousands kips, there is little room in the design of high-rise buildings for excessively complex thoughts. Indeed, the better high-rise buildings carry the universal traits of simplicity of thought and clarity of expression.It does not follow that there is no room for grand thoughts. Indeed, it is with such grand thoughts that the new family of high-rise buildings has evolved. Perhaps more important, the new concepts of but a few years ago have become commonplace in today’ s technology.Omitting some concepts that are related strictly to the materials of construction, the most commonly used structural systems used in high-rise buildings can be categorized as follows:1.Moment-resisting frames.2.Braced frames, including eccentrically braced frames.3.Shear walls, including steel plate shear walls.4.Tube-in-tube structures.5.Tube-in-tube structures.6.Core-interactive structures.7.Cellular or bundled-tube systems.Particularly with the recent trend toward more complex forms, but in response also to the need for increased stiffness to resist the forces from wind and earthquake, most high-rise buildings have structural systems built up of combinations of frames, braced bents, shear walls, and related systems. Further, for the taller buildings, the majorities are composed of interactive elements in three-dimensional arrays.The method of combining these elements is the very essence of the design process for high-rise buildings. These combinations need evolve in response to environmental, functional, and cost considerations so as to provide efficient structures that provoke the architectural development to new heights. This is not to say that imaginative structural design can create great architecture. To the contrary, many examples of fine architecture have been created with only moderate support from the structural engineer, while only fine structure, not great architecture, can be developed without the genius and the leadership of a talented architect. In any event, the best of both isneeded to formulate a truly extraordinary design of a high-rise building.While comprehensive discussions of these seven systems are generally available in the literature, further discussion is warranted here .The essence of the design process is distributed throughout the discussion.Moment-Resisting FramesPerhaps the most commonly used system in low-to medium-rise buildings, the moment-resisting frame, is characterized by linear horizontal and vertical members connected essentially rigidly at their joints. Such frames are used as a stand-alone system or in combination with other systems so as to provide the needed resistance to horizontal loads. In the taller of high-rise buildings, the system is likely to be found inappropriate for a stand-alone system, this because of the difficulty in mobilizing sufficient stiffness under lateral forces.Analysis can be accomplished by STRESS, STRUDL, or a host of other appropriate computer programs; analysis by the so-called portal method of the cantilever method has no place in today’s technology.Because of the intrinsic flexibility of the column/girder intersection, and because preliminary designs should aim to highlight weaknesses of systems, it is not unusual to use center-to-center dimensions for the frame in the preliminary analysis. Of course, in the latter phases of design, a realistic appraisal in-joint deformation is essential.Braced Frame sThe braced frame, intrinsically stiffer than the moment –resisting frame, finds also greater application to higher-rise buildings. The system is characterized by linear horizontal, vertical, and diagonal members, connected simply or rigidly at their joints. It is used commonly in conjunction with other systems for taller buildings and as a stand-alone system in low-to medium-rise buildings.While the use of structural steel in braced frames is common, concrete frames are more likely to be of the larger-scale variety.Of special interest in areas of high seismicity is the use of the eccentric braced frame.Again, analysis can be by STRESS, STRUDL, or any one of a series of two –or three dimensional analysis computer programs. And again, center-to-center dimensions are used commonly in the preliminary analysis.Shear wallsThe shear wall is yet another step forward along a progression of ever-stiffer structural systems. The system is characterized by relatively thin, generally (but not always) concrete elements that provide both structural strength and separation between building functions.In high-rise buildings, shear wall systems tend to have a relatively high aspect ratio, that is, their height tends to be large compared to their width. Lacking tension in the foundation system, any structural element is limited in its ability to resist overturning moment by the width of the system and by the gravity load supported by the element. Limited to a narrow overturning, One obvious use of the system, which does have the needed width, is in the exterior walls of building, where the requirement for windows is kept small.Structural steel shear walls, generally stiffened against buckling by a concrete overlay, have found application where shear loads are high. The system, intrinsically more economical than steel bracing, is particularly effective in carrying shear loads down through the taller floors in the areas immediately above grade. The sys tem has the further advantage of having high ductility a feature of particular importance in areas of high seismicity.The analysis of shear wall systems is made complex because of the inevitable presence of large openings through these walls. Preliminary analysis can be by truss-analogy, by the finite element method, or by making use of a proprietary computer program designed to consider the interaction, or coupling, of shear walls.Framed or Braced TubesThe concept of the framed or braced or braced tube erupted into the technology with the IBM Building in Pittsburgh, but was followed immediately with the twin 110-story towers of the World Trade Center, New York and a number of other buildings .The system is characterized by three –dimensional frames, braced frames, or shear walls, forming a closed surface more or less cylindrical in nature, but of nearly any plan configuration. Because those columns that resist lateral forces are placed as far as possible from the cancroids of the system, the overall moment of inertia is increased and stiffness is very high.The analysis of tubular structures is done using three-dimensional concepts, or by two- dimensional analogy, where possible, whichever method is used, it must be capable of accounting for the effects of shear lag.The presence of shear lag, detected first in aircraft structures, is a serious limitation in the stiffness of framed tubes. The concept has limited recent applications of framed tubes to the shear of 60 stories. Designers have developed various techniques for reducing the effects of shear lag, most noticeably the use of belt trusses. This system finds application in buildings perhaps 40stories and higher. However, except for possible aesthetic considerations, belt trusses interfere with nearly every building function associated with the outside wall; the trusses are placed often at mechanical floors, mush to the disapproval of the designers of the mechanical systems. Nevertheless, as a cost-effective structural system, the belt truss works well and will likely find continued approval from designers. Numerous studies have sought to optimize the location of these trusses, with the optimum location very dependent on the number of trusses provided. Experience would indicate, however, that the location of these trusses is provided by the optimization of mechanical systems and by aesthetic considerations, as the economics of the structural system is not highly sensitive to belt truss location.Tube-in-Tube StructuresThe tubular framing system mobilizes every column in the exterior wall in resisting over-turning and shearing forces. The term‘tube-in-tube’is largely self-explanatory in that a second ring of columns, the ring surrounding the central service core of the building, is used as an inner framed or braced tube. The purpose of the second tube is to increase resistance to over turning and to increase lateral stiffness. The tubes need not be of the same character; that is, one tube could be framed, while the other could be braced.In considering this system, is important to understand clearly the difference between the shear and the flexural components of deflection, the terms being taken from beam analogy. In a framed tube, the shear component of deflection is associated with the bending deformation of columns and girders (i.e, the webs of the framed tube) while the flexural component is associated with the axial shortening and lengthening of columns (i.e, the flanges of the framed tube). In a braced tube, the shear component of deflection is associated with the axial deformation of diagonals while the flexural component of deflection is associated with the axial shortening and lengthening of columns.Following beam analogy, if plane surfaces remain plane (i.e, the floor slabs),then axial stresses in the columns of the outer tube, being farther form the neutral axis, will be substantiallylarger than the axial stresses in the inner tube. However, in the tube-in-tube design, when optimized, the axial stresses in the inner ring of columns may be as high, or even higher, than the axial stresses in the outer ring. This seeming anomaly is associated with differences in the shearing component of stiffness between the two systems. This is easiest to under-stand where the inner tube is conceived as a braced (i.e, shear-stiff) tube while the outer tube is conceived as a framed (i.e, shear-flexible) tube.Core Interactive StructuresCore interactive structures are a special case of a tube-in-tube wherein the two tubes are coupled together with some form of three-dimensional space frame. Indeed, the system is used often wherein the shear stiffness of the outer tube is zero. The United States Steel Building, Pittsburgh, illustrates the system very well. Here, the inner tube is a braced frame, the outer tube has no shear stiffness, and the two systems are coupled if they were considered as systems passing in a straight line from the “hat”structure. Note that the exterior columns would be improperly modeled if they were considered as systems passing in a straight line from the “hat”to the foundations; these columns are perhaps 15% stiffer as they follow the elastic curve of the braced core. Note also that the axial forces associated with the lateral forces in the inner columns change from tension to compression over the height of the tube, with the inflection point at about 5/8 of the height of the tube. The outer columns, of course, carry the same axial force under lateral load for the full height of the columns because the columns because the shear stiffness of the system is close to zero.The space structures of outrigger girders or trusses, that connect the inner tube to the outer tube, are located often at several levels in the building. The AT&T headquarters is an example of an astonishing array of interactive elements:1.The structural system is 94 ft (28.6m) wide, 196ft(59.7m) long, and 601ft (183.3m) high.2.Two inner tubes are provided, each 31ft(9.4m) by 40 ft (12.2m), centered 90 ft (27.4m) apart in the long direction of the building.3.The inner tubes are braced in the short direction, but with zero shear stiffness in the long direction.4. A single outer tube is supplied, which encircles the building perimeter.5.The outer tube is a moment-resisting frame, but with zero shear stiffness for the center50ft (15.2m) of each of the long sides.6. A space-truss hat structure is provided at the top of the building.7. A similar space truss is located near the bottom of the building8.The entire assembly is laterally supported at the base on twin steel-plate tubes, because the shear stiffness of the outer tube goes to zero at the base of the building.Cellular structuresA classic example of a cellular structure is the Sears Tower, Chicago, a bundled tube structure of nine separate tubes. While the Sears Tower contains nine nearly identical tubes, the basic structural system has special application for buildings of irregular shape, as the several tubes need not be similar in plan shape, It is not uncommon that some of the individual tubes one of the strengths and one of the weaknesses of the system.This special weakness of this system, particularly in framed tubes, has to do with the concept of differential column shortening. The shortening of a column under load is given by the expression△=ΣfL/EFor buildings of 12 ft (3.66m) floor-to-floor distances and an average compressive stress of 15 ksi (138MPa), the shortening of a column under load is 15 (12)(12)/29,000 or 0.074in (1.9mm) per story. At 50 stories, the column will have shortened to 3.7 in. (94mm) less than its unstressed length. Where one cell of a bundled tube system is, say, 50stories high and an adjacent cell is, say, 100stories high, those columns near the boundary between .the two systems need to have this differential deflection reconciled.Major structural work has been found to be needed at such locations. In at least one building, the Rialto Project, Melbourne, the structural engineer found it necessary to vertically pre-stress the lower height columns so as to reconcile the differential deflections of columns in close proximity with the post-tensioning of the shorter column simulating the weight to be added on to adjacent, higher columns。

其它-专业英语-IT专业英语词汇精选(U)U unit 装置；部件；单元U update 更新U user 用户U you 你〖网语〗U.N.S.C. United Nations Statistical Commission 联合国统计委员会U.N.S.O. United Nations Statistical Office 联合国统计局U / L Up – Link 上行链路ua Ukrainian SSR 乌克兰（域名）UA Ultima Ascension 《创世纪9：升天》〖游戏名〗UA Ultrasonic Attenuation 超声波衰减UA Uniform Array 一致阵列UA Unit Address 单元地址UA Universal Agent 全权代理人UA Unnumbered Acknowledgment 未编号确认UA User Agent 用户代理（程序）UA User Area 用户区UAA Universal Access Authority 通用访问权，通用存取授权UAAS Universal Accounting Automatic System 通用自动记账系统UAC Uninterrupted Automatic Control 不间断性自动控制UACN Universal Automated Communication Network 万国自动通信网络UAD Uniform Automatic Processing System 统一的自动处理系统UADS User Attribute Data Set 用户属性数据集UADSL Universal Asymmetric Digital Subscriber Line 通用非对称数字用户线UAF User Authorization File 用户授权文件，用户认可文件UAG Universal Address Group 通用地址组UAL User Adaptive Language 用户自适应语言UALA Universal Adaptive Logic Arrays 通用自适应逻辑阵列UAM Underwater – to – Air Missile 水下对空导弹UAM User Account Manager 用户账户管理器UAN Unattended Answering Accessory 无人看管的应答辅助设备UAN User Account Number 用户账号UAOS User Alliance for Open Systems 开放系统用户联盟UAP Universal Availability of Publications 出版物国际共享UAP User Application Program 用户应用程序UAP User Area Profile 用户区简介UAQ Usable Area Query 可用区查询UAR User Action Routine 用户活动常规UART Universal Asynchronous Receiver / Transmitter 通用异步收发器〖芯片〗UAS Universal Access System 通用存取系统UAS Unmanned Aerospace Surveillance 无人孙宙空间监视，无人航空航天管制UATE Universal Automatic Test Equipment 通用自动测试设备UAWG UADSL Working Group 通用非对称数字用户线标准工作组UAX Unit Automatic Exchange （电话）自动交换装置，小型自动电话交换机UB Upper Bound 上界，上限UB Upper Byte 高位字节.ub 无符号字节的音频文件格式〖后缀〗UBA UnBlocking Acknowledgement 分块确认UBA UniBus Adapter 单总线适配器UBB Universal Black Box 通用黑箱UBC Universal Bibliographic Control 世界目录控制UBC Universal Block Channel 通用数据块通道UBC Universal Buffer Controller 通用缓冲器控制器UBF UnBind Failure 协议撤销失败，终止会话失败UBHR User Block Handling Routine 用户块操作例程UBI UniBus Interconnect 单总线互连UBI Universal Bi – directional Interactive 通用双向交互UBIC UniBus Initialization Complete 单总线初始化完成ubiquilink 热门链接〖因特网〗UBITS Universal Bus Information Transfer System 通用总线信息传送系统UBN Unisource Business Network 单源商业网络UBNI UB Network Inc. UB 网络公司（美国网络厂商）UBR Unspecified Bit Rate 未定比特率UBR+ Unspecified Bit Rate Plus 未加说明的比特速率+UBS Unidirectional Broadcast System 单向广播系统UBSSYNTO UniBus Slave SYNc Time Out 单总线从设备同步时间结束UBSTO UniBus Select Time Out 单总线选择时间结束UBTA Uniform Binary Toggling Algorithm 统一二进制切换算法UC UnClassified 无类别，不保密UC UniChannel 单通道UC Union Carbide 联合碳化物公司（美国）UC Unisys Corp. 优利系统公司（美国，出品电脑主机）UC Unit Check 设备校验UC Universal Connectivity 通用连通性UC Universal decimal Code 通用十进制编码UC Unrecognizable Code 不可识别的代码，乱码UC Upper Case 大写字母盘UC Upper Character 高位字符UC User Class 用户类别.uc2 由UltraCompressor生成的压缩存档文件格式〖后缀〗UCA Unitized Component Assembly 通用化组件装配UCAT User Catalog 用户目录UCB UniGate Control Block 优利网关控制块（48字节数据块）UCB Unit Control Block 设备（单元）控制块UCB Universal Character Buffer 通用字符缓冲器UCB User Control Block 用户控制块UCBAR Universal Character Buffer Address Register 通用字符缓冲器地址寄存器UCC Uniform Code Council 统一编码理事会UCC Uniform Commercial Code 统一商用代码UCC Universal Category System 通用分类系统UCC Universal Conference Circuit 通用会议线路UCC Universal Conference Control 通用会议控制器UCC Universal Copyright Convention 万国版权公约UCC Utility Control Center 实用程序控制中心UCCS Universal Camera Control System 通用摄像机控制系统UCD Uniform Call Distribution(-or) 统一呼叫分配（器）UCDOS Universal Chinese Disk Operation System 通用中文磁盘操作系统UCDP UnCorrected Data Processor 漏校数据处理器UCE Unit Checkout Equipment 部件校验设备UCE Unit Control Error 部件控制误差UCF Unit Control File 部件控制文件UCG Universal Call Generator 一般调用发生器UCI User Class Identifier 用户类别标识符，用户级标识符UCIC Unequipped Circuit Identification Code 未配备的线路识别码UCIPS University of Canterbury Image – Processing System 坎特伯雷大学图像处理系统UCL Universal Communications Language 通用通信语言UCL Update Control List 更新控制表UCL Upper Control Limit 上控制限度UCLAN User Cluster Language 用户群语言UCM Unit Control Module 部件控制模块UCM Universal Communication Monitor 通用通信监视器UCM User Communication Manager 用户通信管理器UCMI Unit Control Module Identifier 部件控制模块标识符UCMT Unit Control Module Table 部件控制模块表.ucn 由UltraCompressor II生成的新压缩存档文件格式〖后缀〗UCP User Controlled Path 用户控制的路径UCPA Upper Command Packet Address 上级命令数据分组地址UCR UnConditioned Response 无条件响应UCS Universal Call Sequence 通用调用顺序UCS Universal Card Scanner 通用卡片扫描器（IBM研制）UCS Universal Character Set 通用字符集UCS Universal Classification System 通用分类系统UCS User Control Store 用户控制存储UCSB Universal Controller – System Bus 通用控制器系统总线UCSD Unitized Channel Storage Device 单元化通道存储装置UCSD Universal Communication Switching Device 通用通信转换装置UCSR Universal Code Synchronous Receiver 通用码同步接收机UCST Universal Code Synchronous Transmitter 通用码同步发送器UCT Universal Coordinated Time 通用的调整时间UCW Unit Command Word 设备命令字UCW Unit Control Word 设备控制字UCWIN Universal Chinese WINdows 通用中文窗口操作系统UD Unit Driver 部件驱动器UD User Data 用户数据UDAC User Digital Analog Controller 用户数字模拟控制器UDAS Unified Direct Access Standards 统一的直接存取标准UDB Unibus Data Block 单总线数据块UDB Universal Data Base 通用数据库UDBAS Universal Data Base Access System 通用数据库存取系统UDC Universal Decimal Classification 通用十进制分类法UDC Universal Digital Controller 通用数字控制器UDC Up – Down Counter 加减计数器UDC Upper Dead Center 上死点，上静点，死区上限UDC User Designation Code 用户指定代码UDEC Unitized Digital Electronic Calculator 单元化数字式电子计算器UDF Universal Data Format 通用数据格式UDF Universal Disk Format 通用磁盘格式UDF Unshielded twisted pair Development Forum 未屏蔽双绞线开发论坛UDF User – Defined Function 用户定义的功能，用户定义函数（子程序）.udf Photostyler的筛选文件格式〖后缀〗UDL Unifield Databased Language 单域数据库语言UDL Uniform Data Language 统一数据语言UDL Up Data Link 上行数据链路UDLC Universal Data Link Control 通用数据链路控制（通用自动计算机的）UDP User Datagram Protocol 用户数据包协议〖因特网〗UDPC Universal Digital Personal Communications 通用数字个人通信UDPRC Universal Digital Portable Radio Communication 便携式通用数字无线通信系统UDR Universal Document Reader 通用文件阅读器UDRC Utility Data Reduction Control 实用程序数据简化控制UDRC Utility Data Retrieval Control 实用程序数据检索控制UDRS Universal Data Reduction System 通用数据简化系统UDS Universal Data Structure 通用数据结构UDS Universal Data System 通用数据系统UDS Universal Distributed System 通用型分布式计算机系统UDS User Default Specification 用户缺省说明UDS Utility Definition Specifications 实用程序定义说明UDT Uniform Data Transfer 统一数据传送UDT UnitDaTa 单元数据UDT Unstructured Data Transfer 非系统化数据传送UDT User Defined Types 用户定义的样式UDTI Universal Digital Transducer Indicator 通用数字传感器指示器UDTS UnitDaTa Service 单元数据服务UDTS Universal Data Transfer Service 通用数据传送服务UDTV Ultra Definition TV 超清晰度电视UE Unit Exception 部件异常UE User Element 用户要素UE User Equipment 用户设备.ue2 由UltraCompressor II生成的加密存档文件格式〖后缀〗UEC Ultra Enterprise Cluster 超级企业群UEH User Exit Handler 用户退出处理程序UEI User Exit Interface 用户退出接口UEM User Exit Manager 用户退出管理器UERS Unusual Event Recording System 异常事件记录系统UET Universal Emulating Terminal 通用仿真终端UET User Electric Tag 用户电子标记UF Urban Factor 都市因素UF User Function 用户函数UFAM Universal File Access Method 通用文件存取方法UFC Universal Feature Card 通用特征卡UFC Universal Frequency Counter 通用频率计数器UFD User File Directory 用户文件目录UFDL Universal Forms Description Language 通用窗体描述语言UFE User Function Editor 用户函数编辑器UFET Unipolar Field – Effect Transistor 单极性场效应晶体管UFI USA Flex Inc. 美国电线公司（出品电脑主机）UFI User Friendly Interface 用户友好界面UFN until further notice 直至进一步通知〖网语〗UFO Unidentified Flying Object 不明飞行物，飞碟UFO Utility for File Operation 文件操作实用系统UFP Utility Facility Program 实用工具程序UFR Unspecified Frame Rate 未标明的帧速率UFS Universal Feature Slot 通用特性插槽UFS Universal Financial System 通用财务系统ug Uganda 乌干达（域名）UGR Universal Graphic Recorder 通用图形记录器UHCS Ultra – High Capacity Storage 超大容量存储体UHF UltraHigh Frequency 超高频UHFO UltraHigh Frequency Oscillator 超高频振荡器UHFR UltraHigh Frequency Receiver 超高频接收机UHM Universal Host Machine 通用主机UHR Ultra – High Resolution 超高分辨率UHRF Ultra High Resolution Facsimile 超高分辨率传真.uhs 二进制文件的通用暗示系统文件格式〖后缀〗UHSIC UltraHigh Speed Integrated Circuit 超高速集成电路UHV Ultra – High Voltage 超高压UI Unix International Unix 国际UI Unnumbered Information 未编号信息UI User Interface 用户接口，用户界面.ui Geoworks UI Compiler的Espire源码文件格式〖后缀〗.ui Sprint的用户接口文件格式〖后缀〗UIBPIP United International Bureaux for the Protection of Intellectual Property 国际联合保护知识产权局（瑞士，日内瓦）UIC User Identification Code 用户识别码UID User IDentifier 用户标识符UID number User IDentification number 用户识别号码UIE Universal Information Exchange 通用信息交换.uif WordPerfect for Win的windows长提示符文件格式〖后缀〗UIFN Universal International Freephone Numbers 通用国际免费电话号码.uih Geoworks UI Compiler的Espire页眉文件格式〖后缀〗UIM Ultra Intelligence Machine 超智能机UIM User Interactive Module 用户人机对话模块UIMS User Interface Management System 用户界面管理系统UIN Universal Internet Number 通用互联网号码（网络寻呼机专用）UIO Universal Input / Output 通用输入 / 输出UIOC Universal Input / Output Controller 通用输入 / 输出控制器UIP Universal Interface Processor 通用接口处理器UIS Unit Identification System 部件识别系统UIS Urban Information System 都市信息系统UIS User Interface System 用户接口系统UJCL Universal Job Control Language 通用作业控制语言UJP Ultra Java Processor 超级“爪哇”处理器UJT Unijunction Transistor 单结晶体管uk United Kingdom 英国（域名）UKAEA United Kingdom Atomic Energy Authority 英国原子能局UKB Universal KeyBoard 通用键盘UKITO United Kingdom Information Technology Organization 英国信息技术组织Uknet 美国肯塔基州立大学校园网〖因特网〗UKPO United Kingdom Post Office 英国邮政总局UL Underwriters Laboratories 保险协会实验室（美国，制定机电产品的安全规范）UL UnLoad 卸载UL UpLink 上行链路UL Upper Limit 上限UL User Language 用户语言（美国研制）.ul Ulaw音频文件格式〖后缀〗ULA Uncommitted Logic Array 自由逻辑阵列ULA Upper Layer Architecture 上层体系结构ULC Universal Logic Circuit 通用逻辑电路ULD Unit Logic Device 单元逻辑装置ULD Universal Language Definition 通用语言定义ULD Universal Language Description 通用语言描述ULD Up – Line Dumping 上一行清除.uld ProComm Plus的上传文件信息文件格式〖后缀〗ULF Ultra – Low Frequency 超低频ULG United Loan Gunmen “联合借贷枪手”（黑客名，1999.9.5侵入美国C –SPAN 有线电视网的网站）ULG Universal Logic Gate 通用逻辑门ULM Ultrasonic Light Modulator 超声波光线调节器ULM Universal Line Multiplexer 通用线路多路复用器ULMS Undersea Long – range Missile System 水下远程导弹系统ULP Upper – Layer Protocol 上层协议ULP Upper Level Protocol 高级别协议ULP User Location Protocol 用户区位协议ULS Ultra Limit Condition 极限状态ULS User Location Service 用户区位服务ULSI Ultra – Large – Scale Integration 超大规模集成（电路）ULSIC Ultra Large Scale Integrated Circuit 超大规模集成电路.ult UltraTracker的音乐文件格式〖后缀〗UltraSCSI Ultra Small Computer System Interface 超小型计算机系统接口um United States Out Islands 美国海外领地（域名）UM UnMatch 不匹配UM User Mode 用户模式UMA Unified Memory Architecture 统一内存体系结构，合一内存结构UMA Uniform Memory Access 统一内存访问UMA Universal Modeling Architecture 通用建模体系结构UMA Universal Multiple Access 通用多路存取，通用多重接入UMA Upper Memory Area 上端内存区（640K－1024K）UMADS Univac Automated Documentation System 通用自动计算机的自动文件编制系统UMB Universal Mail Box 通用邮箱UMB Upper Memory Block 上位内存块，上端内存块（UMA的）.umb MemMaker的备份文件格式〖后缀〗UMC Unibus Micro Channel 单总线微通道UMC Universal Multiline Controller 通用多线路控制器UMC 台湾联华电子公司〖厂标〗UMCPS Ultra – Micro – Computer Processor System 超微型计算机处理器系统UMCS Unattended Multipoint Communication Station 无人看管的多点通信站UMCS Universal Mobile Communication Service 通用移动通信服务UMCT Universal Move Communication Terminal 通用移动通信终端UMF Ultra Microfiche 超缩微胶片UMID Update Modification IDentifier 更新修改标识符UMIN University Medical Information Network 大学医学信息网络UMIS Urban Management Information System 城市管理信息系统UML Unified Modeling Language 统一建模语言，通用建模语言UMLC Universal MultiLine Controller 通用多线路控制器UMMPS University of Michigan Multi – Programming System （美国）密西根大学多道程序设计系统UMRECC University of Manchester REgional Computer Center 曼彻斯特大学地区计算机中心UMS Universal Maintenance Standard 通用维修标准UMS Universal Memory System 通用内存系统（英特尔公司研制）UMS Universal Multiprogramming System 通用多路编程系统UMTS Universal Mobile Telecommunication Service 通用移动电信业务UMTS Universal Mobile Telecommunication System 通用移动电信系统（欧洲的第三代无线多媒体标准）UMTSF Universal Mobile Telecommunications Service Forum 通用移动电信业务论坛UN Unnumbered Acknowledgement 无编号确认UN Usenet News “友思网”新闻UN User's Network (Usenet) 用户网络（“友思网”）UN / EDIFACT United Nations / Electronic Data Interchange forAdministration, Commerce and Transport 联合国用于行政管理、商务和交通运输的电子数据交换UN ECE GDI United Nations Economic Community Europe General Data Interchange 联合国与欧共体的常规数据交换UNA Universal Network Access 通用网络存取UNALC User / Network Access Link Control 用户 / 网络存取链路控制UNC Universal Naming Convention 通用命名惯例，统一命名约定UNC Universal Navigation Computer 通用导航计算机UNCAST United Nations Conference of the Applications of Science and Technology 联合国科学技术应用会议UNCID United Nations Communication Interactive trade Data 联合国交互式通信贸易数据UNCL Unified Numerical Control Language 统一数控语言UNCM User Network Control Machine 用户网络控制机UNCOL UNiversal Computer – Oriented Language 面向通用计算机的语言UNCTAD United Nations Conference on Trade and Development 联合国贸发会议undelete DOS的外部命令：恢复删除文件Undernet “下网”（1992年创建的另一个因特网在线聊天服务系统）UNDIS UN Documentation Information System 联合国文献资料系统UNESCO United Nations Educational Scientific and Cultural Organization 联合国教科文组织unformat DOS的外部命令：恢复误格式化磁盘UNGA United Nation General Assembly 联合国大会UNI UNIversal 通用，万能，普遍UNI User – to – Network Interface 用户－网络接口〖ATM〗.uni MIKMOD的Unimod音乐模块文件格式〖后缀〗.uni Forecast Pro的数据文件格式〖后缀〗UNIC UN Information Center 联合国信息中心UNICOL UNIversal Computer – Oriented Language 面向通用计算机的语言UNICOM UNIversal COMpiler 通用编译程序UNICOM Universal Integrated COMmunication system 通用综合通信系统UNIDO United Nation Industrial Development Organization 联合国工业发展组织UNIFET UNIpolar Field – Effect Transistor 单极场效应晶体管U-NII Unlicensed National Information Infrastructure 未经批准的全国性信息基础设施UNINET 联通公用计算机互联网（中国）UNIPOL Universal Problem Oriented Language 面向通用问题的语言UNIPOL Universal Procedure Oriented Language 面向通用规程的语言UNIQUE Uniform Inquiry Update Element 统一查询和更新码元UNIS United Nations Information Service 联合国信息服务处Uniscan 清华紫光扫描仪〖品牌〗UNISIST United Nations Intergovernmental System of Information inScience and Technology 联合国科学技术信息交流系统UNISIST Universal System for Information in Science and Technology 国际科技情报系统UNISYS 优利系统公司（美国，见：UPCD）UNIT Universal Numerical Interchange Terminal 通用数字交换终端UNIVAC UNIVersal Automatic Computer 通用自动计算机（世界第一台商用计算机，兰德公司1951年制造，安装在美国人口普查局）UNIX (Uniplexed Information and Computer Systems) 程序设计语言统一扩充的信息和计算机系统（1969年贝尔实验室开发的多任务操作系统）UNL Universal Networking Language 通用网络语言UNMA Unified Network Management Architecture 统一网络管理体系结构〖AT&T〗UNMA Unified Network Management Architecture 统一的网络管理体系结构UNO Universal Network Object 通用网络对象UNOVAC (Universal Automatic Computer) 通用自动计算机UNPA United Nations Postal Administration 联合国邮政管理处UNPI Universal Network Programming Interface 通用网络编程接口UNPS UNiversal Power Supply 通用电源unreal 《虚幻》〖游戏名〗UNRISD United Nations Research Institute for Social Development 联合国社会发展研究学会UNSCC United Nations Standards Coordinating Committee 联合国标准协调委员会UNTDID United Nations Trade Data Interactive Document 联合国贸易数据交互式文献.unx 含有UNIX特殊信息的文本文件格式〖后缀〗UO Ultima Online 《网络创世纪》〖游戏名〗UOC Universal Output Computer 通用输出计算机UODDL User Oriented Data Display Language 面向用户的数据显示语言UOL User – Oriented Language 面向用户的语言UOS Unmanned Orbital Satellite 闲置不用的轨道卫星UP Unis Pen 紫光笔UP Unnumbered Poll 未编号轮询UP User Part 用户部分UPA User Part Available 用户部分可用UPA Ultra Port Architecture 超级端口体系结构UPACS Universal Performance Assessment and Control System 通用性能的评估控制系统UPC Uniform Product Code 产品统一编码UPC Universal Peripheral Controller 通用外围设备控制器UPC Universal Plumbing Code 通用管道设备编码UPC Universal Product Code 通用产品代码（由12位数字组成）UPC Usage Parameter Control 使用情况参数控制UPC / NPC User / Network Parameter Control 用户 / 网络参数控制UPCD Unisys PC Division 优利系统公司个人电脑分公司（美国，出品个人电脑）UPCH User Packet CHannel 用户分组信道UPD Uniform Probability Design 统一概率设计.upd 程序更新信息文件格式〖后缀〗.upd dBase的更新数据文件格式〖后缀〗UPDT UPDaTe 更新UPI Universal Peripheral Interface 通用外围设备接口UPI Universal Personal Identifier 通用个人标识符UPI User Programming Language 用户编程语言UPL Universal Programming Language 通用编程语言UPL User Programming Language 用户编程语言U-plane User plane 用户面UPN Universal Product Number 通用产品编号UPO Undistorted Power Output 不失真功率输出.upo dBase的编译更新数据文件格式〖后缀〗UPOS Universal Portable Operation System 通用可移植操作系统UPS Uninterruptible Power Supply 不间断电源UPS United Parcel Service 统一包裹服务UPS Universal Processing System 通用处理系统UPS User Process Subsystem 用户进程子系统UPSRs Unidirectional Path – Switched Rings 单项路径切换环UPT Universal Personal Telecommunication 全世界个人远程通信UPT User Part Test 用户部分测试UPT User Process Table 用户过程表UPT User Profile Table 用户简介表UPTE Ultra – Precision Test Equipment 超精度测试设备UPTN Universal Personal Telecommunication Number 通用个人远程通信编码UPU Universal Postal Union 国际邮政联盟UQCB User Queue Control Block 用户队列控制块UQT User Queue Table 用户队列表UR Unit Record 单元记录UR your 你的〖网语〗URA Uniform Resource Agent 统一资源代理URA User Requirements Analysis 用户需求分析URC Uniform Resource Citation 统一资源的引用符〖因特网〗URC Unit Record Controller 单元记录控制器URC User Request Correlation 用户请求的关联性URC Utility Radio Communication 实用无线电通信URD Unit of Recovery Descriptor 恢复描述符的部件URD User Requirements Definition 用户请求定义URDB User Requirements Data Base 用户需求数据库URET User Request Evaluation Tool 用户评估鉴定工具URI Universal Resource Identifier 通用资源标识符，统一资源识别器〖因特网〗URISA Urban and Regional Information System Association 城市与地域性信息系统协会URL Uniform Resource Locators 统一资源定位器，通用资源定位符标准，标准资源定位器（台湾用语）〖因特网〗URL Uniform Resource Locator 统一资源定位器URL User Requirements Language 用户需求语言URL User Route List 用户路由表URN Uniform Resource Name 统一资源名称〖因特网〗URO Utilization Ratio of the Object 对象利用率URP User Request Packet 用户请求信息包URS Uniform Reporting System 统一报告系统URSF Universal Remote Support Facility 通用远程支持设施URSI (Union Radio – Scientifique Internationale) 国际无线电科学协会US Undistorted Signal 未失真信号US Unit Separator 单元分隔符us United States 美国（域名）US Universal Server 通用服务器USA Universal Synchronous Asynchronous 通用同步异步USACS United States Army Computer System 美国陆军计算机系统USAEC United States Atomic Energy Commission 美国原子能委员会USAERDA United States Army Electronic Research and Development Agency 美国陆军电子研究发展局USAF United States Air Force 美国空军USAR User Security Authorization Record 用户的安全性认可记录USART Universal Synchronous Asynchronous Receiver Transmitter 通用同步异步收发器USAS United States of America Standard 美国国家标准USASCII United States of America Standard Code for Information Interchange 美国信息交换标准代码USASCSOCR USA Standard Character Set for Optical Character –Recognition 美国光学字符识别标准字符集USASI United States of America Standards Institute 美国标准学会（1966年建立，取代美国标准协会）USB Universal Serial Bus 通用串行总线（英特尔等七家世界领先计算机和通讯产业厂商共同制定的规范）USB Upper SideBand 上边带USB 硬件技术标志：有串行总线接口USBD USB Device 通用串行总线设备（包括集线器和设备单元）〖USB的五个部分之一〗USBD USB Driver 串行总线驱动程序〖USB的五个部分之一〗USBS United States Bureau of Standards 美国标准局USC Uniprocessor System Controller 单处理机系统控制器USC User Specific Channel 用户特定信道USCMI United States Commission on Mathematical Instruction 美国数学指导委员会USD United States Drone 美国遥控无人驾驶飞机USDS User Attribute Data Set 用户属性数据集USE Ubi Soft Entertainment “无比”软件娱乐公司（美国，出品MMX软件包）USE User Software Engineering 用户软件工程USEC User – Based Security Model 基于用户的安全模型USEMA United States Electronic Mail Association 美国电子邮政协会USER User System EvaluatoR 用户系统鉴别器USERID USER IDentification 用户标识符USERS (Active Users Protocol) 当前用户报告协议〖因特网〗USFS United States Frequency Standard 美国标准频率USG Unified Software Gauge 统一软件标准USG United States Gauge 美国标准规，美国标准度量USG UNIX System Group UNIX 系统组U-SHR Unidirectional Self – Healing Ring 单向自愈环USI Universal Software Interface 通用软件接口USI User / System Interface 用户系统接口USIA United States Information Agency 美国新闻署USIB United States Intelligence Board 美国情报局USIC United States Information Center 美国信息中心USICA US International Communications Agency 美国国际通信局USISL United States Information Service Library 美国新闻处图书馆USITA United States Independent Telephone Association 美国独立电话公司协会USL UNIX System Laboratories UNIX 系统实验室公司（美国）USL User Specialty Language 用户专门语言USM UnSharp Masking 模糊屏蔽USN United States Navy 美国海军USO Universal Service Order 通用服务顺序USOA Uniform Systems Of Accounts 统一账号系统USOC Universal Service Order Code 通用服务命令码USP United States Patent 美国专利USP Universal Serial Bus 通用串行总线USP User Stack Pointer 用户堆栈指示器.usp PageMaker带有美国标准码扩展字符集的打印机字体文件格式〖后缀〗USPA Ultra SPARC Port Architecture 超级可升级处理器体系结构的端口架构USPO United States Post Office 美国邮政局USPO United States Patent Office 美国专利局USPS United States Postal Service 美国邮政总局USR U.S. Robotics Corp. 美国机器人技术公司（出品网络技术设备、个人数字助理等）.usr ProComm Plus和Turbo C++ tour的用户数据库文件格式〖后缀〗USRA Universities Space Research Association 大学空间研究联合会（美国）USRMC U.S. Robotics Mobile Communications Corp. 美国机器人技术移动通信公司（出品无线PC卡）USRT Universal Synchronous Receiver / Transmitter 通用同步收发器〖芯片〗USS Uniform Symbology Specification 统一符号学规范USS United States Specification 美国（工业）规格USS United States Standard 美国（工业）标准USSB United States Satellite Broadcasting 美国卫星广播USSB Upper Single Side Band 上单边带USSBS United States Satellite Broadcasting System 美国卫星广播系统USSE User Specific Service Elements 用户特定服务单元USSG United States Standard Gauge 美国标准线规UST Unit Symbol Time 单元常数象征时间，部件符号时间USTA United States Telephone Association 美国电话协会USW Ultra Short Wave 超短波UT Unipolar field – effect Transistor 单极场效应晶体管UT Unit Test 单元测试UT United Technologies 联合技术公司（美国，高科技）UT Universal Time 国际标准时间UT Unreal Tournament 《虚幻锦标赛》〖游戏名〗UT User Terminal 用户终端UTA User Transfer Address 用户传送地址UTC Undercarpet Telephone Cable 地毯下的电话电缆UTC United Technology Center 联合技术中心UTC Universal Time Chiming 标准时间谐音报时UTC Universal Time Coordinate 标准时间配置UTC Unload Time Chain 卸载时间链UTC Utilities Telecommunications Council 公用事业电信联合会UTCLK Universal Transmitter CLocK 通用发送器时钟UTD Universal Transfer Device 通用传送设备UTI Umax Technologies Inc. “力捷精英”技术公司（美国，出品彩色扫描仪、DVD光碟、个人电脑等）UTI Unconditional Transfer Instruction 无条件转移指令UTI Unitek Technology Inc. 联合技术公司（美国，出品电脑主机）UTL User Task List 用户任务表UTL User Trailer Label 用户尾部标志，用户记录尾标UTM Universal Test Machine 通用测试机UTOL Universal Translator – Oriented Language 面向通用翻译程序的语言UTP Universal Telephony Platform 通用电话通信帄台UTP Universal Trunk Processor 通用中继线处理器UTP Universal Trunk Protocol 通用中继线协议UTP Unscreened Twisted Pair 未筛选的双绞线UTP Unshielded Twisted Paired 无屏蔽双绞线，非屏蔽双绞线UTS Unbound Task Set 无约束任务集UTS United Transfer System 联合传送系统UTS United Translation System 联合翻译系统UTS Universal Time – sharing System 通用时间分享系统，通用分时系统UTTC Universal Tape to Tape Converter 通用带间转换器UTV Underwater TeleVision 水下电视UU Ultimate User 最终用户UU Unix – to – Unix encoding Unix 到Unix 编码，UU编码〖电子邮件〗.uu 将二进制文件转换成美国标准码文本的文件格式〖后缀〗.uu 由UUDE/ENCODE生成的美国标准码压缩存档文件格式〖后缀〗UUA Univac Users Association 通用自动计算机用户协会UUCG Undefined Universal Command Group 未定义通用指令组UUCP Unix to Unix Copy Program 从Unix 到Unix 的拷贝程序UUCP Unix to Unix Copy Protocol 从Unix 到Unix 的拷贝协议（“友思网”上的主要通信协议之一）.uud 将二进制文件转换成ASCII文本的文件格式〖后缀〗.uue 将二进制文件转换成ASCII文本的文件格式〖后缀〗.uue 由UUENCODE (uuexe515.exe) 生成的美国标准码压缩存档文件格式〖后缀〗UUI User – to – User Indicators 用户对用户指示器UUI User to User Information 用户间信息UUM UMTS User Mobility 通用移动电信系统的用户机动性UUNET UNIX – to – UNIX Network Unix对Unix网络UUS User to User Signaling 用户间信令UUSCC User – to – User Signaling with Call Control 带呼叫控制的用户对用户信令UUT Unit Under Test 被测部件，待测部件UV Ultra – Violet 紫外线UV Unaware Viewers 察觉不到的观察器UV Universal Viewers 通用观察器UVC Ultraviolet Communication 紫外线通信UVGC Using Video in Group Collaboration 群体合作使用视频UVM Universal Virtual Machine 通用虚拟机UVM Universal Voice Model 通用语音模型UVROM UltraViolet – erasable ROM 紫外线可擦只读存储器UVS Universal Voltage Source 通用电压源.uw 无符号字的音频文件格式〖后缀〗uy Uruguay 乌拉圭（域名）uz Uzbekistan 乌兹别克斯坦（域名）。

ACM论文的分类问题ACM Computing Classification System (1998 Version, valid in 2006)美国计算机协会Association of Computing Machinery编制的计算机分类法。

ACM Computing Classification System一级类/class/1998/TOP.htmlA. General LiteratureB. HardwareC. Computer Systems OrganizationD. SoftwareE. DataF. Theory of ComputationG. Mathematics of ComputingH. Information SystemsI. Computing MethodologiesJ. Computer ApplicationsK. Computing Milieux具体分类见网址：/class/1998/ccs98.html∙ A. General Literatureo A.0 GENERAL▪Biographies/autobiographies▪Conference proceedings▪General literary works (e.g., fiction, plays)o A.1 INTRODUCTORY AND SURVEYo A.2 REFERENCE (e.g., dictionaries, encyclopedias, glossaries)o A.m MISCELLANEOUS∙ B. Hardwareo B.0 GENERALo B.1 CONTROL STRUCTURES AND MICROPROGRAMMING (D.3.2) ▪ B.1.0 General▪ B.1.1 Control Design Styles▪Hardwired control [**]▪Microprogrammed logic arrays [**]▪Writable control store [**]▪ B.1.2 Control Structure Performance Analysis and Design Aids▪Automatic synthesis [**]▪Formal models [**]▪Simulation [**]▪ B.1.3 Control Structure Reliability, Testing, and Fault-Tolerance [**](B.8)▪Diagnostics [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪ B.1.4 Microprogram Design Aids (D.2.2, D.2.4, D.3.2, D.3.4)▪Firmware engineering [**]▪Languages and compilers▪Machine-independent microcode generation [**]▪Optimization▪Verification [**]▪ B.1.5 Microcode Applications▪Direct data manipulation [**]▪Firmware support of operating systems/instruction sets [**]▪Instruction set interpretation▪Peripheral control [**]▪Special-purpose [**]▪ B.1.m Miscellaneouso B.2 ARITHMETIC AND LOGIC STRUCTURES▪ B.2.0 General▪ B.2.1 Design Styles (C.1.1, C.1.2)▪Calculator [**]▪Parallel▪Pipeline▪ B.2.2 Performance Analysis and Design Aids [**] (B.8)▪Simulation [**]▪Verification [**]▪Worst-case analysis [**]▪ B.2.3 Reliability, Testing, and Fault-Tolerance [**] (B.8)▪Diagnostics [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪ B.2.4 High-Speed Arithmetic▪Algorithms▪Cost/performance▪ B.2.m Miscellaneouso B.3 MEMORY STRUCTURES▪ B.3.0 General▪ B.3.1 Semiconductor Memories (B.7.1)▪Dynamic memory (DRAM)▪Read-only memory (ROM)▪Static memory (SRAM)▪ B.3.2 Design Styles (D.4.2)▪Associative memories▪Cache memories▪Interleaved memories [**]▪Mass storage (e.g., magnetic, optical, RAID)▪Primary memory▪Sequential-access memory [**]▪Shared memory▪Virtual memory▪ B.3.3 Performance Analysis and Design Aids [**] (B.8, C.4)▪Formal models [**]▪Simulation [**]▪Worst-case analysis [**]▪ B.3.4 Reliability, Testing, and Fault-Tolerance [**] (B.8)▪Diagnostics [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪ B.3.m Miscellaneouso B.4 INPUT/OUTPUT AND DA TA COMMUNICA TIONS▪ B.4.0 General▪ B.4.1 Data Communications Devices▪Processors [**]▪Receivers (e.g., voice, data, image) [**]▪Transmitters [**]▪ B.4.2 Input/Output Devices▪Channels and controllers▪Data terminals and printers▪Image display▪Voice▪ B.4.3 Interconnections (Subsystems)▪Asynchronous/synchronous operation▪Fiber optics▪Interfaces▪Parallel I/O▪Physical structures (e.g., backplanes, cables, chip carriers) [**]▪Topology (e.g., bus, point-to-point)▪ B.4.4 Performance Analysis and Design Aids [**] (B.8)▪Formal models [**]▪Simulation [**]▪Verification [**]▪Worst-case analysis [**]▪ B.4.5 Reliability, Testing, and Fault-Tolerance [**] (B.8) ▪Built-in tests [**]▪Diagnostics [**]▪Error-checking [**]▪Hardware reliability [**]▪Redundant design [**]▪Test generation [**]▪ B.4.m Miscellaneouso B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION ▪ B.5.0 General▪ B.5.1 Design▪Arithmetic and logic units▪Control design▪Data-path design▪Memory design▪Styles (e.g., parallel, pipeline, special-purpose)▪ B.5.2 Design Aids▪Automatic synthesis▪Hardware description languages▪Optimization▪Simulation▪Verification▪ B.5.3 Reliability and Testing [**] (B.8)▪Built-in tests [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪Testability [**]▪ B.5.m Miscellaneouso B.6 LOGIC DESIGN▪ B.6.0 General▪ B.6.1 Design Styles▪Cellular arrays and automata▪Combinational logic▪Logic arrays▪Memory control and access [**]▪Memory used as logic [**]▪Parallel circuits▪Sequential circuits▪ B.6.2 Reliability and Testing [**] (B.8)▪Built-in tests [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪Testability [**]▪ B.6.3 Design Aids▪Automatic synthesis▪Hardware description languages▪Optimization▪Simulation▪Switching theory▪Verification▪ B.6.m Miscellaneouso B.7 INTEGRATED CIRCUITS▪ B.7.0 General▪ B.7.1 Types and Design Styles▪Advanced technologies▪Algorithms implemented in hardware▪Gate arrays▪Input/output circuits▪Memory technologies▪Microprocessors and microcomputers▪Standard cells [**]▪VLSI (very large scale integration)▪ B.7.2 Design Aids▪Graphics▪Layout▪Placement and routing▪Simulation▪Verification▪ B.7.3 Reliability and Testing [**] (B.8)▪Built-in tests [**]▪Error-checking [**]▪Redundant design [**]▪Test generation [**]▪Testability [**]▪ B.7.m Miscellaneouso B.8 PERFORMANCE AND RELIABILITY (C.4) ▪ B.8.0 General▪ B.8.1 Reliability, Testing, and Fault-Tolerance▪ B.8.2 Performance Analysis and Design Aids▪ B.8.m Miscellaneouso B.m MISCELLANEOUS▪Design managementC. Computer Systems Organizationo C.0 GENERAL▪Hardware/software interfaces▪Instruction set design (e.g., RISC, CISC, VLIW)▪Modeling of computer architecture▪System architectures▪Systems specification methodologyo C.1 PROCESSOR ARCHITECTURES▪ C.1.0 General▪ C.1.1 Single Data Stream Architectures▪Multiple-instruction-stream, single-data-stream processors(MISD) [**]▪Pipeline processors [**]▪RISC/CISC, VLIW architectures▪Single-instruction-stream, single-data-stream processors (SISD) [**]▪Von Neumann architectures [**]▪ C.1.2 Multiple Data Stream Architectures (Multiprocessors)▪Array and vector processors▪Associative processors▪Connection machines▪Interconnection architectures (e.g., common bus, multiportmemory, crossbar switch)▪Multiple-instruction-stream, multiple-data-stream processors(MIMD)▪Parallel processors [**]▪Pipeline processors [**]▪Single-instruction-stream, multiple-data-stream processors(SIMD)▪ C.1.3 Other Architecture Styles▪Adaptable architectures▪Analog computers▪Capability architectures [**]▪Cellular architecture (e.g., mobile)▪Data-flow architectures▪Heterogeneous (hybrid) systems▪High-level language architectures [**]▪Neural nets▪Pipeline processors▪Stack-oriented processors [**]▪ C.1.4 Parallel Architectures▪Distributed architectures▪Mobile processors▪ C.1.m Miscellaneous▪Analog computers [**]▪Hybrid systems [**]o C.2 COMPUTER-COMMUNICATION NETWORKS▪ C.2.0 General▪Data communications▪Open Systems Interconnection reference model (OSI)▪Security and protection (e.g., firewalls)▪ C.2.1 Network Architecture and Design▪Asynchronous Transfer Mode (ATM)▪Centralized networks [**]▪Circuit-switching networks▪Distributed networks▪Frame relay networks▪ISDN (Integrated Services Digital Network)▪Network communications▪Network topology▪Packet-switching networks▪Store and forward networks▪Wireless communication▪ C.2.2 Network Protocols▪Applications (SMTP, FTP, etc.)▪Protocol architecture (OSI model)▪Protocol verification▪Routing protocols▪ C.2.3 Network Operations▪Network management▪Network monitoring▪Public networks▪ C.2.4 Distributed Systems▪Client/server▪Distributed applications▪Distributed databases▪Network operating systems▪ C.2.5 Local and Wide-Area Networks▪Access schemes▪Buses▪Ethernet (e.g., CSMA/CD)▪High-speed (e.g., FDDI, fiber channel, ATM)▪Internet (e.g., TCP/IP)▪Token rings▪ C.2.6 Internetworking (C.2.2)▪Routers▪Standards (e.g., TCP/IP)▪ C.2.m Miscellaneouso C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS (J.7) ▪Microprocessor/microcomputer applications▪Process control systems▪Real-time and embedded systems▪Signal processing systems▪Smartcardso C.4 PERFORMANCE OF SYSTEMS▪Design studies▪Fault tolerance▪Measurement techniques▪Modeling techniques▪Performance attributes▪Reliability, availability, and serviceabilityo C.5 COMPUTER SYSTEM IMPLEMENTA TION▪ C.5.0 General▪ C.5.1 Large and Medium (``Mainframe'') Computers▪Super (very large) computers▪ C.5.2 Minicomputers [**]▪ C.5.3 Microcomputers▪Microprocessors▪Personal computers▪Portable devices (e.g., laptops, personal digital assistants)▪Workstations▪ C.5.4 VLSI Systems▪ C.5.5 Servers▪ C.5.m Miscellaneouso C.m MISCELLANEOUSD. Softwareo D.0 GENERALo D.1 PROGRAMMING TECHNIQUES (E)▪ D.1.0 General▪ D.1.1 Applicative (Functional) Programming▪ D.1.2 Automatic Programming (I.2.2)▪ D.1.3 Concurrent Programming▪Distributed programming▪Parallel programming▪ D.1.4 Sequential Programming▪ D.1.5 Object-oriented Programming▪ D.1.6 Logic Programming▪ D.1.7 Visual Programming▪ D.1.m Miscellaneouso D.2 SOFTWARE ENGINEERING (K.6.3)▪ D.2.0 General (K.5.1)▪Protection mechanisms▪Standards▪ D.2.1 Requirements/Specifications (D.3.1)▪Elicitation methods (e.g., rapid prototyping, interviews, JAD)▪Languages▪Methodologies (e.g., object-oriented, structured)▪Tools▪ D.2.2 Design Tools and Techniques▪Computer-aided software engineering (CASE)▪Decision tables▪Evolutionary prototyping▪Flow charts▪Modules and interfaces▪Object-oriented design methods▪Petri nets▪Programmer workbench [**]▪Software libraries▪State diagrams▪Structured programming [**]▪Top-down programming [**]▪User interfaces▪ D.2.3 Coding Tools and Techniques▪Object-oriented programming▪Pretty printers▪Program editors▪Reentrant code [**]▪Standards▪Structured programming▪Top-down programming▪ D.2.4 Software/Program Verification (F.3.1)▪Assertion checkers▪Class invariants▪Correctness proofs▪Formal methods▪Model checking▪Programming by contract▪Reliability▪Statistical methods▪Validation▪ D.2.5 Testing and Debugging▪Code inspections and walk-throughs▪Debugging aids▪Diagnostics▪Distributed debugging▪Dumps [**]▪Error handling and recovery▪Monitors▪Symbolic execution▪Testing tools (e.g., data generators, coverage testing)▪Tracing▪ D.2.6 Programming Environments▪Graphical environments▪Integrated environments▪Interactive environments▪Programmer workbench▪ D.2.7 Distribution, Maintenance, and Enhancement▪Corrections [**]▪Documentation▪Enhancement [**]▪Extensibility [**]▪Portability▪Restructuring, reverse engineering, and reengineering▪Version control▪ D.2.8 Metrics (D.4.8)▪Complexity measures▪Performance measures▪Process metrics▪Product metrics▪Software science [**]▪ D.2.9 Management (K.6.3, K.6.4)▪Copyrights [**]▪Cost estimation▪Life cycle▪Productivity▪Programming teams▪Software configuration management▪Software process models (e.g., CMM, ISO, PSP)▪Software quality assurance (SQA)▪Time estimation▪ D.2.10 Design [**] (D.2.2)▪Methodologies [**]▪Representation [**]▪ D.2.11 Software Architectures▪Data abstraction▪Domain-specific architectures▪Information hiding▪Languages (e.g., description, interconnection, definition)▪Patterns (e.g., client/server, pipeline, blackboard) ▪ D.2.12 Interoperability▪Data mapping▪Distributed objects▪Interface definition languages▪ D.2.13 Reusable Software▪Domain engineering▪Reusable libraries▪Reuse models▪ D.2.m Miscellaneous▪Rapid prototyping [**]▪Reusable software [**]o D.3 PROGRAMMING LANGUAGES▪ D.3.0 General▪Standards▪ D.3.1 Formal Definitions and Theory (D.2.1, F.3.1, F.3.2, F.4.2, F.4.3) ▪Semantics▪Syntax▪ D.3.2 Language Classifications▪Applicative (functional) languages▪Concurrent, distributed, and parallel languages▪Constraint and logic languages▪Data-flow languages▪Design languages▪Extensible languages▪Macro and assembly languages▪Microprogramming languages [**]▪Multiparadigm languages▪Nondeterministic languages [**]▪Nonprocedural languages [**]▪Object-oriented languages▪Specialized application languages▪Very high-level languages▪ D.3.3 Language Constructs and Features (E.2)▪Abstract data types▪Classes and objects▪Concurrent programming structures▪Constraints▪Control structures▪Coroutines▪Data types and structures▪Dynamic storage management▪Frameworks▪Inheritance▪Input/output▪Modules, packages▪Patterns▪Polymorphism▪Procedures, functions, and subroutines▪Recursion▪ D.3.4 Processors▪Code generation▪Compilers▪Debuggers▪Incremental compilers▪Interpreters▪Memory management (garbage collection)▪Optimization▪Parsing▪Preprocessors▪Retargetable compilers▪Run-time environments▪Translator writing systems and compiler generators ▪ D.3.m Miscellaneouso D.4 OPERA TING SYSTEMS (C)▪ D.4.0 General▪ D.4.1 Process Management▪Concurrency▪Deadlocks▪Multiprocessing/multiprogramming/multitasking▪Mutual exclusion▪Scheduling▪Synchronization▪Threads▪ D.4.2 Storage Management▪Allocation/deallocation strategies▪Distributed memories▪Garbage collection▪Main memory▪Secondary storage▪Segmentation [**]▪Storage hierarchies▪Swapping [**]▪Virtual memory▪ D.4.3 File Systems Management (E.5)▪Access methods▪Directory structures▪Distributed file systems▪File organization▪Maintenance [**]▪ D.4.4 Communications Management (C.2)▪Buffering▪Input/output▪Message sending▪Network communication▪Terminal management [**]▪ D.4.5 Reliability▪Backup procedures▪Checkpoint/restart▪Fault-tolerance▪Verification▪ D.4.6 Security and Protection (K.6.5)▪Access controls▪Authentication▪Cryptographic controls▪Information flow controls▪Invasive software (e.g., viruses, worms, Trojan horses)▪Security kernels [**]▪Verification [**]▪ D.4.7 Organization and Design▪Batch processing systems [**]▪Distributed systems▪Hierarchical design [**]▪Interactive systems▪Real-time systems and embedded systems▪ D.4.8 Performance (C.4, D.2.8, I.6)▪Measurements▪Modeling and prediction▪Monitors▪Operational analysis▪Queueing theory▪Simulation▪Stochastic analysis▪ D.4.9 Systems Programs and Utilities▪Command and control languages▪Linkers [**]▪Loaders [**]▪Window managers▪ D.4.m Miscellaneouso D.m MISCELLANEOUS▪Software psychology [**]E. Datao E.0 GENERALo E.1 DA TA STRUCTURES▪Arrays▪Distributed data structures▪Graphs and networks▪Lists, stacks, and queues▪Records▪Tables [**]▪Treeso E.2 DA TA STORAGE REPRESENTATIONS▪Composite structures [**]▪Contiguous representations [**]▪Hash-table representations▪Linked representations▪Object representation▪Primitive data items [**]o E.3 DA TA ENCRYPTION▪Code breaking▪Data encryption standard (DES) [**]▪Public key cryptosystems▪Standards (e.g., DES, PGP, RSA)o E.4 CODING AND INFORMATION THEORY (H.1.1) ▪Data compaction and compression▪Error control codes▪Formal models of communication▪Nonsecret encoding schemes [**]o E.5 FILES (D.4.3, F.2.2, H.2)▪Backup/recovery▪Optimization [**]▪Organization/structure▪Sorting/searchingo E.m MISCELLANEOUSF. Theory of Computationo F.0 GENERALo F.1 COMPUTATION BY ABSTRACT DEVICES▪ F.1.0 General▪ F.1.1 Models of Computation (F.4.1)▪Automata (e.g., finite, push-down, resource-bounded)▪Bounded-action devices (e.g., Turing machines, random accessmachines)▪Computability theory▪Relations between models▪Self-modifying machines (e.g., neural networks)▪Unbounded-action devices (e.g., cellular automata, circuits,networks of machines)▪ F.1.2 Modes of Computation▪Alternation and nondeterminism▪Interactive and reactive computation▪Online computation▪Parallelism and concurrency▪Probabilistic computation▪Relations among modes [**]▪Relativized computation▪ F.1.3 Complexity Measures and Classes (F.2)▪Complexity hierarchies▪Machine-independent complexity [**]▪Reducibility and completeness▪Relations among complexity classes▪Relations among complexity measures▪ F.1.m Miscellaneouso F.2 ANAL YSIS OF ALGORITHMS AND PROBLEM COMPLEXITY (B.6, B.7,F.1.3)▪ F.2.0 General▪ F.2.1 Numerical Algorithms and Problems (G.1, G.4, I.1)▪Computation of transforms (e.g., fast Fourier transform)▪Computations in finite fields▪Computations on matrices▪Computations on polynomials▪Number-theoretic computations (e.g., factoring, primalitytesting)▪ F.2.2 Nonnumerical Algorithms and Problems (E.2, E.3, E.4, E.5, G.2,H.2, H.3)▪Complexity of proof procedures▪Computations on discrete structures▪Geometrical problems and computations▪Pattern matching▪Routing and layout▪Sequencing and scheduling▪Sorting and searching▪ F.2.3 Tradeoffs between Complexity Measures (F.1.3)▪ F.2.m Miscellaneouso F.3 LOGICS AND MEANINGS OF PROGRAMS▪ F.3.0 General▪ F.3.1 Specifying and Verifying and Reasoning about Programs (D.2.1,D.2.4, D.3.1,E.1)▪Assertions▪Invariants▪Logics of programs▪Mechanical verification▪Pre- and post-conditions▪Specification techniques▪ F.3.2 Semantics of Programming Languages (D.3.1)▪Algebraic approaches to semantics▪Denotational semantics▪Operational semantics▪Partial evaluation▪Process models▪Program analysis▪ F.3.3 Studies of Program Constructs (D.3.2, D.3.3)▪Control primitives▪Functional constructs▪Object-oriented constructs▪Program and recursion schemes▪Type structure▪ F.3.m Miscellaneouso F.4 MATHEMA TICAL LOGIC AND FORMAL LANGUAGES▪ F.4.0 General▪ F.4.1 Mathematical Logic (F.1.1, I.2.2, I.2.3, I.2.4)▪Computability theory▪Computational logic▪Lambda calculus and related systems▪Logic and constraint programming▪Mechanical theorem proving▪Modal logic▪Model theory▪Proof theory▪Recursive function theory▪Set theory▪Temporal logic▪ F.4.2 Grammars and Other Rewriting Systems (D.3.1)▪Decision problems▪Grammar types (e.g., context-free, context-sensitive)▪Parallel rewriting systems (e.g., developmental systems,L-systems)▪Parsing▪Thue systems▪ F.4.3 Formal Languages (D.3.1)▪Algebraic language theory▪Classes defined by grammars or automata (e.g., context-freelanguages, regular sets, recursive sets)▪Classes defined by resource-bounded automata [**]▪Decision problems▪Operations on languages▪ F.4.m Miscellaneouso F.m MISCELLANEOUSG. Mathematics of Computingo G.0 GENERALo G.1 NUMERICAL ANAL YSIS▪G.1.0 General▪Computer arithmetic▪Conditioning (and ill-conditioning)▪Error analysis▪Interval arithmetic▪Multiple precision arithmetic▪Numerical algorithms▪Parallel algorithms▪Stability (and instability)▪G.1.1 Interpolation (I.3.5, I.3.7)▪Difference formulas [**]▪Extrapolation▪Interpolation formulas▪Smoothing▪Spline and piecewise polynomial interpolation▪G.1.2 Approximation▪Approximation of surfaces and contours▪Chebyshev approximation and theory▪Elementary function approximation▪Fast Fourier transforms (FFT)▪Least squares approximation▪Linear approximation▪Minimax approximation and algorithms▪Nonlinear approximation▪Rational approximation▪Special function approximations▪Spline and piecewise polynomial approximation▪Wavelets and fractals▪G.1.3 Numerical Linear Algebra▪Conditioning▪Determinants [**]▪Eigenvalues and eigenvectors (direct and iterative methods)▪Error analysis▪Linear systems (direct and iterative methods)▪Matrix inversion▪Pseudoinverses [**]▪Singular value decomposition▪Sparse, structured, and very large systems (direct and iterativemethods)▪G.1.4 Quadrature and Numerical Differentiation (F.2.1)▪Adaptive and iterative quadrature▪Automatic differentiation▪Equal interval integration [**]▪Error analysis▪Finite difference methods▪Gaussian quadrature▪Iterative methods▪Multidimensional (multiple) quadrature▪G.1.5 Roots of Nonlinear Equations▪Continuation (homotopy) methods▪Convergence▪Error analysis▪Iterative methods▪Polynomials, methods for▪Systems of equations▪G.1.6 Optimization▪Constrained optimization▪Convex programming▪Global optimization▪Gradient methods▪Integer programming▪Least squares methods▪Linear programming▪Nonlinear programming▪Quadratic programming methods▪Simulated annealing▪Stochastic programming▪Unconstrained optimization▪G.1.7 Ordinary Differential Equations▪Boundary value problems▪Chaotic systems▪Convergence and stability▪Differential-algebraic equations▪Error analysis▪Finite difference methods▪Initial value problems▪Multistep and multivalue methods▪One-step (single step) methods▪Stiff equations▪G.1.8 Partial Differential Equations▪Domain decomposition methods▪Elliptic equations▪Finite difference methods▪Finite element methods▪Finite volume methods▪Hyperbolic equations▪Inverse problems▪Iterative solution techniques▪Method of lines▪Multigrid and multilevel methods▪Parabolic equations▪Spectral methods▪G.1.9 Integral Equations▪Delay equations▪Fredholm equations▪Integro-differential equations▪Volterra equations▪G.1.10 Applications▪G.1.m Miscellaneouso G.2 DISCRETE MATHEMA TICS▪G.2.0 General▪G.2.1 Combinatorics (F.2.2)▪Combinatorial algorithms▪Counting problems▪Generating functions▪Permutations and combinations▪Recurrences and difference equations ▪G.2.2 Graph Theory (F.2.2)▪Graph algorithms▪Graph labeling▪Hypergraphs▪Network problems▪Path and circuit problems▪Trees▪G.2.3 Applications▪G.2.m Miscellaneouso G.3 PROBABILITY AND STA TISTICS▪Contingency table analysis▪Correlation and regression analysis▪Distribution functions▪Experimental design▪Markov processes▪Multivariate statistics▪Nonparametric statistics▪Probabilistic algorithms (including Monte Carlo)▪Queueing theory▪Random number generation▪Reliability and life testing▪Renewal theory▪Robust regression▪Statistical computing▪Statistical software▪Stochastic processes▪Survival analysis▪Time series analysiso G.4 MATHEMA TICAL SOFTWARE▪Algorithm design and analysis▪Certification and testing▪Documentation▪Efficiency▪Parallel and vector implementations▪Portability [**]▪Reliability and robustness▪User interfaces▪Verification [**]o G.m MISCELLANEOUS▪Queueing theory [**]H. Information Systemso H.0 GENERALo H.1 MODELS AND PRINCIPLES▪H.1.0 General▪H.1.1 Systems and Information Theory (E.4)▪General systems theory▪Information theory▪Value of information▪H.1.2 User/Machine Systems▪Human factors▪Human information processing▪Software psychology▪H.1.m Miscellaneouso H.2 DATABASE MANAGEMENT (E.5)▪H.2.0 General▪Security, integrity, and protection [**]▪H.2.1 Logical Design▪Data models▪Normal forms▪Schema and subschema▪H.2.2 Physical Design▪Access methods▪Deadlock avoidance▪Recovery and restart▪H.2.3 Languages (D.3.2)▪Data description languages (DDL)▪Data manipulation languages (DML)▪Database (persistent) programming languages▪Query languages▪Report writers▪H.2.4 Systems▪Concurrency▪Distributed databases▪Multimedia databases▪Object-oriented databases▪Parallel databases▪Query processing▪Relational databases▪Rule-based databases▪Textual databases▪Transaction processing▪H.2.5 Heterogeneous Databases▪Data translation [**]▪Program translation [**]▪H.2.6 Database Machines▪H.2.7 Database Administration▪Data dictionary/directory▪Data warehouse and repository▪Logging and recovery▪Security, integrity, and protection ▪H.2.8 Database Applications▪Data mining▪Image databases▪Scientific databases▪Spatial databases and GIS▪Statistical databases▪H.2.m Miscellaneouso H.3 INFORMA TION STORAGE AND RETRIEV AL ▪H.3.0 General▪H.3.1 Content Analysis and Indexing▪Abstracting methods▪Dictionaries▪Indexing methods▪Linguistic processing▪Thesauruses▪H.3.2 Information Storage▪File organization▪Record classification [**]▪H.3.3 Information Search and Retrieval▪Clustering▪Information filtering▪Query formulation▪Relevance feedback▪Retrieval models▪Search process▪Selection process▪H.3.4 Systems and Software▪Current awareness systems (selective dissemination ofinformation--SDI) [**]▪Distributed systems▪Information networks▪Performance evaluation (efficiency and effectiveness)▪Question-answering (fact retrieval) systems [**]▪User profiles and alert services▪H.3.5 Online Information Services▪Commercial services▪Data sharing▪Web-based services▪H.3.6 Library Automation▪Large text archives▪H.3.7 Digital Libraries▪Collection▪Dissemination▪Standards▪Systems issues▪User issues▪H.3.m Miscellaneouso H.4 INFORMA TION SYSTEMS APPLICATIONS▪H.4.0 General▪H.4.1 Office Automation (I.7)▪Desktop publishing▪Equipment [**]▪Groupware▪Spreadsheets▪Time management (e.g., calendars, schedules)▪Word processing▪Workflow management▪H.4.2 Types of Systems▪Decision support (e.g., MIS)▪Logistics▪H.4.3 Communications Applications▪Bulletin boards▪Computer conferencing, teleconferencing, andvideoconferencing▪Electronic mail▪Information browsers▪Videotex▪H.4.m Miscellaneouso H.5 INFORMA TION INTERFACES AND PRESENTATION (e.g., HCI) (I.7)▪H.5.0 General▪H.5.1 Multimedia Information Systems▪Animations▪Artificial, augmented, and virtual realities▪Audio input/output▪Evaluation/methodology▪Hypertext navigation and maps [**]▪Video (e.g., tape, disk, DVI)▪H.5.2 User Interfaces (D.2.2, H.1.2, I.3.6)▪Auditory (non-speech) feedback▪Benchmarking▪Ergonomics▪Evaluation/methodology▪Graphical user interfaces (GUI)▪Haptic I/O▪Input devices and strategies (e.g., mouse, touchscreen)▪Interaction styles (e.g., commands, menus, forms, direct manipulation)▪Natural language▪Prototyping▪Screen design (e.g., text, graphics, color)▪Standardization▪Style guides▪Theory and methods▪Training, help, and documentation▪User-centered design▪User interface management systems (UIMS)▪Voice I/O▪Windowing systems▪H.5.3 Group and Organization Interfaces▪Asynchronous interaction▪Collaborative computing▪Computer-supported cooperative work▪Evaluation/methodology▪Organizational design▪Synchronous interaction▪Theory and models▪Web-based interaction▪H.5.4 Hypertext/Hypermedia (I.7, J.7)▪Architectures▪Navigation▪Theory▪User issues。

TECHNICAL SPECIFICATIONSPolycom®RealPresence Immersive Studio™ Flex Technical SpecificationsSolution Components:Room Design ElementsRealPresence Immersive Studio Flex is available in a 6-seat or 15-seat configuration with three color options: walnut, apple, and white. The standard system configuration includes a free-standing media wall, wall façade and main table.Walnut Apple WhiteRear Wall DimensionsSeating flexibility to maximize room usageTable geometry designed to support 6 participants in a call or up to 13 participants out of an immersive telepresence callOptionally add an extra rear table to support an additional 9 participantsOptional Optimized LED Lighting (for NA & EU only)To further improve the video quality, this specially-designed lighting configuration optimizes participant illumination in a comfortable diffused manner, further enabling the immersive experience with matched near end and far end illumination. If you are providing your own lighting, Polycom recommends using a lighting designer and having the lighting professionally installed. Lighting specifications are included in the Room Preparation Guide.Optional SeatingChairs are to be supplied by the customer or canbe purchased through Polycom. The chairsPolycom offers to accompany RealPresenceImmersive Studio Flex are:•Herman Miller Eames Executive•Steelcase Amia Task ChairThese chairs were chosen to complement thedécor of the system in both style and size. It isrecommended that chairs are the same size, colorand shape to maintain cohesiveness of the suite.For customers choosing to supply their ownchairs, the dimensions must NOT exceed:•Arm span: 24.5” [62.23 cm]•Wheel base: 27” [68.58 cm]Wall façade for decorative purposeUsed for improved aesthetics. Included in standardconfiguration. Not included in Media Wall-onlypurchase.Media Wall FaçadeMinimum Room DimensionsInteroperabilityContentDisplay •(1) 55” 1080p HD LCD w/LED backlightDisplay resolution •People Displays – 1080p upscaled to 4K UHD •Content Display: Full HD (1920x1080)Input Sources • (1) Analog laptop interface - VGA with 3.5 mm audio connector (main table)•(1) Digital laptop interface - HDMI with audio embedded (main table) (DisplayPort available with customer supplied adapter)•Wireless: People+Content IP, Polycom® RealPresence®Desktop or Polycom® RealPresence® MobilePeople/Content Swap •Place content on the people displays, either one or all.Also supports moving people to content screen (55”display) while people display is used for content.Content Frame Rate •5–60 fps (up to 1080p resolution at 60 fps)Content Input formats •HD (1920 x 1080i)•HD (1920 x 1080p)•WSXGA+ (1680 x 1050)•UXGA (1600 x 1200)•SXGA (1280 x 1024)•WXGA (1280 x 768)•HD (1280 x720p), XGA (1024 x 768) •SVGA (800 x 600)Content Output formats •HD (1920 x 1080) •WSXGA+ (1680 x 1050) •SXGA+ (1400 x 1050) •SXGA (1280 x 1024) •HD (1280 x 720) •XGA (1024 x 768) •VGA (640 x 480)Directory and Management SupportMultipoint ConferencingThe RealPresence Immersive Studio Flex solution provides three methods for viewing participants in a multipoint conference. In order to conduct multipoint calls, you will need a multipoint server, such as Polycom RealPresence Clariti™ or RealPresence® Collaboration Server (RMX®)with the telepresence option enabled and applicable licensing as well as Polycom’s Multipoint Layout Application (MLA). The RealPresence® Distributed Media Application™ (DMA®) (included with RealPresence Clariti) for dialing is also a requirement.•Room Continuous Presence: In this standard mode, the multipoint layout will automatically be generated. All participants will be shown on the displays. The layout will be determined either by following the general principles of Polycom Immersive Telepresence multipoint or fit a custom-set view configured by the conference administrator.•Voice Activated Room Switching (VARS): VARS is different from the standard Room Continuous Presence mode in that the speaker’s site is the only site seen by others. The view of thespeaker’s site is sized to be as large as possible on all of the other participants’ displays. Thecurrent speaker sees the previous speaker’s site (i.e., the speaker’s layout remains unchanged).Layouts used in VARS are not customizable.•Active Speaker Priority (ASP): ASP mode allocates full screen real-estate to endpoints that have speaking participants. Non speaking endpoints are put in a “film-strip” in the bottom center ofeach display. Each film-strip can accommodate five endpoints. Note that ImmersiveTelepresence rooms require a frame for each codec.BandwidthThe recommended bandwidth required depends on the customer’s application, location, required resolution and other factors. Please refer to the RealPresence®Group Series Administrator’s Guide for a detailed matrix of call speeds and resolutions. Numbers are for People and Content being shared simultaneously.*Minimum network requirement may not provide an end-to-end max frame rate / highest resolutionexperience. **Other network conditions may require additional bandwidth beyond what is recommended.LAN Connection RequirementsThe customer must provide 10 sequential static IP addresses. These will be used for the Codecs, Content monitor, SoundStructure(s), Terminal Server, Display Matrix, and RealPresence Touch.A 24-port unmanaged Ethernet switch is supplied with the system. This may be replaced with a customer-preferred device of the same capacity. If an in-room switch is used, only one LAN connection on the front wall is required.Environmental Conditions•Conference room operating temperature: 41-82° F, 5-28° C•Relative humidity: 20% to 90% (non-condensing)•Ambient Noise Level: 40 dBA or lower•Recommended NC rating: NC18 to NC25Weights and Dimensions© 2017 Polycom, Inc. All rights reserved. All Polycom® names and marks associated with Polycom products are trademarks or service marks of Polycom, Inc. and are registered or common law marks in the United States and other countries. All other trademarks are property of their respective。

计算机专业英语教程（第三版）练习答案计算机专业英语教程Array第三版练习参考答案Unit 1 [Ex 1] 1. F 2. T 3. T 4. F 5. T 6. T 7. T 8. T 9. T 10. F [Ex 2] 1. input, storage, processing, and output 2. power; speed; memory3. central processing unit4. internal; primary; memory5. keyboard; central processing unit; main memory; monitor[Ex 3] A. 1. F 2. D 3. G 4. C 5. B 6. A 7. E 8. HB. 1. user 2. monitor 3. data 4. keyboard 5. data processing6. information7. computer8. memory[Ex 4] 1. input device 2. screen, screen 3. manipulates 4. instructions 5. retrieve6. code7. hard copy8. function[Ex 5] 1. T 2. T 3. F 4. F 5. T 6. F 7. T 8. FUnit 2 [Ex 1] 1. T 2. F 3. T 4. F 5. T 6. T 7. T 8. F[Ex 2] 1. sizes, shapes, processing capabilities2. supercomputers, mainframe computers, minicomputers, microcomputers3. mainframe computer4. microcomputers, storage locations5. protables, laptop computers/notebook/palm-sized computer.desktop workstations6. semiconductor7. CPU, memory, storage, devices, processing, users8. microprocessor chip[Ex 3] A. 1. C 2. A 3. H 4. I 5. E 6. F 7. G 8. BB. 1. capacity 2. device 3. laptop computer 4. Portable computers5. Silicon6. semiconductor7. workstation8. voltage9. RAM 10. ROM[Ex 4] 1. portable 2. access 3. main memory 4. sophisiticated programs5. processing capability6. instructions7. computation8. computer professional[Ex 5] 1. T 2. T 3. T 4. F 5. F 6. T 7. F 8. T 9. F 10. T 11. F13. T 14. TUnit 3 [Ex 1] 1. T 2. F 3. T 4. T 5. T 6. T 7. F 8. F 9. T11. T 12. F 13. F 14. T[Ex 2] 1. microprocessor 2. bus 3. register 4. control unit 5. processor6. binary7. arithmetic, logical8. milliseconds,nanoseconds. 9. instruction 10. execution 11. megahertz 12. wordsize [Ex 3] A. 1. F 2. A 3. J 4. C 5. D 6. E 7. H 8. I 9. B 10. GB. 1. Storage 2. chip 3. registers 4. ALU 5. bus 6. control unit7. machine language 8. binary system 9. bits 10. computer program[Ex 4] 1. configuration 2. converts 3. data buses 4. characters3.远远不能覆盖绝⼤多数嫌疑⼈4.真正奇才所掌握的技术5.⽂件和程序6. 1. 系统详情、扩展其性能5. 敏感信息的⼈7.滞缓的特性和控制开发的复杂性8.⾮常巧妙的权宜之计，旨在解决很棘⼿的问题9.不能有效与他⼈沟通的⼈10.⼀个程序、数据结构或全部程序的11.交叉指向不合适的新闻组12.打免费长途电话了；通信⽹络，但不单指通信⽹络13.眼睛疲劳14.⽆关紧要或令⼈讨厌的琐碎问题15.不会有⼈发现这些漏洞的，或发现了也不会利⽤16.受⼈雇佣，为测试系统的安全性⽽攻⼊某个地⽅17.那种使⽤许多GOTO、例外或另外的“⾮结构的”分⽀构造18.不能定期运⾏适当的抑制程序19.某种⾮常友好程序的20.远在没有正式发⾏之前21.该技术也许不能发挥作⽤。

IT专业英语词汇精选(U)U unit 装置；部件；单元U update 更新U user 用户U you 你〖网语〗U.N.S.C. United Nations Statistical Commission 联合国统计委员会U.N.S.O. United Nations Statistical Office 联合国统计局U / L Up –Link 上行链路ua Ukrainian SSR 乌克兰（域名）UA Ultima Ascension 《创世纪9：升天》〖游戏名〗UA Ultrasonic Attenuation 超声波衰减UA Uniform Array 一致阵列UA Unit Address 单元地址UA Universal Agent 全权代理人UA Unnumbered Acknowledgment 未编号确认UA User Agent 用户代理（程序）UA User Area 用户区UAA Universal Access Authority 通用访问权，通用存取授权UAAS Universal Accounting Automatic System 通用自动记账系统UAC Uninterrupted Automatic Control 不间断性自动控制UACN Universal Automated Communication Network 万国自动通信网络UAD Uniform Automatic Processing System 统一的自动处理系统UADS User Attribute Data Set 用户属性数据集UADSL Universal Asymmetric Digital Subscriber Line 通用非对称数字用户线UAF User Authorization File 用户授权文件，用户认可文件UAG Universal Address Group 通用地址组UAL User Adaptive Language 用户自适应语言UALA Universal Adaptive Logic Arrays 通用自适应逻辑阵列UAM Underwater –to –Air Missile 水下对空导弹UAM User Account Manager 用户账户管理器UAN Unattended Answering Accessory 无人看管的应答辅助设备UAN User Account Number 用户账号UAOS User Alliance for Open Systems 开放系统用户联盟UAP Universal Availability of Publications 出版物国际共享UAP User Application Program 用户应用程序UAP User Area Profile 用户区简介UAQ Usable Area Query 可用区查询UAR User Action Routine 用户活动常规UART Universal Asynchronous Receiver / Transmitter 通用异步收发器〖芯片〗UAS Universal Access System 通用存取系统UAS Unmanned Aerospace Surveillance 无人宇宙空间监视，无人航空航天管制UA TE Universal Automatic Test Equipment 通用自动测试设备UAWG UADSL Working Group 通用非对称数字用户线标准工作组UAX Unit Automatic Exchange （电话）自动交换装置，小型自动电话交换机UB Upper Bound 上界，上限UB Upper Byte 高位字节.ub 无符号字节的音频文件格式〖后缀〗UBA UnBlocking Acknowledgement 分块确认UBA UniBus Adapter 单总线适配器UBB Universal Black Box 通用黑箱UBC Universal Bibliographic Control 世界目录控制UBC Universal Block Channel 通用数据块通道UBC Universal Buffer Controller 通用缓冲器控制器UBF UnBind Failure 协议撤销失败，终止会话失败UBHR User Block Handling Routine 用户块操作例程UBI UniBus Interconnect 单总线互连UBI Universal Bi –directional Interactive 通用双向交互UBIC UniBus Initialization Complete 单总线初始化完成ubiquilink 热门链接〖因特网〗UBITS Universal Bus Information Transfer System 通用总线信息传送系统UBN Unisource Business Network 单源商业网络UBNI UB Network Inc. UB 网络公司（美国网络厂商）UBR Unspecified Bit Rate 未定比特率UBR+ Unspecified Bit Rate Plus 未加说明的比特速率+UBS Unidirectional Broadcast System 单向广播系统UBSSYNTO UniBus Slave SYNc Time Out 单总线从设备同步时间结束UBSTO UniBus Select Time Out 单总线选择时间结束UBTA Uniform Binary Toggling Algorithm 统一二进制切换算法UC UnClassified 无类别，不保密UC UniChannel 单通道UC Union Carbide 联合碳化物公司（美国）UC Unisys Corp. 优利系统公司（美国，出品电脑主机）UC Unit Check 设备校验UC Universal Connectivity 通用连通性UC Universal decimal Code 通用十进制编码UC Unrecognizable Code 不可识别的代码，乱码UC Upper Case 大写字母盘UC Upper Character 高位字符UC User Class 用户类别.uc2 由UltraCompressor生成的压缩存档文件格式〖后缀〗UCA Unitized Component Assembly 通用化组件装配UCAT User Catalog 用户目录UCB UniGate Control Block 优利网关控制块（48字节数据块）UCB Unit Control Block 设备（单元）控制块UCB Universal Character Buffer 通用字符缓冲器UCB User Control Block 用户控制块UCBAR Universal Character Buffer Address Register 通用字符缓冲器地址寄存器UCC Uniform Code Council 统一编码理事会UCC Uniform Commercial Code 统一商用代码UCC Universal Category System 通用分类系统UCC Universal Conference Circuit 通用会议线路UCC Universal Conference Control 通用会议控制器UCC Universal Copyright Convention 万国版权公约UCC Utility Control Center 实用程序控制中心UCCS Universal Camera Control System 通用摄像机控制系统UCD Uniform Call Distribution(-or) 统一呼叫分配（器）UCDOS Universal Chinese Disk Operation System 通用中文磁盘操作系统UCDP UnCorrected Data Processor 漏校数据处理器UCE Unit Checkout Equipment 部件校验设备UCE Unit Control Error 部件控制误差UCF Unit Control File 部件控制文件UCG Universal Call Generator 一般调用发生器UCI User Class Identifier 用户类别标识符，用户级标识符UCIC Unequipped Circuit Identification Code 未配备的线路识别码UCIPS University of Canterbury Image –Processing System 坎特伯雷大学图像处理系统UCL Universal Communications Language 通用通信语言UCL Update Control List 更新控制表UCL Upper Control Limit 上控制限度UCLAN User Cluster Language 用户群语言UCM Unit Control Module 部件控制模块UCM Universal Communication Monitor 通用通信监视器UCM User Communication Manager 用户通信管理器UCMI Unit Control Module Identifier 部件控制模块标识符UCMT Unit Control Module Table 部件控制模块表.ucn 由UltraCompressor II生成的新压缩存档文件格式〖后缀〗UCP User Controlled Path 用户控制的路径UCPA Upper Command Packet Address 上级命令数据分组地址UCR UnConditioned Response 无条件响应UCS Universal Call Sequence 通用调用顺序UCS Universal Card Scanner 通用卡片扫描器（IBM研制）UCS Universal Character Set 通用字符集UCS Universal Classification System 通用分类系统UCS User Control Store 用户控制存储UCSB Universal Controller –System Bus 通用控制器系统总线UCSD Unitized Channel Storage Device 单元化通道存储装置UCSD Universal Communication Switching Device 通用通信转换装置UCSR Universal Code Synchronous Receiver 通用码同步接收机UCST Universal Code Synchronous Transmitter 通用码同步发送器UCT Universal Coordinated Time 通用的调整时间UCW Unit Command Word 设备命令字UCW Unit Control Word 设备控制字UCWIN Universal Chinese WINdows 通用中文窗口操作系统UD Unit Driver 部件驱动器UD User Data 用户数据UDAC User Digital Analog Controller 用户数字模拟控制器UDAS Unified Direct Access Standards 统一的直接存取标准UDB Unibus Data Block 单总线数据块UDB Universal Data Base 通用数据库UDBAS Universal Data Base Access System 通用数据库存取系统UDC Universal Decimal Classification 通用十进制分类法UDC Universal Digital Controller 通用数字控制器UDC Up –Down Counter 加减计数器UDC Upper Dead Center 上死点，上静点，死区上限UDC User Designation Code 用户指定代码UDEC Unitized Digital Electronic Calculator 单元化数字式电子计算器UDF Universal Data Format 通用数据格式UDF Universal Disk Format 通用磁盘格式UDF Unshielded twisted pair Development Forum 未屏蔽双绞线开发论坛UDF User –Defined Function 用户定义的功能，用户定义函数（子程序）.udf Photostyler的筛选文件格式〖后缀〗UDL Unifield Databased Language 单域数据库语言UDL Uniform Data Language 统一数据语言UDL Up Data Link 上行数据链路UDLC Universal Data Link Control 通用数据链路控制（通用自动计算机的）UDP User Datagram Protocol 用户数据包协议〖因特网〗UDPC Universal Digital Personal Communications 通用数字个人通信UDPRC Universal Digital Portable Radio Communication 便携式通用数字无线通信系统UDR Universal Document Reader 通用文件阅读器UDRC Utility Data Reduction Control 实用程序数据简化控制UDRC Utility Data Retrieval Control 实用程序数据检索控制UDRS Universal Data Reduction System 通用数据简化系统UDS Universal Data Structure 通用数据结构UDS Universal Data System 通用数据系统UDS Universal Distributed System 通用型分布式计算机系统UDS User Default Specification 用户缺省说明UDS Utility Definition Specifications 实用程序定义说明UDT Uniform Data Transfer 统一数据传送UDT UnitDaTa 单元数据UDT Unstructured Data Transfer 非系统化数据传送UDT User Defined Types 用户定义的样式UDTI Universal Digital Transducer Indicator 通用数字传感器指示器UDTS UnitDaTa Service 单元数据服务UDTS Universal Data Transfer Service 通用数据传送服务UDTV Ultra Definition TV 超清晰度电视UE Unit Exception 部件异常UE User Element 用户要素UE User Equipment 用户设备.ue2 由UltraCompressor II生成的加密存档文件格式〖后缀〗UEC Ultra Enterprise Cluster 超级企业群UEH User Exit Handler 用户退出处理程序UEI User Exit Interface 用户退出接口UEM User Exit Manager 用户退出管理器UERS Unusual Event Recording System 异常事件记录系统UET Universal Emulating Terminal 通用仿真终端UET User Electric Tag 用户电子标记UF Urban Factor 都市因素UF User Function 用户函数UFAM Universal File Access Method 通用文件存取方法UFC Universal Feature Card 通用特征卡UFC Universal Frequency Counter 通用频率计数器UFD User File Directory 用户文件目录UFDL Universal Forms Description Language 通用窗体描述语言UFE User Function Editor 用户函数编辑器UFET Unipolar Field –Effect Transistor 单极性场效应晶体管UFI USA Flex Inc. 美国电线公司（出品电脑主机）UFI User Friendly Interface 用户友好界面UFN until further notice 直至进一步通知〖网语〗UFO Unidentified Flying Object 不明飞行物，飞碟UFO Utility for File Operation 文件操作实用系统UFP Utility Facility Program 实用工具程序UFR Unspecified Frame Rate 未标明的帧速率UFS Universal Feature Slot 通用特性插槽UFS Universal Financial System 通用财务系统ug Uganda 乌干达（域名）UGR Universal Graphic Recorder 通用图形记录器UHCS Ultra –High Capacity Storage 超大容量存储体UHF UltraHigh Frequency 超高频UHFO UltraHigh Frequency Oscillator 超高频振荡器UHFR UltraHigh Frequency Receiver 超高频接收机UHM Universal Host Machine 通用主机UHR Ultra –High Resolution 超高分辨率UHRF Ultra High Resolution Facsimile 超高分辨率传真.uhs 二进制文件的通用暗示系统文件格式〖后缀〗UHSIC UltraHigh Speed Integrated Circuit 超高速集成电路UHV Ultra –High V oltage 超高压UI Unix International Unix 国际UI Unnumbered Information 未编号信息UI User Interface 用户接口，用户界面.ui Geoworks UI Compiler的Espire源码文件格式〖后缀〗.ui Sprint的用户接口文件格式〖后缀〗UIBPIP United International Bureaux for the Protection of Intellectual Property 国际联合保护知识产权局（瑞士，日内瓦）UIC User Identification Code 用户识别码UID User IDentifier 用户标识符UID number User IDentification number 用户识别号码UIE Universal Information Exchange 通用信息交换.uif WordPerfect for Win的windows长提示符文件格式〖后缀〗UIFN Universal International Freephone Numbers 通用国际免费电话号码.uih Geoworks UI Compiler的Espire页眉文件格式〖后缀〗UIM Ultra Intelligence Machine 超智能机UIM User Interactive Module 用户人机对话模块UIMS User Interface Management System 用户界面管理系统UIN Universal Internet Number 通用互联网号码（网络寻呼机专用）UIO Universal Input / Output 通用输入/ 输出UIOC Universal Input / Output Controller 通用输入/ 输出控制器UIP Universal Interface Processor 通用接口处理器UIS Unit Identification System 部件识别系统UIS Urban Information System 都市信息系统UIS User Interface System 用户接口系统UJCL Universal Job Control Language 通用作业控制语言UJP Ultra Java Processor 超级“爪哇”处理器UJT Unijunction Transistor 单结晶体管uk United Kingdom 英国（域名）UKAEA United Kingdom Atomic Energy Authority 英国原子能局UKB Universal KeyBoard 通用键盘UKITO United Kingdom Information Technology Organization 英国信息技术组织Uknet 美国肯塔基州立大学校园网〖因特网〗UKPO United Kingdom Post Office 英国邮政总局UL Underwriters Laboratories 保险协会实验室（美国，制定机电产品的安全规范）UL UnLoad 卸载UL UpLink 上行链路UL Upper Limit 上限UL User Language 用户语言（美国研制）.ul Ulaw音频文件格式〖后缀〗ULA Uncommitted Logic Array 自由逻辑阵列ULA Upper Layer Architecture 上层体系结构ULC Universal Logic Circuit 通用逻辑电路ULD Unit Logic Device 单元逻辑装置ULD Universal Language Definition 通用语言定义ULD Universal Language Description 通用语言描述ULD Up –Line Dumping 上一行清除.uld ProComm Plus的上传文件信息文件格式〖后缀〗ULF Ultra –Low Frequency 超低频ULG United Loan Gunmen “联合借贷枪手”（黑客名，1999.9.5侵入美国C –SPAN 有线电视网的网站）ULG Universal Logic Gate 通用逻辑门ULM Ultrasonic Light Modulator 超声波光线调节器ULM Universal Line Multiplexer 通用线路多路复用器ULMS Undersea Long –range Missile System 水下远程导弹系统ULP Upper –Layer Protocol 上层协议ULP Upper Level Protocol 高级别协议ULP User Location Protocol 用户区位协议ULS Ultra Limit Condition 极限状态ULS User Location Service 用户区位服务ULSI Ultra –Large –Scale Integration 超大规模集成（电路）ULSIC Ultra Large Scale Integrated Circuit 超大规模集成电路.ult UltraTracker的音乐文件格式〖后缀〗UltraSCSI Ultra Small Computer System Interface 超小型计算机系统接口um United States Out Islands 美国海外领地（域名）UM UnMatch 不匹配UM User Mode 用户模式UMA Unified Memory Architecture 统一内存体系结构，合一内存结构UMA Uniform Memory Access 统一内存访问UMA Universal Modeling Architecture 通用建模体系结构UMA Universal Multiple Access 通用多路存取，通用多重接入UMA Upper Memory Area 上端内存区（640K－1024K）UMADS Univac Automated Documentation System 通用自动计算机的自动文件编制系统UMB Universal Mail Box 通用邮箱UMB Upper Memory Block 上位内存块，上端内存块（UMA的）.umb MemMaker的备份文件格式〖后缀〗UMC Unibus Micro Channel 单总线微通道UMC Universal Multiline Controller 通用多线路控制器UMC 台湾联华电子公司〖厂标〗UMCPS Ultra –Micro –Computer Processor System 超微型计算机处理器系统UMCS Unattended Multipoint Communication Station 无人看管的多点通信站UMCS Universal Mobile Communication Service 通用移动通信服务UMCT Universal Move Communication Terminal 通用移动通信终端UMF Ultra Microfiche 超缩微胶片UMID Update Modification IDentifier 更新修改标识符UMIN University Medical Information Network 大学医学信息网络UMIS Urban Management Information System 城市管理信息系统UML Unified Modeling Language 统一建模语言，通用建模语言UMLC Universal MultiLine Controller 通用多线路控制器UMMPS University of Michigan Multi –Programming System （美国）密西根大学多道程序设计系统UMRECC University of Manchester REgional Computer Center 曼彻斯特大学地区计算机中心UMS Universal Maintenance Standard 通用维修标准UMS Universal Memory System 通用内存系统（英特尔公司研制）UMS Universal Multiprogrammi（本文来自第一范文网，转载请保留此标记。