FPGA可编程逻辑器件芯片XCZU19EG-2FFVC1760I中文规格书

Using CoolRunner-II Advanced Features Figure5 illustrates how to specify the default I/O standard for all pins in a design. The I/O standard can be selected in the Implement Design Process Properties window under the Basic Tab.Figure 5: Global I/O Standard SelectionIf a design requires multiple I/O standards on the same device, each pin must be manually declared with the appropriate I/O standard attribute. Table10 illustrates the available I/O standard attributes that can be declared.Table 10: I/O Standard AttributesI/O Standard Attribute NameLVTTL LVTTLLVCMOS 3.3V LVCMOS33LVCMOS 2.5V LVCMOS25LVCMOS 1.8V LVCMOS181.5V I/O LVCMOS15XAPP378 (v1.2) June 5, 2005White Paper: The Real Value of CoolRunner-II DataGATEWP227 (v1.1) June 29, 2005Figure 8:V CCIO Current Savings, Eight Inputs SwitchingWe have already demonstrated one of the greatest kept secrets in the CPLD world -- although V CCINT dynamic current can be quite low, V CCIO current can exceed V CCINT current by as much as 4x! It is no wonder that manufacturers do not specify V CCIO current. Instead, they focus on what appears to be an extremely low standby current, which is basically useless. They focus on dynamic V CCINT current, which is substantially less than V CCIO current.Other devices may appear to be low power, but only one device actually is low power. CoolRunner-II devices are the only CPLDs providing 99% savings on V CCINT and 99% power savings on V CCIO.Conclusion Table1 and Table2 understate the problem. Data was taken with simple buffers,showing the effect of blocking inputs into the chip. If those inputs connected tomultiple sites within the CPLD, additional power would be drawn, driving thecapacitance of the additional connections. Hence, the more complex the design, themore power is saved by blocking inputs. Because we cannot anticipate how muchlogic your inputs will drive, it is difficult to estimate how much current will be savedfor a particular design. However, one thing is certain: CoolRunner-II is the leading lowpower device not only because it has low dynamic power consumption, but alsobecause it is the only CPLD that allows a design to approach standby current duringfull operation.。

HD IOB Supported Standards Table 106: HD IOB Supported Single-Ended StandardsIOSTANDARD Required V CCOLevel for Inputand OutputINTERNAL _VREF Level forInput DRIVE and Termination OptionsLVTTL 3.3V N/A DRIVE: 4, 8, 12LVCMOS33 3.3V N/A DRIVE: 4, 8, 12LVCMOS25 2.5V N/A DRIVE: 4, 8, 12LVCMOS18 1.8V N/A DRIVE: 4, 8, 12SSTL18_I 1.8V0.9V SPLITHSTL_I_18 1.8V0.9V SPLITTable 107: HD IOB Supported Differential StandardsIOSTANDARD V CCO Level1Drive and Termination Options LVDS_25 (input only) 2.5VLVPECL (input only) 3.3VSLVS_400_25 (input only) 2.5VSUB_LVDS (input only) 1.8VDIFF_HSTL_I_18 1.8V SPLITDIFF_SSTL18_I 1.8V SPLITNotes:1.When on-die input termination is used (ODT is set to a value other than RTT_NONE) or when PULLTYPE leveragesV CCO (KEEPER or PULLUP), the V CCO input voltage is as specified. When ODT = RTT_NONE and PULLTYPE is unused,NONE, or PULLDOWN, the V CCO input voltage is any allowed voltage higher than the highest signal level applied tothe pin.HD IOB PrimitivesThe Vivado Design Suite library includes an extensive list of primitives supporting many I/Oprimitives. The generic primitives can each support most of the single-ended I/O standards:•IBUF: Input buffer•IOBUF: Bidirectional buffer•IOBUF_INTERMDISABLE: Bidirectional buffer with input buffer disable and on-die input termination disable control•OBUF: Output buffer•OBUFT: Tristate output bufferChapter 7: HD IOB ResourcesAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture ManualChapter 1: OverviewDifferences from Previous Generations Versal™ ACAPs have several important feature enhancements as well as updates to existingfeatures.XP XPHYThe following table summarizes the key differences between the UltraScale™ architecture PHY and the Versal™ architecture XPHY.Table 1: UltraScale Architecture PHY and Versal Architecture XPHY Key DifferencesFunction Versal Architecture XPHY UltraScale Architecture PHY NIBBLESLICEs per nibble6 6 or 7Nibbles per bank9 (54 pins)8 (52 pins)Serialization8:1, 4:1, 2:18:1, 4:1Deserialization1:8, 1:4, 1:21:8, 1:4Wizard required to access interface Yes NoInput and output delays625 ps (512 taps)UltraScale devices: 1250 ps (512 taps)UltraScale+ devices: 1100 ps (512 taps) Some of the other differences between the PHY architectures of UltraScale™ and Versal devices include the following:•Receive FIFO bypass support for low-latency applications•No NIBBLESLICE 0 (formerly called BITSLICE 0) instantiation requirements•The IDELAYCTRL, ISERDES, OSERDES, RXTX_BITSLICE, RX_BITSLICE, TX_BITSLICE, BITSLICE_CONTROL, and RIU_OR UNISIM primitives are not supported•The XP IOL resources are independent of the XPHY. Only one or the other can be used at a time.•Programmable logic control ports are shared between input and output delays through a delay select port•Some XPIO banks (typically located on the corner of the device) have pins that have limited function and can only be used for DDR memory controller functionality. See the Versal ACAPPackaging and Pinouts Architecture Manual (AM013) for specific pin information. Also see theVersal Architecture and Product Data Sheet: Overview (DS950).•QBC and DBC functionality has been split into two parts: Strobes now enter on XCC pins, while inter-nibble and inter-byte clocking capabilities are determined by the nibble.•The PHY can only be constructed by using the Advanced IO Wizard together with the Advanced I/O Planner (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)).AM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture Manual。

Electrical Data Generation and Measurement Methods Figure4-1 depicts an Altair BGA test fixture that is used in some of the TDR measurementson BGA packages. For TDR measurements, the DUTs for all inductance (self and mutual)are specially assembled components with all leads shorted to the internal package ground.For packages without an internal ground (i.e., QFP, PLCC, etc.), the die-paddle is usedinstead (i.e., bonds are made to the paddle). Measurement includes the wire parasitics.The DUT samples for capacitance (self and mutual) measurements are special assembledpackage units with all internal leads floating (un-bonded). In the actual testing, thelead/ball under test is isolated and all other package leads are connected to a commonpotential (ground) in the all conductor grounded (OCG) mode.The DUT interface provides a physical connection between the oscilloscope and the DUTwith minimum crosstalk and probe/DUT reflection. It also provides a small ground loopto minimize ground inductance of the fixture.UG112_c4_02_040709Figure 4-2:GTL VNA FixtureFor VNA measurements, either single-sided or two-sided measurements can be made. Inmost cases, the package to be measured is attached to a test fixture board that facilitatesholding the sample package during the measurement procedure. Two-sidedmeasurements allow characterization of the package from the bumps sites to the BGAballs. The package is held at right angles to the probing station table. Single-sidemeasurements are sometimes made when it is difficult or impossible to achieve two-sidedprobing of the package. In this case, the package is held parallel to the probe station table.In both TDR and VNA cases, measured waveforms are usually downloaded to anintegrated PC running analysis software for package parasitic model extraction. Thesoftware for TDR uses a method called the Z-profile algorithm, or the impedance-profilealgorithm, for parasitic analysis. This method translates the downloaded reflectionwaveforms into true impedance waveforms, from which package models for inductanceand capacitance are extracted.Software-Based Simulations and ExtractionsXilinx data generation approach consists of a mix of electrical models based on 2-D andFull Wave 3-D package simulations/extraction that are calibrated with time and frequencydomain measurements. Once the simulation assumptions are optimized and calibratedwith data, we deploy the extraction tools to generate per pin data and other full packageAdditional Power Management Options-0.1°C/watt — θCS from interface material data •From above, θSA ≤5.25°C/watt •The objective will be to look for a heatsink with θSA < 5.25°C/watt that meets the physical constraints in the system •Passive heatsink with some air flow — 250 LFM (1.25 m/s) can be selected •Active heatsinks — it might be possible to use small low-profile heatsinks withDC fansAdditional Power Management OptionsThe variety of applications that the FPGA devices are used in makes it a challenge to anticipate the power requirements and thus the thermal management needs a particular user might have. While Xilinx programmable devices might not be the dominating power consumers in some systems, it is conceivable that high-gate-count FPGA devices will be exercised sufficiently to generate considerable heat.In general, high-I/O and high-gate-count devices have the potential of being clocked to produce high wattage. Being aware of this potential in power needs, the package offering for these devices includes medium- and high-power-capable package options. This allows a system designer to further enhance these high-end BGA packages to handle more power.When the actual or estimated power dissipation appears to be more than the specification of the bare package, some thermal management options can be considered. The accompanying Thermal management chart illustrates the incremental nature of the recommendations — ranging from simple airflow to schemes that can include passive heatsinks and active heatsinks.Figure 3-12:Enhanced BGA with Low Profile Retainer Type Passive Heatsinks UG112_C3_11_111208。

Appendix D: Using the Xilinx Virtual Cable to DebugXVC-over-PCIe Enabled FPGA DesignTraditionally Vivado® debug is performed over JTAG. By default, Vivado tool automationconnects the Xilinx debug cores to the JTAG BSCAN resource within the FPGA to performdebug. In order to perform XVC-over-PCIe debug, this information must be transmitted over the PCIe link rather than over the JTAG cable interface. The Xilinx Debug Bridge IP allows you toconnect the debug network to PCIe through either the PCIe extended configuration interface(PCIe-XVC-VSEC) or through a PCIe BAR via an AXI4-Lite Memory Mapped interface (AXI-XVC).The Debug Bridge IP, when configured for From PCIe to BSCAN or From AXI to BSCAN,provides a connection point for the Xilinx® debug network from either the PCIe ExtendedCapability or AXI4-Lite interfaces respectively. Vivado tool automation connects this instance of the Debug Bridge to the Xilinx debug cores found in the design rather than connecting them to the JTAG BSCAN interface. There are design trade-offs to connecting the debug bridge to thePCIe Extended Configuration Space or AXI4-Lite. The following sections describe theimplementation considerations and register map for both implementations.XVC-over-PCIe Through PCIe Extended Configuration Space (PCIe-XVC-VSEC)Using the PCIe-XVC-VSEC approach, the Debug Bridge IP uses a PCIe Vendor Specific Extended Capability (VSEC) to implement the connection from PCIe to the Debug Bridge IP. The PCIeextended configuration space is set up as a linked list of extended capabilities that arediscoverable from a Host PC. This is specifically valuable for platforms where one version of the design implements the PCIe-XVC-VSEC and another design implementation does not. The linked list can be used to detect the existence or absence of the PCIe-XVC-VSEC and respondaccordingly.The PCIe Extended Configuration Interface uses PCIe configuration transactions rather than PCIe memory BAR transactions. While PCIe configuration transactions are much slower, they do not interfere with PCIe memory BAR transactions at the PCIe IP boundary. This allows for separate data and debug communication paths within the FPGA. This is ideal if you expect to debug the datapath. Even if the datapath becomes corrupt or halted, the PCIe Extended ConfigurationInterface can remain operational to perform debug. The following figure describes theconnectivity between the PCIe IP and the Debug Bridge IP to implement the PCIe-XVC-VSEC.PG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1Appendix D: Using the Xilinx Virtual Cable to DebugXVC-over-PCIe Register MapThe PCIe-XVC-VSEC and AXI-XVC have a slightly different register map that must be taken into account when designing XVC drivers and software. The register maps in the following tablesshow the byte-offset from the base address.•The PCIe-XVC-VSEC base address must fall within the valid range of the PCIe Extended Configuration space. This is specified in the Debug Bridge IP configuration.•The base address of an AXI-XVC Debug Bridge is the offset for the Debug Bridge IP peripheral that was specified in the Vivado Address Editor.The following tables describe the register map for the Debug Bridge IP as an offset from the base address when configured for the From PCIe-Ext to BSCAN or From AXI to BSCAN modes.Table 142: Debug Bridge for XVC-PCIe-VSEC Register MapRegisterOffset Register Name Description Register Type0x00PCIe Ext Capability Header PCIe defined fields for VSEC use.Read Only0x04PCIe VSEC Header PCIe defined fields for VSEC use.Read Only0x08XVC Version Register IP version and capabilities information.Read Only0x0C XVC Shift Length Register Shift length.Read Write0x10XVC TMS Register TMS data.Read Write0x14XVC TDIO Register TDO/TDI data.Read Write0x18XVC Control Register General control register.Read Write0x1C XVC Status Register General status register.Read Only Table 143: Debug Bridge for AXI-XVC Register MapRegisterOffset Register Name Description Register Type0x00XVC Shift Length Register Shift length.Read Write0x04XVC TMS Register TMS data.Read Write0x08XVC TDI Register TDI data.Read Write0x0C XVC TDO Register TDO data.Read Only0x10XVC Control Register General control register.Read Write0x14XVC Status Register General status register.Read Only0x18XVC Version Register IP version and capabilities information.Read OnlyPG195 (v4.1) April 29, 2021DMA/Bridge Subsystem for PCIe v4.1。

Table 77: Allowed Attributes for DIFF_HSTL_I and DIFF_HSTL_I_12 I/O PrimitivesAttributesIBUF/IBUFE3OBUF/OBUFT IOBUF/IOBUFE3 AllowedValues DefaultAllowedValues DefaultAllowedValues DefaultIOSTANDARD DIFF_HSTL_I, DIFF_HSTL_I_12DIFF_HSTL_I, DIFF_HSTL_I_12DIFF_HSTL_I, DIFF_HSTL_I_12ODT RTT_40, RTT_48,RTT_60RTT_48N/A RTT_40, RTT_48,RTT_60RTT_48OUTPUT_IMPE DANCE N//A RDRV_40_40,RDRV_48_48,RDRV_60_60RDRV_48_48RDRV_40_40,RDRV_48_48,RDRV_60_60RDRV_48_48SLEW N/A FAST, MEDIUM,SLOW SLOW FAST, MEDIUM,SLOWSLOWDIFF_PODThe differential (DIFF_) versions (DIFF_POD10 and DIFF_POD12) use complementary single-ended drivers for outputs and differential receivers for inputs.Table 78: Allowed Attributes for DIFF_POD10 and DIFF_POD12 I/O PrimitivesAttributesIBUF/IBUFE3OBUF/OBUFT IOBUF/IOBUFE3 AllowedValues DefaultAllowedValue DefaultAllowedValues DefaultIOSTANDARD DIFF_POD10, DIFF_POD12DIFF_POD10, DIFF_POD12DIFF_POD10, DIFF_POD12SLEW N/A FAST,MEDIUM,SLOW SLOW FAST, MEDIUM,SLOWSLOWOUTPUT_IMPED ANCE N//A RDRV_40_40,RDRV_48_48,RDRV_60_60RDRV_40_40RDRV_40_40,RDRV_48_48,RDRV_60_60RDRV_40_40ODT RTT_40, RTT_48,RTT_60RTT_40N/A N/APRE_EMPHASIS N/A RDRV_240,RDRV_NONE RDRV_NONE RDRV_240,RDRV_NONERDRV_NONEEQUALIZATION (DIFF_POD12 ONLY)EQ_LEVEL0,EQ_LEVEL1,EQ_LEVEL2,EQ_LEVEL3,EQ_LEVEL4,EQ_NONEEQ_NONE N/A N/ADQS_BIAS(DIFF_POD12ONLY)TRUE, FALSE FALSE TRUE, FALSE FALSE MIPI_DPHYThe MIPI D-PHY standard MIPI_DPHY is intended for use in mobile devices including cameras, displays, and unified protocol interfaces.Chapter 4: XP IOB ResourcesAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture ManualFigure 45: Differential Bidirectional DIFF_OUT Buffer PrimitivesIOBUFDS_DIFF_OUT I IOB IIOBUFDS_DIFF_OUT_DCIENIOBX21620-112818Table 84: IOBUFDSE3, IOBUFDS, IOBUFDS_COMP, IOBUFDS_DCIEN, IOBUFDS_DIFF_OUT,and IOBUF_DIFF_OUT_DCIEN AttributesAttributeValues Description IBUF_LOW_PWR TRUE, FALSE When set to TRUE, allows for reduced power on differential inputs for standards (for example: LVDS). A setting of FALSE demands more power but delivers higher performance characteristics.SLEW SLOW, FAST, MEDIUM Specifies the slew rate of the output.DRIVE 2, 4, 8, 12Specifies the drive strength of the output.IOSTANDARD See XP IOB Supported Standards Assigns an I/O standard to the element.DIFF_TERM TRUE, FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).DQS_BIAS TRUE, FALSE Provides pull-up/pull-down feature required for some DQS memory interface pins or provides DC bias for certain LVDS applications.USE_IBUFDISABLE TRUE, FALSEEnables use of the IBUFDISABLE. (IOBUFDSE3, IOBUFDS_COMP,IOBUFDS_DCIEN, IOBUFDS_DIFF_OUT_DCIEN only)Chapter 4: XP IOB ResourcesAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture Manual。

Chapter 2:Xilinx Silicon Solutionseither double data rate capability or the ability to distribute a slower clock (thereby savingpower). For single-edge clocking or latching, either clock polarity may be selected permacrocell.CoolRunner-II macrocell details are shown in Figure2-7. Standard logic symbols are usedin the in figure, except the trapezoidal multiplexers have input selection from staticallyprogrammed configuration select lines (not shown). Xilinx application note XAPP376gives a detailed explanation of how logic is created in the CoolRunner-II CPLD family.Figure 2-7:CoolRunner-II Macrocell ArchitectureWhen configured as a D-type flip-flop, each macrocell has an optional clock enable signalpermitting state hold while a clock runs freely. Note that control terms are available to beshared for key functions within the function block, and are generally used whenever theexact same logic function would be repeatedly created at multiple macrocells. The controlterm product terms are available for function block clocking (CTC), function blockasynchronous set (CTS), function block asynchronous reset (CTR), and function blockoutput enable (CTE).You can configure any macrocell flip-flop as an input register or latch, which takes in thesignal from the macrocell’s I/O pin and directly drives the AIM. The macrocellcombinatorial functionality is retained for use as a buried logic node if needed.Advanced Interconnect Matrix (AIM)AIM is a highly connected low-power rapid switch directed by the software to deliver a setof as many as 40 signals to each function block for the creation of logic. Results from allfunction block macrocells, as well as all pin inputs, circulate back through the AIM foradditional connection available to all other function blocks, as dictated by the designsoftware. The AIM minimizes both propagation delay and power as it makes attachmentsto the various function blocks.Programmable Logic DesignMay 8, 2008Programmable Logic Design May 8, 2008Chapter 2:Xilinx Silicon SolutionsThe CoolRunner-II family of CPLDs is targeted for low-power applications that include portable, handheld, and power-sensitive applications. Each member of the family includes RealDigital design technology that combines low power and high speed. With this design technique, the family offers true pin-to-pin speeds of 5.0 ns, while simultaneouslydelivering power that is less than 16 µA (standby) without the need for special "power down bits" that can negatively affect device performance. By replacing conventional amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. CoolRunner-II devices are the only total CMOS PLDsFigure 2-3:CPLD Application TrendsXilinx CoolRunner-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family and the extremely low power versatility of the XPLA3. This means that the exact same parts can be used for high-speed data communications,computing systems, and leading-edge portable products, with the added benefit of ISP . Low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. Xilinx-patented Fast Zero Power architecture inherently delivers extremely low power performance without the need for special design measures.Clocking techniques and other power-saving features extend your power budget. These design features are supported from Xilinx ISE 4.1i software onwards. Figure 2-4 shows some of the advanced CoolRunner-II CPLD package offering with dimensions. All •••High Performance, Low Power with CoolRunner TM XC9500XLXC9500•Consumer •Cell Phones •Cameras •Set-Top Boxes•DVD Players•Portable GPS•MP3 & Portable Radios•PDAs •Communication •Servers &PCs•Graphics Cards•Printers •Line Cards •Cable Modems•Industrial•Motor Controllers Glue Logic LSI SSI / MSI 19801990 2000Memory Controllers •Bus Interfaces •UAR/Ts High Speed Clocking •Delay Lock Loops •Digital Delay Lines Counters •State Machines •7400 Series ReplacementHigh Volume ApplicationsNo Cost PenaltySpecialty Functions -II。

XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007Product SpecificationAC Characteristics SymbolParameter XC9572XL-5XC9572XL-7XC9572XL-10Units Min Max Min Max Min Max T PDI/O to output valid - 5.0-7.5-10.0ns T SUI/O setup time before GCK 3.7- 4.8- 6.5-ns T HI/O hold time after GCK 0-0-0-ns T COGCK to output valid - 3.5- 4.5- 5.8ns f SYSTEMMultiple FB internal operating frequency -178.6-125.0-100.0MHzT PSUI/O setup time before p-term clock input 1.7- 1.6- 2.1-ns T PHI/O hold time after p-term clock input 2.0- 3.2- 4.4-ns T PCOP-term clock output valid - 5.5-7.7-10.2ns T OEGTS to output valid - 4.0- 5.0-7.0ns T ODGTS to output disable - 4.0- 5.0-7.0ns T POEProduct term OE to output enabled -7.0-9.5-11.0ns T PODProduct term OE to output disabled -7.0-9.5-11.0ns T AOGSR to output valid -10.0-12.0-14.5ns T PAOP-term S/R to output valid -10.5-12.6-15.3ns T WLHGCK pulse width (High or Low) 2.8- 4.0- 4.5-ns T APRPWAsynchronous preset/reset pulse width (High or Low) 5.0- 6.5-7.0-ns T PLH P-term clock pulse width (High or Low) 5.0- 6.5-7.0-nsFigure 3: AC Load CircuitXC9572XL High Performance CPLDDS057 (v2.0) April 3, 2007Product SpecificationInternal Timing Parameters SymbolParameter XC9572XL-5XC9572XL-7XC9572XL-10Units Min Max Min Max Min Max Buffer DelaysT INInput buffer delay - 1.5- 2.3- 3.5ns T GCKGCK buffer delay - 1.1- 1.5- 1.8ns T GSRGSR buffer delay - 2.0- 3.1- 4.5ns T GTSGTS buffer delay - 4.0- 5.0-7.0ns T OUTOutput buffer delay - 2.0- 2.5- 3.0ns T ENOutput buffer enable/disable delay -0-0-0ns Product Term Control Delays T PTCKProduct term clock delay - 1.6- 2.4- 2.7ns T PTSRProduct term set/reset delay - 1.0- 1.4- 1.8ns T PTTSProduct term 3-state delay - 5.5-7.2-7.5ns Internal Register and Combinatorial Delays T PDICombinatorial logic propagation delay -0.5- 1.3- 1.7ns T SUIRegister setup time 2.3- 2.6- 3.0-ns T HIRegister hold time 1.4- 2.2- 3.5-ns T ECSURegister clock enable setup time 2.4- 2.6- 3.0-ns T ECHORegister clock enable hold time 1.4- 2.2- 3.5-ns T COIRegister clock to output valid time -0.4-0.5- 1.0ns T AOIRegister async. S/R to output delay - 6.0- 6.4-7.0ns T RAIRegister async. S/R recover before clock 5.07.510.0ns T LOGIInternal logic delay - 1.0- 1.4- 1.8ns T LOGILPInternal low power logic delay - 5.0- 6.4-7.3ns Feedback Delays T FFast CONNECT II feedback delay - 1.9- 3.5- 4.2ns Time Adders T PTAIncremental product term allocator delay -0.7-0.8- 1.0ns T SLEW Slew-rate limited delay - 3.0- 4.0- 4.5ns。

Chapter 5: XP Bank Supporting Resources and Corner BanksBoundary Logic InterfaceIn addition to clocking resource, XPIO banks provide register stages for both signals going intoand coming out of the programmable logic space to and from XPIO. Because this resource exists between both types of XPIO logic resources (XPHY and XPIOL) and programmable logic regions, these logical blocks are called the boundary logic interface (BLI). In certain configurations, these BLI register stages can help optimize the timing of an interface. T o implement registers in the BLI region, an FDCE or FDRE primitive can be instantiated in a design leveraging the BLI attribute:set_property BLI TRUE|FALSE [get_cells register_name]BLI registers have a few restrictions that FDRE and FDCE typically do not have. BLI registerscannot be assigned an initial value and BLI registers do not have synchronous reset capabilities.When leveraging BLI registers, it can be helpful to leverage directives like EXTRACT_RESET ="no" in the Vivado Design Suite.Figure 56: BLI Capable Flip-Flops (FDCE and FDRE)Table 94: Single Data Rate Flip-Flop (FDCE and FDRE) PortsPort I/O DescriptionQ Output Data outputC Input Clock input pinCE Input Active-High clock enable registerD Input Data inputCLR Input Asynchronous clear (FDCE only)R Input R must be tied to ground for FDRE in BLI.Both single data rate and double data rate paths to and from the XP IOL can either use or bypass BLI registers. For the XPHY, several signals can leverage the BLI, see the below table for specific XPHY signals that can leverage BLI registers. For the table below, DIV_CLK =REFCLK_FREQUENCY / TX_DATA_WIDTH.AM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture ManualFigure 54: DQS_BIAS and DC_BIAS DiagramDC_BIASDQS_BIAS V BIASX22475-071320AC Coupling RecommendationsWhen receiving data from an AC coupled driver (like a clock source), care must be taken to ensure the appropriate bias levels are selected so that the receiver's input thresholdrequirements are met. If the receiver uses LVDS15 and resides in a 1.5V powered bank, aDC_BIAS value of DC_BIAS_1 along with DIFF_TERM_ADV setting of TERM_100 ensure that both a DC bias level and termination are provided inside the IOB for an AC coupled input. In scenarios where a 1.5V bank voltage is not used and AC coupling is required, it is recommended that both an external bias and external termination are used:•Do not use the optional internal differential termination.○DIFF_TERM_ADV = TERM_NONE ○DIFF_TERM = FALSE (default)•The differential signals at the input pins must meet the V IN requirements in the Recommended Operating Conditions table of the specific Versal ACAP data sheets .•The differential signals at the input pins must meet the V IDIFF (minimum) requirements in the corresponding LVDS15 specifications tables of the specific Versal ACAP data sheets .•The differential signals at the input pins must meet the V IDIFF (minimum) requirements in the corresponding LVDS15 specifications tables of the specific Versal ACAP data sheets .Chapter 4: XP IOB ResourcesAM010 (v1.2) April 2, 2021Versal ACAP SelectIO Resources Architecture Manual。

•Groups of gigabit serial transceiver (GT) power pins are separated by column for each column of GT Quads.•Standard HP I/O banks each have a total of 52 SelectIO™ pins, optionally configurable as (up to) 24 differential pairs.•Standard HD I/O banks each have a total of 24 SelectIO pins, optionally configurable as (up to) 12 differential pairs.•Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.•Four differential clock pin pairs per bank consist of a single type of global clock (GC or HDGC) input.•Four memory byte groups per HP I/O bank are each separated into an upper and a lower memory byte group.•Multiple PL configuration pins are removed.•A POR_OVERRIDE pin is used to override the default power-on-reset delay. See Table 1-4.Device/Package CombinationsTable 1-1 shows the size and BGA pitch of the Zynq UltraScale+ device packages. Allpackages are available with eutectic BGA balls. For these packages, the Pb-free signifier in the package name is a Q.Table 1‐1:Package SpecificationsPackagesDescriptionPackage SpecificationsPackage Type Pitch (mm)Size (mm)SBVA484Flip-chip, bare-dieBGA0.819x 19SFRA484Ruggedized flip-chip, bare-die 19x 19SFVA625Flip-chip 21x 21SFVC784Flip-chip23x 23SFRC784Ruggedized flip-chip FBVB900Flip-chip, bare-die 1.031x 31FFRB900Ruggedized flip-chip FFVC900Flip-chipFFRC900Ruggedized flip-chip找FPGA 和CPLD 可编程逻辑器件，上深圳宇航军工半导体有限公司Pin DefinitionsTable1-4 lists the pin definitions.Table 1‐4:Pin DefinitionsPin Name Type Direction Description User I/O PinsIO_L[1to24][P or N]_T[0to3] [U or L]_N[0to12]_ [multi-function]_[bank number] orIO_T[0to3][U or L]_N[0to12]_[multi-function]_[bank number]Dedicated Input/Output Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:•IO indicates a user I/O pin.•L[1to24] indicates a unique differential pair with P (positive) and N (negative) sides. User I/O pins without the L indicator are single-ended.•T[0 to 3][U or L] indicates the assigned byte group and nibble location (upper or lower portion) within that group for the pin.•N[0 to 12] the number of the I/O within its byte group.•[multi-function] indicates any other functions that the pin can provide. If not used for this function, the pin can be a user I/O.•[bank number] indicates the assigned bank for the user I/O pin.User I/O Multi-Function PinsGC or HDGC Multi-function Input Four global clock (GC or HDGC) pin pairs are in each bank. HDGC pins have direct access to the global clock buffers. GC pins have direct access to the global clock buffers and the MMCMs and PLLs that are in the clock management tile (CMT) adjacent to the same I/O bank. GC and HDGC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC and HDGC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative.Up-to-date information about designing with the GC (or HDGC) pin is available in the UltraScale Architecture Clocking Resources User Guide (UG572) [Ref7]VRP(1)Multi-function N/A This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).Table 1‐4:Pin Definitions (Cont’d)Footprint Compatibility between PackagesZynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices with the same number of package pins and the same preceding alphabetic designator. For example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the XCZU9EG-FFVC900. Pins that are available in one device but are not available in another device are labeled as No Connects in the other device's package file.compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packagessection of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref14].Table1-5 shows the footprint compatible devices available for each package. See theZynq UltraScale+ MPSoC Overview (DS891) [Ref1] for specific package letter code options.All packages are available with eutectic BGA balls. For these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.Table 1‐5:Footprint CompatibilityPackages Footprint Compatible DevicesSBVA484 SFRA484XCZU2CG, XCZU2EG,XAZU2EGXCZU3CG, XCZU3EG,XAZU3EG, XQZU3EGSFVA625XCZU2CG, XCZU2EG,XAZU2EG XCZU3CG, XCZU3EG, XAZU3EGSFVC784 SFRC784XCZU2CG, XCZU2EG,XAZU2EGXCZU3CG, XCZU3EG,XAZU3EG, XQZU3EGXCZU4CG, XCZU4EG,XCZU4EV, XAZU4EVXCZU5CG, XCZU5EG,XCZU5EV, XAZU5EV,XQZU5EVFBVB900 FFRB900XCZU4CG, XCZU4EG,XCZU4EVXCZU5CG, XCZU5EG,XCZU5EV, XQZU5EVXCZU7CG, XCZU7EG,XCZU7EV, XAZU7EV,XQZU7EVFFVC900 FFRC900XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG,XQZU9EGXCZU15EG, XQZU15EGFFVB1156 FFRB1156XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG,XQZU9EGXCZU15EG, XQZU15EGFFVC1156 FFRC1156XCZU7CG, XCZU7EG,XCZU7EV, XQZU7EVXCZU11EG, XQZU11EGFFVD1156XCZU21DR, XQZU21DRFFVE1156 FSVE1156XCZU25DR XCZU27DR, XCZU43DR,XCZU47DR, XCZU49DRXCZU28DR, XQZU28DRFFVB1517XCZU11EG XCZU17EG XCZU19EG, XQZU19EG。

DataGATE By lowering the average power, CoolRunner-II CPLDs can dramatically extend the battery lifeof a system in a way that brings the high flexibility and value of FPGAs into the portable world.Let’s show how more value is gained using CoolRunner-II DataGATE.DataGATE DataGATE was designed to stop unwanted input switching from continuously draining power in CoolRunner-II CPLDs. Additional applications evolved from testing to security, and aredocumented in the Advanced Features and DataGATE application notes. However, oneadditional application is simply to “DataGATE“ other chips.Figure4 shows how the DataGATE feature works. A metal rail (DataGATE Assertion Rail)circles the whole chip inside, near the pins. Each input site provides a place where the receivedsignal can be blocked by a pass transistor, depending on two conditions. The first condition isan enable bit, selecting that pin to participate in the DataGATE decision. The second conditionis simply whether the DataGATE Rail is asserted. If the rail is asserted and that input’sparticipation selected, the input signal is blocked from penetrating the chip, until the railreleases assertion. It’s that simple. When the rail asserts, blocking follows immediately. Theprevious input level automatically latches, so static CMOS logic signals forward into the CPLDcore. The signal freezes until released. When the rail releases, switching action resumes.Figure 4: DataGATE ArchitectureXAPP436 (v1.2) September 28, 2005XAPP799 (v1.1) August 2, 2005Using the CoolRunner-II SMBus/I2C Port Expander Designdictating the values on the GPIO output ports. On the 9th clock cycle, the CPLD acknowledges this second data byte, and sets the GPIO output pins accordingly.Figure 3:Write Command Transaction Performing a Read CommandIf a slave address with a read command has been sent, one final data byte is sent from the CPLD to the master. The data byte relays the values present on the ‘GPIO_INPUT_PINS’ bus.Figure 4 shows a full Read Command transaction. The master initiates a start command, then sends a read request to the CPLD located at slave address 0x56. The CPLD acknowledges the read request on the 9th clock edge. On the next data byte, the CPLD returns the value on the GPIO input pins. In this example, since there are only 2 GPIO input pins in the design, only the data on the 7th and 8th clock are valid. The first 6 data bits are high by default, and are ignored by the master. On the 9th clock cycle, the master acknowledges this second data byte, and the read transaction completes.Figure 4: Read Command TransactionStandbyThe CoolRunner-II family of CPLDs automatically enters "standby" when all pins are set to Vcc or GND. Standby current is specified in the individual device data sheets. This design fits into an XC2C32A device, which has a typical standby number of 22 uA -- ideal for SMBus and I 2C applications.。