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MEMORY存储芯片TMS320DM8147BCYE2中文规格书

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41TMS320C6745,TMS320C6747SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747DeviceOverviewCopyright©2008–2014,TexasInstrumentsIncorporated(1)I=Input,O=Output,I/O=Bidirectional,Z=Highimpedance,PWR=Supplyvoltage,GND=Ground,A=Analogsignal.Note:Thepintypeshownreferstotheinput,outputorhigh-impedancestateofthepinfunctionwhenconfiguredasthethesignalnamehighlightedinbold.Allmultiplexedsignalsmayenterahigh-impedancestatewhentheconfiguredfunctionisinput-onlyortheconfiguredfunctionsupportshigh-Zoperation.AllGPIOsignalscanbeusedasinputoroutput.Formultiplexedpinswherefunctionshavedifferenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral.(2)IPD=InternalPulldownresistor,IPU=InternalPullupresistor3.6.14UniversalHost-PortInterface(UHPI)Note:TheUHPImodulerequires16datapinsforthehostportinterfacetofunction.ThereforeonthePTP,theUHPIisnotavailable.Table3-19.UniversalHost-PortInterface(UHPI)TerminalFunctionsSIGNALNAMEPINNOTYPE(1)PULL(2)MUXEDDESCRIPTIONPTPZKBEMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]-M16I/OIPDEMIFA,LCD,GPIOUHPIdatabusEMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]-N14I/OIPDEMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]-N16I/OIPDEMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]-P14I/OIPDEMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]-P16I/OIPDEMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]-R14I/OIPDEMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]-T14I/OIPDEMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]-N12I/OIPDEMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]-M15I/OIPUEMIFA,MMC/SD,GPIO,BOOTEMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]-N13I/OIPUEMIFA,MMC/SD,GPIOEMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]-N15I/OIPUEMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]-P13I/OIPUEMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]-P15I/OIPUEMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]-R13I/OIPUEMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]-R15I/OIPUEMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]-T13I/OIPUEMIFA,MMC/SD,GPIO,BOOTEMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]-P9I/OIPUEMIFA,MMCSD_CMD,GPIOUHPIaccesscontrolEMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]-R9I/OIPUEMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]-P8I/OIPUEMIFA,LCD,GPIOUHPIhalf-wordidentificationcontrolEMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]-M13I/OIPUEMIFA,McASP,GPIO,BOOTUHPIread/writeEMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]-P7I/OIPUEMIFA,GPIO,BOOTUHPIchipselectEMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]-P12I/OIPUEMIFA,McASP0,GPIOUHPIdatastrobeEMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]-R7I/OIPUEMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]-M14I/OIPUUHPIhostinterruptEMA_WAIT[0]/UHPI_HRDY/GP2[10]-N6I/OIPUEMIFA,GPIOUHPIreadyEMA_CS[0]/UHPI_HAS/GP2[4]-T8I/OIPUUHPIaddressstrobe

51TMS320C6745,TMS320C6747SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747DeviceOverviewCopyright©2008–2014,TexasInstrumentsIncorporatedTable3-25.GeneralPurposeInputOutputTerminalFunctions(continued)SIGNALNAMEPINNOTYPE(1)PULL(2)MUXEDDESCRIPTIONPTPZKBGP4USB0_DRVVBUS/GP4[15]-E4OIPDUSB0GPIOBank4AMUTE1/EPWMTZ/GP4[14]132D4OIPDMcASP1,eHRPWM0,eHRPWM1,eHRPWM2AFSR1/GP4[13]166L3I/OIPDMcASP1ACLKR1/ECAP2/APWM2/GP4[12]165L2I/OIPDMcASP1,eCAP2AHCLKR1/GP4[11]-L1I/OIPDMcASP1AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]163K4I/OIPDMcASP1,eHRPWM0AXR1[9]/GP4[9]-M1I/OIPDMcASP1AXR1[8]/EPWM1A/GP4[8]168M2I/OIPDMcASP1,eHRPWM1AAXR1[7]/EPWM1B/GP4[7]169M3I/OIPDMcASP1,eHRPWM1BAXR1[6]/EPWM2A/GP4[6]170M4I/OIPDMcASP1,eHRPWM2AAXR1[5]/EPWM2B/GP4[5]171N1I/OIPDMcASP1,eHRPWM2BAXR1[4]/EQEP1B/GP4[4]173N2I/OIPDMcASP1,eQEPAXR1[3]/EQEP1A/GP4[3]174P1I/OIPDAXR1[2]/GP4[2]175P2I/OIPDMcASP1AXR1[1]/GP4[1]176R2I/OIPDAXR1[0]/GP4[0]1T3I/OIPDGP5EMB_WE_DQM[0]/GP5[15]60K14OIPUEMIFBGPIOBank5EMB_WE_DQM[1]/GP5[14]85C15OIPUSPI1_SCS[0]/UART2_TXD/GP5[13]8P4OIPUSPI1,UART2SPI1_ENA/UART2_RXD/GP5[12]7R4IIPUAXR1[11]/GP5[11]6T4I/OIPUMcASP1AXR1[10]/GP5[10]4N3I/OIPUUART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]2R3IIPUUART0,I2C0,BOOTUART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]3P3OIPUSPI1_CLK/EQEP1S/GP5[7]/BOOT[7]16T6IIPDSPI1,eQEP1,BOOTSPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]14N5I/OIPUSPI1,I2C1,BOOTSPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]13P5I/OIPUSPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]9N4IIPUSPI0,UART0,eQEP0,BOOTSPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]12R5IIPUSPI0_CLK/EQEP1I/GP5[2]/BOOT[2]11T5IIPDSPI0,eQEP1,BOOTSPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]18P6IIPDSPI0,eQEP0,BOOTSPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]17R6IIPD

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MEMORY存储芯片ADM3202ARUZ-REEL7中文规格书

MEMORY存储芯片ADM3202ARUZ-REEL7中文规格书

READ OperationREAD bursts are initiated with a READ command. The starting column and bank ad-dresses are provided with the READ command and auto precharge is either enabled ordisabled for that burst access. If auto precharge is enabled, the row being accessed isautomatically precharged at the completion of the burst. If auto precharge is disabled,the row will be left open after the completion of the burst.During READ bursts, the valid data-out element from the starting column address isavailable READ latency (RL) clocks later. RL is defined as the sum of posted CAS additivelatency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma-ble in the mode register via the MRS command. Each subsequent data-out element isvalid nominally at the next positive or negative clock edge (that is, at the next crossingof CK and CK#). Figure 69 shows an example of RL based on a CL setting of 8 and an ALsetting of 0.

MEMORY存储芯片TMS320C6701GJC120中文规格书

MEMORY存储芯片TMS320C6701GJC120中文规格书

TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS146N − FEBRUARY 2001 − REVISED MAY 2005

documentation support

Extensive documentation supports all TMS320™ DSP family generations of devices from product

announcement through applications development. The types of documentation available include: data sheets,

such as this document, with design specifications; complete user’s reference guides for all devices and tools;

technical briefs; development-support tools; on-line help; and hardware and software applications. The

following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes theC6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an

MEMORY存储芯片TMS320DM640AZNZ4中文规格书

MEMORY存储芯片TMS320DM640AZNZ4中文规格书

214TMS320C6745,TMS320C6747SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747DeviceandDocumentationSupportCopyright©2008–2014,TexasInstrumentsIncorporated7DeviceandDocumentationSupport7.1DeviceSupport7.1.1DevelopmentSupportTIoffersanextensivelineofdevelopmenttoolsfortheTMS320C6745/47platform,includingtoolstoevaluatetheperformanceoftheprocessors,generatecode,developalgorithmimplementations,andfullyintegrateanddebugsoftwareandhardwaremodules.Thetool'ssupportdocumentationiselectronicallyavailablewithintheCodeComposerStudio™IntegratedDevelopmentEnvironment(IDE).ThefollowingproductssupportdevelopmentofTMS320C6745/47applications:SoftwareDevelopmentTools:CodeComposerStudio™IntegratedDevelopmentEnvironment(IDE):includingEditorC/C++/AssemblyCodeGeneration,andDebugplusadditionaldevelopmenttoolsScalable,Real-TimeFoundationSoftware(DSP/BIOS™),whichprovidesthebasicrun-timetargetsoftwareneededtosupportanyapplication.HardwareDevelopmentTools:ExtendedDevelopmentSystem(XDS™)EmulatorForacompletelistingofdevelopment-supporttoolsforTMS320C6745/47,uniformresourcelocator(URL).Forinformationonpricingandavailability,contactthenearestTIfieldsalesofficeorauthorizeddistributor.7.1.2DeviceandDevelopment-SupportToolNomenclatureTodesignatethestagesintheproductdevelopmentcycle,TIassignsprefixestothepartnumbersofallDSPdevicesandsupporttools.EachDSPcommercialfamilymemberhasoneofthreeprefixes:TMX,TMP,orTMS(e.g.,TMS320C6745).TexasInstrumentsrecommendstwoofthreepossibleprefixdesignatorsforitssupporttools:TMDXandTMDS.Theseprefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes(TMX/TMDX)throughfullyqualifiedproductiondevices/tools(TMS/TMDS).Devicedevelopmentevolutionaryflow:TMXExperimentaldevicethatisnotnecessarilyrepresentativeofthefinaldevice'selectricalspecifications.TMPFinalsilicondiethatconformstothedevice'selectricalspecificationsbuthasnotcompletedqualityandreliabilityverification.TMSFully-qualifiedproductiondevice.Supporttooldevelopmentevolutionaryflow:TMDXDevelopment-supportproductthathasnotyetcompletedTexasInstrumentsinternalqualificationtesting.TMDSFullyqualifieddevelopment-supportproduct.TMXandTMPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer:"Developmentalproductisintendedforinternalevaluationpurposes."TMSdevicesandTMDSdevelopment-supporttoolshavebeencharacterizedfully,andthequalityandreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies.

MEMORY存储芯片TMS320F28032PNT中文规格书

MEMORY存储芯片TMS320F28032PNT中文规格书

2

1

GP[]󰀀as󰀀inputn

mGP[]󰀀as󰀀inputnm

432

1

GP[]󰀀as󰀀outputn

m

81TMS320C6745,TMS320C6747

SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

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ProductFolderLinks:TMS320C6745TMS320C6747PeripheralInformationandElectricalSpecificationsCopyright©2008–2014,TexasInstrumentsIncorporated6.8.2GPIOPeripheralInput/OutputElectricalData/Timing

(1)ThepulsewidthgivenissufficienttogenerateaCPUinterruptoranEDMAevent.However,ifauserwantstohaveC6745/6747

recognizetheGPIxchangesthroughsoftwarepollingoftheGPIOregister,theGPIxdurationmustbeextendedtoallowC6745/6747

enoughtimetoaccesstheGPIOregisterthroughtheinternalbus.

(2)C=SYSCLK4periodinns.Table6-9.TimingRequirementsforGPIOInputs(1)(seeFigure6-10)

No.PARAMETERMINMAXUNIT

1tw(GPIH)Pulseduration,GPn[m]asinputhigh2C(1)(2)ns

2tw(GPIL)Pulseduration,GPn[m]asinputlow2C(1)(2)ns

(1)Thisparametervalueshouldnotbeusedasamaximumperformancespecification.Actualperformanceofback-to-backaccessesofthe