MEMORY存储芯片TMS27C010中文规格书

UHPI_HCSUHPI_HAS(D)UHPI_HCNTL[1:0]UHPI_HR/WUHPI_HHWILUHPI_HSTROBEUHPI_HD[15:0](output)UHPI_HRDY121212563431212128141514871st Half-Word2nd Half-Word61315(A)(C)(B)

196TMS320C6745,TMS320C6747SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747PeripheralInformationandElectricalSpecificationsCopyright©2008–2014,TexasInstrumentsIncorporatedA.UHPI_HSTROBEreferstothefollowinglogicaloperationonUHPI_HCS,UHPI_HDS1,andUHPI_HDS2:[NOT(UHPI_HDS1XORUHPI_HDS2)]ORUHPI_HCS.B.Dependingonthetypeofwriteorreadoperation(HPIDwithoutauto-incrementing;HPIA,HPIC,orHPIDwithauto-incrementing)andthestateoftheFIFO,transitionsonUHPI_HRDYmayormaynotoccur.C.UHPI_HCSreflectstypicalUHPI_HCSbehaviorwhenUHPI_HSTROBEassertioniscausedbyUHPI_HDS1orUHPI_HDS2.UHPI_HCStimingrequirementsarereflectedbyparametersforUHPI_HSTROBE.D.ThediagramaboveassumesUHPI_HAShasbeenpulledhigh.Figure6-67.UHPIReadTiming(UHPI_HASNotUsed,TiedHigh)

11TMS320C6745,TMS320C6747SPRS377F–SEPTEMBER2008–REVISEDJUNE2014

SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747DeviceOverviewCopyright©2008–2014,TexasInstrumentsIncorporated3.3.1C674xDSPCPUDescriptionTheC674xCentralProcessingUnit(CPU)consistsofeightfunctionalunits,tworegisterfiles,andtwodatapathsasshowninFigure3-2.Thetwogeneral-purposeregisterfiles(AandB)eachcontain3232-bitregistersforatotalof64registers.Thegeneral-purposeregisterscanbeusedfordataorcanbedataaddresspointers.Thedatatypessupportedincludepacked8-bitdata,packed16-bitdata,32-bitdata,40-bitdata,and64-bitdata.Valueslargerthan32bits,suchas40-bit-longor64-bit-longvaluesarestoredinregisterpairs,withthe32LSBsofdataplacedinanevenregisterandtheremaining8or32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister).Theeightfunctionalunits(.M1,.L1,.D1,.S1,.M2,.L2,.D2,and.S2)areeachcapableofexecutingoneinstructioneveryclockcycle.The.Mfunctionalunitsperformallmultiplyoperations.The.Sand.Lunitsperformageneralsetofarithmetic,logical,andbranchfunctions.The.Dunitsprimarilyloaddatafrommemorytotheregisterfileandstoreresultsfromtheregisterfileintomemory.TheC674xCPUcombinestheperformanceoftheC64x+corewiththefloating-pointcapabilitiesoftheC67x+core.EachC674x.Munitcanperformoneofthefollowingeachclockcycle:one32x32bitmultiply,one16x32bitmultiply,two16x16bitmultiplies,two16x32bitmultiplies,two16x16bitmultiplieswithadd/subtractcapabilities,four8x8bitmultiplies,four8x8bitmultiplieswithaddoperations,andfour16x16multiplieswithadd/subtractcapabilities(includingacomplexmultiply).ThereisalsosupportforGaloisfieldmultiplicationfor8-bitand32-bitdata.ManycommunicationsalgorithmssuchasFFTsandmodemsrequirecomplexmultiplication.Thecomplexmultiply(CMPY)instructiontakesfour16-bitinputsandproducesa32-bitrealanda32-bitimaginaryoutput.Therearealsocomplexmultiplieswithroundingcapabilitythatproducesone32-bitpackedoutputthatcontain16-bitrealand16-bitimaginaryvalues.The32x32bitmultiplyinstructionsprovidetheextendedprecisionnecessaryforhigh-precisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes.The.LUnit(orArithmeticLogicUnit)nowincorporatestheabilitytodoparalleladd/subtractoperationsonapairofcommoninputs.Versionsofthisinstructionexisttoworkon32-bitdataoronpairsof16-bitdataperformingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions.TheC674xcoreenhancesthe.Sunitinseveralways.Onthepreviouscores,dual16-bitMIN2andMAX2comparisonswereonlyavailableonthe.Lunits.OntheC674xcoretheyarealsoavailableonthe.Sunitwhichincreasestheperformanceofalgorithmsthatdosearchingandsorting.Finally,toincreasedatapackingandunpackingthroughput,the.Sunitallowssustainedhighperformanceforthequad8-bit/16-bitanddual16-bitinstructions.Unpackinstructionsprepare8-bitdataforparallel16-bitoperations.Packinstructionsreturnparallelresultstooutputprecisionincludingsaturationsupport.Othernewfeaturesinclude:•SPLOOP-AsmallinstructionbufferintheCPUthataidsincreationofsoftwarepipeliningloopswheremultipleiterationsofaloopareexecutedinparallel.TheSPLOOPbufferreducesthecodesizeassociatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible.•CompactInstructions-ThenativeinstructionsizefortheC6000™devicesis32bits.ManycommoninstructionssuchasMPY,AND,OR,ADD,andSUBcanbeexpressedas16bitsiftheC674xcompilercanrestrictthecodetousecertainregistersintheregisterfile.Thiscompressionisperformedbythecodegenerationtools.•InstructionSetEnhancement-Asnotedabove,therearenewinstructionssuchas32-bitmultiplications,complexmultiplications,packing,sorting,bitmanipulation,and32-bitGaloisfieldmultiplication.•ExceptionsHandling-Intendedtoaidtheprogrammerinisolatingbugs.TheC674xCPUisabletodetectandrespondtoexceptions,bothfrominternallydetectedsources(suchasillegalop-codes)andfromsystemevents(suchasawatchdogtimeexpiration).•Privilege-Definesuserandsupervisormodesofoperation,allowingtheoperatingsystemtogiveabasiclevelofprotectiontosensitiveresources.Localmemoryisdividedintomultiplepages,eachwithread,write,andexecutepermissions.

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SubmitDocumentationFeedbackProductFolderLinks:TMS320C6745TMS320C6747PeripheralInformationandElectricalSpecificationsCopyright©2008–2014,TexasInstrumentsIncorporated(1)TheseparametersareinadditiontothegeneraltimingsforSPIslavemodes(Table6-55).(2)P=SYSCLK2period(3)FigureshowsonlyPolarity=0,Phase=0asanexample.Tablegivesparametersforallfourslaveclockingmodes.(4)SPI0_ENAisdrivenlowafterthetransmissioncompletesiftheSPIINT0.ENABLE_HIGHZbitisprogrammedto0.Otherwiseitis3-stated.If3-stated,anexternalpullupresistorshouldbeusedtoprovideavalidleveltothemaster.ThisoptionisusefulwhentyingseveralSPIslavedevicestoasinglemaster.Table6-61.Additional(1)SPI0SlaveTimings,5-PinOption(2)(3)No.PARAMATERMINMAXUNIT25td(SCSL_SPC)SRequireddelayfromSPI0_SCSassertedatslavetofirstSPI0_CLKedgeatslave.2Pns26td(SPC_SCSH)SRequireddelayfromfinalSPI0_CLKedgebeforeSPI0_SCSisdeasserted.Polarity=0,Phase=0,fromSPI0_CLKfalling0.5tc(SPC)M+P+5nsPolarity=0,Phase=1,fromSPI0_CLKfallingP+5Polarity=1,Phase=0,fromSPI0_CLKrising0.5tc(SPC)M+P+5Polarity=1,Phase=1,fromSPI0_CLKrisingP+527tena(SCSL_SOMI)SDelayfrommasterassertingSPI0_SCStoslavedrivingSPI0_SOMIvalidP+18.5ns28tdis(SCSH_SOMI)SDelayfrommasterdeassertingSPI0_SCStoslave3-statingSPI0_SOMIP+18.5ns29tena(SCSL_ENA)SDelayfrommasterdeassertingSPI0_SCStoslavedrivingSPI0_ENAvalid18.5ns30tdis(SPC_ENA)SDelayfromfinalclockreceiveedgeonSPI0_CLKtoslave3-statingordrivinghighSPI0_ENA.(4)Polarity=0,Phase=0,fromSPI0_CLKfalling2.5P+18.5nsPolarity=0,Phase=1,fromSPI0_CLKrising2.5P+18.5Polarity=1,Phase=0,fromSPI0_CLKrising2.5P+18.5Polarity=1,Phase=1,fromSPI0_CLKfalling2.5P+18.5

DDR3L SDRAM

MT41K1G4 – 128 Meg x 4 x 8 banks

MT41K512M8 – 64 Meg x 8 x 8 banksMT41K256M16 – 32 Meg x 16 x 8 banks

Description

DDR3L SDRAM (1.35V) is a low voltage version of theDDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM(Die Rev :E) data sheet specifications when running in1.5V compatible mode.

Features

•VDD = VDDQ = 1.35V (1.283–1.45V)•Backward compatible to VDD = VDDQ = 1.5V ±0.075V–Supports DDR3L devices to be backward com-patible in 1.5V applications•Differential bidirectional data strobe•8n-bit prefetch architecture•Differential clock inputs (CK, CK#)•8 internal banks•Nominal and dynamic on-die termination (ODT)for data, strobe, and mask signals•Programmable CAS (READ) latency (CL)•Programmable posted CAS additive latency (AL)•Programmable CAS (WRITE) latency (CWL)•Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])•Selectable BC4 or BL8 on-the-fly (OTF)•Self refresh mode•TC of 105°C–64ms, 8192-cycle refresh up to 85°C–32ms, 8192-cycle refresh at >85°C to 95°C–16ms, 8192-cycle refresh at >95°C to 105°C•Self refresh temperature (SRT)•Automatic self refresh (ASR)•Write leveling•Multipurpose register•Output driver calibration