MEMORY存储芯片TMS320C6455DZTZA中文规格书
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TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005peripheral register descriptions (continued)Table 17. HPI RegistersHEX ADDRESS RANGEACRONYMREGISTER NAMECOMMENTS−HPIDHPI data registerHost read/write access only0188 0000HPICHPI control registerHPIC has both Host/CPUread/write access0188 0004HPIA(HPIAW)†HPI address register (Write)HPIA has both Host/CPU0188 0008HPIA(HPIAR)†HPI address register (Read)read/write access0188 000C − 0189 FFFF−Reserved018A 0000TRCTLHPI transfer request control register018A 0004 − 018B FFFF−Reserved†Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.Table 18. GPIO RegistersHEX ADDRESS RANGEACRONYMREGISTER NAME01B0 0000GPENGPIO enable register01B0 0004GPDIRGPIO direction register01B0 0008GPVALGPIO value register01B0 000C−Reserved01B0 0010GPDHGPIO delta high register01B0 0014GPHMGPIO high mask register01B0 0018GPDLGPIO delta low register01B0 001CGPLMGPIO low mask register01B0 0020GPGCGPIO global control register01B0 0024GPPOLGPIO interrupt polarity register01B0 0028 − 01B0 01FF−Reserved01B0 0200DEVICE_REVSilicon Revision Identification Register(For more details, see the device characteristics listed in Table 1.)01B0 0204 − 01B3 FFFF−ReservedTMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORSSPRS146N − FEBRUARY 2001 − REVISED MAY 2005signal groups description TRSTGP7/EXT_INT7‡
IEEE Standard1149.1(JTAG)EmulationReservedReset andInterrupts
Control/StatusTDITDOTMSTCKEMU0EMU1NMIGP6/EXT_INT6‡GP5/EXT_INT5‡GP4/EXT_INT4‡RESET
RSVRSVRSVRSVClock/PLLCLKINCLKMODE1CLKMODE0PLLV
EMU2EMU3EMU4EMU5RSV
GPIOGeneral-Purpose Input/Output (GPIO) PortGP7/EXT_INT7‡GP6/EXT_INT6‡GP5/EXT_INT5‡GP4/EXT_INT4‡GP3CLKOUT6/GP2†CLKOUT4/GP1†GP0CLKOUT6/GP2†CLKOUT4/GP1†
EMU6EMU7EMU8EMU9EMU10
GP15/PRST§GP14/PCLK§GP13/PINTA§GP12/PGNT§GP11/PREQ§GP10/PCBE3§GP9/PIDSEL§CLKS2/GP8†These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2clock source (CLKS2). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must beproperly enabled and configured. For more details, see the Device Configurations section of this data sheet.†These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx orGPIO as input-only.‡RSV
EMU11RSVRSVRSV•••
PeripheralControl/StatusPCI_ENMCBSP2_EN
For the C6415 and C6416 devices, these GPIO pins are muxed with the PCI peripheral pins. By default, these signals are set up tono function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurationssection of this data sheet. For the C6414 device, the GPIO peripheral pins are not muxed; the C6414 device does not support thePCI peripheral.§Figure 3. CPU and Peripheral Signals
