AWT6138中文资料

03/2006AWT6136450 MHz CDMA 3.4V/29.5dBmLinear Power Amplifier ModulePRELIMINARY DATA SHEET - Rev 1.6FEATURES•InGaP HBT Technology •High Efficiency 37% CDMA•Low Receive Band Noise (NR X ) -132 dBm/Hz @10 MHz offset•Low Leakage Current (<5 µA)•SMT Module Package•Small Foot Print (6 mm x 6 mm)•50 Ω Input and Output Matching•Low Quiescent Current (Icq = 60 mA Typ)•Shut Down and Mode Control •CDMA 2000 1XRTT Compliant•RoHS Compliant Package Option, 250 o C MSL-3APPLICATIONS•450 MHz Single Mode CDMA Wireless Handsets and Wireless Local LoopPRODUCT DESCRIPTIONThe AWT6136 is a high power, high efficiency amplifier module for CDMA wireless handset applications. The device is manufactured on an advanced InGaP HBT MMIC technology offering state-of-the-art reliability, temperature stability and ruggedness. A low power quiescent current modeis digitally controlled to reduce power drain on the system battery. The 6 mm x 6 mm x 1.5 mm laminate package is self contained, incorporating 50 Ω input and output matching networks optimized for output power, linearity, and efficiency.Figure 1: Block DiagramV CC V REFRF IN V CCGNDMODERF OUT2PRELIMINARY DATA SHEET - Rev 1.603/2006AWT6136RF OUTV REFRF INV MODEV CCGNDV CCFigure 2: Pinout (X-ray Top View)Table 1: Pin DescriptionPRELIMINARY DATA SHEET - Rev 1.603/2006 AWT61363ELECTRICAL CHARACTERISTICSTable 2: Absolute Minimum and Maximum RatingsStresses in excess of the absolute ratings may cause permanentdamage. Functional operation is not implied under these conditions.Exposure to absolute ratings for extended periods of time mayadversely affect reliability.guaranteed only over the conditions defined in the electrical specifications.Notes:(1) For operation at V CC = +3.2 V and T C = +90 O C, P OUT is derated by 0.5 dB.AWT6136Table 4: Electrical Specifications – CDMA Operation(T C = +25 O C, V CC = +3.4 V, V REF = +2.90 V, 50 Ω system)Notes:(1) P OUT is derated by 0.5 dB for IS-98 / CDMA 2000 operation.(2) Efficiency spec applies at 455 MHz.4PRELIMINARY DATA SHEET - Rev 1.603/2006PRELIMINARY DATA SHEET - Rev 1.603/2006AWT61365APPLICATION INFORMATIONTo ensure proper performance, refer to all related Application Notes on the ANADIGICS web site:Shutdown ModeThe power amplifier may be placed in a shutdown mode by applying logic low levels (see Operating Ranges table) to both the V REF and V MODE voltages.Figure 3: Application Circuit SchematicGND at slug (pad)High Bias ModeThe power amplifier may be placed in a high bias mode by applying a logic low level (see Operating Ranges table) to the V MODE voltage.AWT6136Figure 4: M5 Package Outline - 7 Pin 6 mm x 6 mm x 1.5 mm Surface Mount Module (Low Band )61366136INK MARKEDFigure 5: Branding Specification6PRELIMINARY DATA SHEET - Rev 1.603/2006PRELIMINARY DATA SHEET - Rev 1.603/2006 AWT613676136R6136RINK MARKEDFigure 6: RoHS Compliant Branding SpecificationAWT6136COMPONENT PACKAGINGFigure 6: Tape & Reel Packaging8PRELIMINARY DATA SHEET - Rev 1.603/2006PRELIMINARY DATA SHEET - Rev 1.603/2006 AWT61369NOTESAWT6136NOTES10PRELIMINARY DATA SHEET - Rev 1.603/2006AWT6136 NOTESAWT6136ORDERING INFORMATIONANADIGICS, Inc.141 Mount Bethel RoadWarren, New Jersey 07059, U.S.A.Tel: +1 (908) 668-5000Fax: +1 (908) 668-5132URL: E-mail: Mktg@IMPORTANT NOTICEANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders.WARNINGANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.。

元器件交易网ASAHI KASEI[AK4628A]AK4628AHigh Performance Multi-channel Audio CODECGENERAL DESCRIPTION The AK4628A is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4628A has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112B. The AK4628A is available in a small 44pin LQFP package which will reduce system space.*AC-3 is a trademark of Dolby Laboratories.FEATURES 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 92dB - Dynamic Range, S/N: 102dB - Digital HPF for offset cancellation - I/F format: MSB justified, I2S or TDM - Overflow flag 8ch 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM - Individual channel digital volume with 128 levels and 0.5dB step - Soft mute - De-emphasis for 32kHz, 44.1kHz and 48kHz - Zero Detect Function High Jitter Tolerance TTL Level Digital I/F 3-wire Serial and I2C Bus µP I/F for mode setting Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=64kHz to 96kHz 128fs for fs=120kHz to 192kHz Power Supply: 4.5 to 5.5V Power Supply for output buffer: 2.7 to 5.5V Small 44pin LQFP AK4529 Pin CompatibleMS0385-E-00 -1-2005/02元器件交易网ASAHI KASEI[AK4628A]Block DiagramLINADC ADCHPF HPFAudio I/FRINRX1 RX2 RX3 RX4 XTILOUT1LPFDACDATTMCLK LRCK BICKMCLK LRCK BICK DAUXXTO MCKO LRCK BICK SDTODIR AK4112BROUT1LPFDACDATTLOUT2LPFDACDATTFormat ConverterROUT2LPFDACDATTSDOUT SDOS SDTO LRCK BICK SDIN SDOUT1 SDOUT2 SDOUT3 SDOUT4AC3LOUT3LPFDACDATTSDIN1 SDIN2 SDIN3 SDIN4ROUT3LPFDACDATTSDTI1 SDTI2 SDTI3 SDTI4LOUT4LPFDACDATTROUT4LPFDACDATTAK4628ABlock Diagram (DIR and AC-3 DSP are external parts)MS0385-E-00 -2-2005/02元器件交易网ASAHI KASEI[AK4628A]Ordering GuideAK4628AVQ AKD4628 -40 ∼ +85°C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4628APin LayoutLOOP0/SDA/CDTIDIF1/SCL/CCLKDIF0/CSNVREFH 35MCLK444143424037AVSSAVDDDZF1P/S3938SDOS I2C SMUTE BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS01 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Top View3634 33 32 31VCOMTDM0DZF2/OVF RIN LIN NC TST2 ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3AK4628AVQ30 29 28 27 26 25 24 23MS0385-E-00 -3-ROUT4LOUT4SDTI4DVDDDVSSTVDDCAD1CAD0DZFETST1PDN2005/02元器件交易网ASAHI KASEI[AK4628A]Compatibility with AK45291. Functions Functions DAC Sampling frequency TDM128 (96kHz) Digital Attenuator Soft Mute DAC channel power-downAK4529 Up to 96kHz Not available 256 levels Soft mute function is independent of Digital attenuator. Not availableAK4628A Up to 192kHz Available 128 levels Soft mute function is not independent of Digital attenuator. Available2. Pin Configuration pin# 11 18 29 44AK4529 DFS TST NC TDMAK4628A DFS0 TST1 TST2 TDM03. Register Addr 00H 00H 01H 01H 01H 09HAK4529 TDM Not available DFS Not available Not available Not availableAK4628A TDM0 TDM1 DFS0 DFS1 CKS1, CKS0 PD4, PD3, PD2, PD1MS0385-E-00 -4-2005/02元器件交易网ASAHI KASEI[AK4628A]PIN/FUNCTIONNo. 1 Pin Name SDOS I/O I Function SDTO Source Select Pin (Note 1) “L”: Internal ADC output, “H”: DAUX input SDOS pin should be set to “L” when TDM= “1”. Control Mode Select Pin “L”: 3-wire Serial, “H”: I2C Bus Soft Mute Pin (Note 1) When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. Audio Serial Data Clock Pin Input Channel Clock Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Serial Data Output Pin AUX Audio Serial Data Input Pin Double Speed Sampling Mode Pin (Note 1) “L”: Normal Speed, “H”: Double Speed DAC4 Audio Serial Data Input Pin Zero Input Detect Enable Pin “L”: mode 7 (disable) at parallel mode, zero detect mode is selectable by DZFM3-0 bits at serial mode “H”: mode 0 (DZF1 is AND of all eight channels) Output Buffer Power Supply Pin, 2.7V∼5.5V Digital Power Supply Pin, 4.5V∼5.5V Digital Ground Pin, 0V Power-Down & Reset Pin When “L”, the AK4628A is powered-down and the control registers are reset to default state. If the state of P/S or CAD1-0 changes, then the AK4628A must be reset by PDN. Test Pin This pin should be connected to DVSS. Chip Address 1 Pin Chip Address 0 Pin DAC4 Lch Analog Output Pin DAC4 Rch Analog Output Pin2 3I2C SMUTEI I4 5 6 7 8 9 10 11 12 13BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS0 SDTI4 DZFEI I I I I O I I I I14 15 16 17TVDD DVDD DVSS PDNI18 19 20 21 22TST1 CAD1 CAD0 LOUT4 ROUT4I I I O OMS0385-E-00 -5-2005/02元器件交易网ASAHI KASEI[AK4628A]No. 23 24 25 26 27 28 29 30 31 32 33Pin Name LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 TST2 NC LIN RIN DZF2I/O O O O O O O I I I OFunction DAC3 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC1 Lch Analog Output Pin DAC1 Rch Analog Output Pin Test pin (Internal pull-down pin) This pin should be left floating or connected to AVSS. No Connect No internal bonding. Lch Analog Input Pin Rch Analog Input Pin Zero Input Detect 2 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. It always is in “L” when P/S is “H”. Analog Input Overflow Detect Pin (Note 3) This pin goes to “H” if the analog input of Lch or Rch overflows. Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2µF is used to reduce power-supply noise. Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin, 4.5V∼5.5V Analog Ground Pin, 0V Zero Input Detect 1 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to “H”. Output is selected by setting DZFE pin when P/S is “H”. Master Clock Input Pin Parallel/Serial Select Pin “L”: Serial control mode, “H”: Parallel control mode Audio Data Interface Format 0 Pin in parallel control mode Chip Select Pin in 3-wire serial control mode This pin should be connected to DVDD at I2C bus control mode Audio Data Interface Format 1 Pin in parallel control mode Control Data Clock Pin in serial control mode I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus) Loopback Mode 0 Pin in parallel control mode Enables digital loop-back from ADC to 4 DACs. Control Data Input Pin in serial control mode I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus) TDM I/F Format Mode Pin (Note 1) “L”: Normal mode, “H”: TDM modeOVF 34 35 36 37 38 VCOM VREFH AVDD AVSS DZF1O O I O39 40 41MCLK P/S DIF0 CSN DIF1 SCL/CCLK LOOP0 SDA/CDTII I I I I I I I/O I424344TDM0Notes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”. 2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All digital input pins except for pull-down should not be left floating.MS0385-E-00 -6-2005/02元器件交易网ASAHI KASEI[AK4628A]ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 5) Parameter Symbol min AVDD -0.3 Power Supplies Analog DVDD -0.3 Digital TVDD -0.3 Output buffer |AVSS-DVSS| (Note 6) ∆GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage (Expect LRCK, BICK pins) VIND1 -0.3 (LRCK, BICK pins) VIND2 -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65Notes: 5. All voltages with respect to ground. 6. AVSS and DVSS must be connected to the same analog ground plane.max 6.0 6.0 6.0 0.3 ±10 AVDD+0.3 DVDD+0.3 TVDD+0.3 85 150Units V V V V mA V V V °C °CWARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 5) Parameter Symbol min typ Power Supplies Analog AVDD 4.5 5.0 (Note 7) Digital DVDD 4.5 5.0 Output buffer TVDD 2.7 5.0max 5.5 5.5 5.5Units V V VNotes: 5. All voltages with respect to ground. 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4628A under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.MS0385-E-00 -7-2005/02元器件交易网ASAHI KASEI[AK4628A]ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 84 92 dB fs=96kHz 86 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB dB 102 94 S/N (Note 8) fs=48kHz, A-weighted dB 96 88 fs=96kHz dB 102 93 fs=96kHz, A-weighted Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/°CInput Voltage AIN=0.62xVREFH 2.90 3.10 3.30 VppInput Resistance (Note 9) Power Supply Rejection (Note 10) DAC Analog Output Characteristics Resolution S/(N+D) fs=48kHz fs=96kHz fs=192kHz DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weightedfs=192kHz fs=192kHz, A-weighted1525 50 24kΩ dB Bits dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/°C Vpp kΩ dBS/N(Note 11)fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weightedfs=192kHz fs=192kHz, A-weightedInterchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Output Voltage AOUT=0.6xVREFH Load Resistance Power Supply Rejection Notes:80 78 95 88 94 95 88 94 9090 88 88 106 100 106 100 106 106 100 106 100 106 110 0.2 20 3.0 50 0.5 3.252.75 5 (Note 10)8. S/N measured by CCIR-ARM is 98dB(@fs=48kHz). 9. Input resistance is 16kΩ typically at fs=96kHz. 10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).MS0385-E-00 -8-2005/02元器件交易网ASAHI KASEI[AK4628A]Parameter Power Supplies Power Supply Current (AVDD+DVDD+TVDD) Normal Operation (PDN = “H”) AVDD fs=48kHz, 96kHz fs=192kHz DVDD+TVDD fs=48kHz fs=96kHz fs=192kHz Power-down mode (PDN = “L”)mintypmaxUnits(Note 12)(Note 13)45 34 18 24 27 8067 51 27 36 40 200mA mA mA mA mA µANotes: 12. TVDD=0.1mA(typ). 13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.MS0385-E-00 -9-2005/02元器件交易网ASAHI KASEI[AK4628A]FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): PB 0 Passband (Note 14) ±0.1dB -0.2dB -3.0dB Stopband SB 28 Passband Ripple PR Stopband Attenuation SA 68 Group Delay (Note 15) GD Group Delay Distortion ∆GD ADC Digital Filter (HPF): Frequency Response (Note 14) -3dB FR -0.1dB DAC Digital Filter: Passband (Note 14) -0.1dB PB 0 -6.0dB Stopband SB 26.2 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 15) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 ∼ 20.0kHz FR 40.0kHz (Note 16) FR 80.0kHz (Note 16)typmax 18.9 ±0.04Units kHz kHz kHz kHz dB dB 1/fs µs Hz Hz20.0 23.016 0 1.0 6.5 21.8 ±0.02 19.2 ±0.2 ±0.3 ±1.024.0kHz kHz kHz dB dB 1/fs dB dB dBNotes: 14. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs. 15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz.DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage TVDD-0.5 VOH (SDTO, LRCK, BICK pins: Iout=-100µA) AVDD-0.5 VOH (DZF1, DZF2/OVF pins: Iout=-100µA) Low-Level Output Voltage VOL (SDTO, LRCK, BICK,DZF1, DZF2/OVF pins: Iout= 100µA) VOL (SDA pins: Iout= 3mA) Input Leakage Current (Note 17) Iin Note 17: TST2 pin has an internal pull-down device, nominally 100kohm.typ -max 0.8 0.5 0.4 ±10Units V V V V V V µAMS0385-E-00 - 10 -2005/02SWITCHING CHARACTERISTICS(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; C L=20pF)Parameter SymbolmintypmaxUnits Master Clock Timing256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd: Pulse Width Low Pulse Width High fCLKtCLKLtCLKHfCLKtCLKLtCLKHfCLKtCLKLtCLKH8.192272712.288202016.384151512.28818.43224.576MHznsnsMHznsnsMHznsnsLRCK TimingNormal mode (TDM0= “0”, TDM1= “0”)Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsnfsdfsqDuty326412045489619255kHzkHzkHz%TDM256 mode (TDM0= “1”, TDM1= “0”)LRCK frequency “H” time“L” time fsntLRHtLRL321/256fs1/256fs48 kHznsnsTDM128 mode (TDM0= “1”, TDM1= “1”)LRCK frequency “H” time“L” time fsntLRHtLRL641/128fs1/128fs96 kHznsnsAudio Interface TimingNormal mode (TDM0= “0”, TDM1= “0”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) LRCK to SDTO(MSB)BICK “↓” to SDTOSDTI1-4,DAUX Hold TimeSDTI1-4,DAUX Setup Time tBCKtBCKLtBCKHtLRBtBLRtLRStBSDtSDHtSDS813232202020204040nsnsnsnsnsnsnsnsnsnsTDM256 mode (TDM0= “1”, TDM1= “0”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTOSDTI1 Hold TimeSDTI1 Setup Time tBCKtBCKLtBCKHtLRBtBLRtBSDtSDHtSDS8132322020101020nsnsnsnsnsnsnsnsnsTDM128 mode (TDM0= “1”, TDM1= “1”)BICK PeriodBICK Pulse Width LowPulse Width HighLRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTOSDTI1-2 Hold TimeSDTI1-2 Setup Time tBCKtBCKLtBCKHtLRBtBLRtBSDtSDHtSDS8132322020101020nsnsnsnsnsnsnsnsnsNotes: 18. BICK rising edge must not occur at the same time as LRCK edge.Parameter SymbolmintypmaxUnitsControl Interface Timing (3-wire Serial mode):CCLK PeriodCCLK Pulse Width LowPulse Width High CDTI Setup Time CDTI Hold TimeCSN “H” TimeCSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” tCCKtCCKLtCCKHtCDStCDHtCSWtCSStCSH200808040401505050nsnsnsnsnsnsnsnsControl Interface Timing (I2C Bus mode):SCL Clock FrequencyBus Free Time Between TransmissionsStart Condition Hold Time (prior to first clock pulse) Clock Low TimeClock High TimeSetup Time for Repeated Start ConditionSDA Hold Time from SCL Falling (Note 19) SDA Setup Time from SCL RisingRise Time of Both SDA and SCL LinesFall Time of Both SDA and SCL LinesSetup Time for Stop ConditionPulse Width of Spike Noise Suppressed by Input Filter fSCLtBUFtHD:STAtLOWtHIGHtSU:STAtHD:DATtSU:DATtRtFtSU:STOtSP-4.74.04.74.04.70.25--4.0100-------1.00.3-50kHzµsµsµsµsµsµsµsµsµsµsnsPower-down & Reset TimingPDN Pulse Width (Note 20) PDN “↑” to SDTO valid (Note 21) tPDtPDV150522ns1/fsNotes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.20. The AK4628A can be reset by bringing PDN “L” to “H” upon power-up.21. These cycles are the number of LRCK rising from PDN rising.22. I2C is a registered trademark of Philips Semiconductors.Timing DiagramVIHMCLKVILLRCKVIH VILVIH BICKVILClock Timing (TDM= “0”)VIH MCLKVILLRCKVIH VILVIH BICKVILClock Timing (TDM= “1”)LRCKVIH BICKVILSDTO50%TVDDVIH VILSDTIVIH VILAudio Interface Timing (TDM= “0”)LRCKVIH BICKVILSDTO50%TVDDVIH VILSDTIVIH VILAudio Interface Timing (TDM= “1”)CSNVIH CCLKVILVIH CDTI VILVIHVILWRITE Command Input Timing (3-wire Serial mode)CSNVIH CCLKVILVIH CDTI VILVIHVILD3D2D1D0WRITE Data Input Timing (3-wire Serial mode)VIHVILVIHVILI 2C Bus mode TimingVILPDNSDTO 50%TVDDVIHPower-down & Reset TimingOPERATION OVERVIEWSystem ClockThe external clocks, which are required to operate the AK4628A, are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2, 3, 4). In Auto Setting Mode (ACKS = “1”), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS.External clocks (MCLK, BICK) should always be present whenever the AK4628A is in normal operation mode (PDN = “H”). If these clocks are not provided, the AK4628A may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4628A should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4628A is in the power-down mode until MCLK and LRCK are input.(fs)SpeedDFS1 DFS0 SamplingDefaultMode 32kHz~48kHzSpeed0 0 Normal0 1 DoubleMode 64kHz~96kHzSpeedMode 120kHz~192kHz1 0 QuadSpeedTable 1. Sampling Speed (Manual Setting Mode)(MHz) BICK(MHz) LRCK MCLKfs 256fs 384fs 512fs 64fs32.0kHz 8.1920 12.2880 16.3840 2.048044.1kHz 11.2896 16.9344 22.5792 2.822448.0kHz 12.2880 18.4320 24.5760 3.0720Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)LRCK MCLK (MHz) BICK (MHz)fs 128fs 192fs 256fs 64fs88.2kHz 11.2896 16.9344 22.5792 5.644896.0kHz 12.2880 18.4320 24.5760 6.1440Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) (Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)LRCK MCLK (MHz) BICK (MHz)fs 128fs 192fs 256fs 64fs176.4kHz 22.5792 - - 11.2896192.0kHz 24.5760 - - 12.2880Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)MCLK Sampling Speed512fs Normal 256fs Double 128fs QuadTable 5. Sampling Speed (Auto Setting Mode)LRCK MCLK (MHz) fs 128fs 256fs 512fs Sampling Speed 32.0kHz - - 16.384044.1kHz - - 22.579248.0kHz - - 24.5760 Normal 88.2kHz - 22.5792 -96.0kHz - 24.5760 - Double176.4kHz 22.5792 - -192.0kHz 24.5760 - -QuadTable 6. System Clock Example (Auto Setting Mode)De-emphasis FilterThe AK4628A includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, DAC4: DEMD1-0, see “Register Definitions”).Mode Sampling Speed DEM1 DEM0 DEM 0 Normal Speed 0 0 44.1kHz 1 Normal Speed 0 1 OFF2 Normal Speed 1 0 48kHz3 Normal Speed 1 1 32kHzDefaultTable 8. De-emphasis controlDigital High Pass FilterThe ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and scales with sampling rate (fs).Audio Serial Interface FormatWhen TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the rising edge of BICK.Figures 1∼4 shows the timing at SDOS = “L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”, the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs.LRCK BICK Mode TDM 1 TDM0 DIF1 DIF0SDTOSDTI1-4,DAUXI/O I/O0 0 0 0 0 24bit, Left justified 20bit, Rightjustified H/LI ≥ 48fs I 1 0 0 0 1 24bit, Left justified 24bit, Rightjustified H/LI ≥ 48fs I 2 0 0 1 0 24bit, Left justified 24bit, LeftjustifiedH/LI≥ 48fsI Default 3 0 0 1 1 24bit, I 2S 24bit, I 2S L/HI ≥ 48fsITable 8. Audio data formats (Normal mode)The audio serial interface format becomes the TDM mode if TDM0 pin is set to “H”. In the TDM256 mode, the serial data of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown in Table 9. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) are input to the SDTI2. TDM0 pin and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register should be set to “H” if Double Speed Mode is selected in TDM128 Mode.LRCK BICKMode TDM 1 TDM0 DIF1 DIF0SDTO SDTI1I/O I/O4 0 1 0 0 24bit, Left justified 20bit, Rightjustified ↑I 256fs I 5 0 1 0 1 24bit, Left justified 24bit, Rightjustified ↑I 256fs I 6 0 1 1 0 24bit, Left justified 24bit, Leftjustified↑I 256fs I 7 0 1 1 1 24bit, I 2S 24bit, I 2S ↓I 256fs ITable 9. Audio data formats (TDM256 mode)LRCK BICKMode TDM 1 TDM0 DIF1 DIF0SDTOSDTI1, SDTI2 I/O I/O8 1 1 0 0 24bit, Left justified 20bit, Rightjustified ↑I 128fs I 9 1 1 0 1 24bit, Left justified 24bit, Rightjustified ↑I 128fs I 10 1 1 1 0 24bit, Left justified 24bit, Leftjustified↑I 128fs I 11 1 1 1 1 24bit, I 2S 24bit, I 2S ↓I 128fs ITable 10. Audio data formats (TDM128 mode)BICK(64fs)SDTO(o)SDTI(i)Figure 1. Mode 0 Timing Array LRCKBICK(64fs)SDTO(o)SDTI(i)Figure 2. Mode 1 TimingLRCKSDTO(o)SDTI(i)Figure 3. Mode 2 Timing ArrayLRCKSDTO(o)SDTI(i)Figure 4. Mode 3 TimingLRCKSDTO(o)SDTI1(i)Figure 5. Mode 4 TimingLRCKSDTO(o)SDTI1(i)Figure 6. Mode 5 TimingLRCKSDTO(o)SDTI1(i)Figure 7. Mode 6 TimingLRCKSDTO(o)SDTI1(i)Figure 8. Mode 7 TimingLRCKSDTO(o)SDTI1(i)SDTI2(i)Figure 9. Mode 8 TimingLRCKSDTI1(i)SDTI2(i)Figure 10. Mode 9 TimingLRCKSDTO(o)SDTI1(i)SDTI2(i)Figure 11. Mode 10 TimingSDTO(o)SDTI1(i)SDTI2(i)Figure 12. Mode 11 TimingOverflow DetectionThe AK4628A has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF outputfor overflowed analog input has the same group delay as ADC (GD = 16/fs = 333µs @fs=48kHz). OVF is “L” for 522/fs(=11.8ms @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled.Zero DetectionThe AK4628A has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L”and DZFE = “L” (Table 11). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0 if DZFE=“H” regardless of P/S pin. DZF1 is AND of all eight channels and DZF2 is disabled (“L”) at mode 0. Table 12 shows therelation of P/S, DZFE, OVFE and DZF.When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2)pin goes to “H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in the group 1(group 2) is notzero after going DZF1(DZF2) “H”.DZFM AOUT Mode 3 2 1 0 L1 R1 L2 R2 L3 R3 L4 R4 0 0 0 0 0 DZF1 DZF1DZF1DZF1DZF1DZF1DZF1 DZF1 1 0 0 0 1 DZF1 DZF1DZF1DZF1DZF1DZF2DZF2 DZF2 2 0 0 1 0 DZF1 DZF1DZF1DZF1DZF2DZF2DZF2 DZF2 3 0 0 1 1 DZF1 DZF1DZF1DZF2DZF2DZF2DZF2 DZF2 4 0 1 0 0 DZF1 DZF1DZF2DZF2DZF2DZF2DZF2 DZF2 5 0 1 0 1 DZF1 DZF2DZF2DZF2DZF2DZF2DZF2 DZF2 6 0 1 1 0 DZF2 DZF2DZF2DZF2DZF2DZF2DZF2 DZF2 7 0 1 1 1 disable (DZF1=DZF2 = “L”)8 1 0 0 0 DZF1 DZF1DZF1DZF1DZF1DZF1DZF1 DZF29 1 0 0 1 DZF1 DZF1DZF1DZF1DZF1DZF1DZF2 DZF210 1 0 1 011 1 0 1 112 1 1 0 0 13 1 1 0 114 1 1 1 015 1 1 1 1disable (DZF1=DZF2 = “L”)DefaultTable 11. Zero detect controlP/S pin DZFE pin OVFE bit DZF mode DZF1 pin DZF2/OVF pin“L” disable Mode 7 “L” “L”“H” (parallel mode) “H” disable Mode 0 AND of 6ch “L”“0” Selectable Selectable Selectable“L” “1” Selectable Selectable OVF output“0” Mode 0 AND of 6ch “L”“L” (serial mode) “H” “1” Mode 0 AND of 6ch OVF outputTable 12. DZF1-2 pins outputs。

9 –12
PGND
Power Ground
Device high-current power ground.
13
D2
Disable 2
Active Low input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is logic Low, both outputs are tri-stated.
5.0 V Reguullator
IN1
IN2
Gate Drive
D1
D2
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Document Number: MC33886 Rev 8.0, 2/2007
33886
H-BRIDGE
VW SUFFIX (PB-FREE) DH SUFFIX
98ASH70702A 20-PIN HSOP
ORDERING INFORMATION
Device
MC33886DH/R2 MC33886VW/R2
Logic Input Control 2 True logic input control of OUT2 (i.e., IN2 logic High = OUT2 logic High).
Analog Integrated Circuit Device Data Freescale Semiconductor

50 MHz to 1000 MHzQuadrature DemodulatorAD8348 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESIntegrated I/Q demodulator with IF VGA amplifier Operating IF frequency 50 MHz to 1000 MHz(3 dB IF BW of 500 MHz driven from R S = 200 Ω) Demodulation bandwidth 75 MHzLinear-in-decibel AGC range 44 dBThird-order interceptIIP3 +28 dBm @ minimum gain (F IF = 380 MHz) IIP3 −8 dBm @ maximum gain (F IF = 380 MHz) Quadrature demodulation accuracyPhase accuracy 0.5°Amplitude balance 0.25 dBNoise figure 11 dB @ maximum gain (F IF = 380 MHz) LO input −10 dBmSingle supply 2.7 V to 5.5 VPower-down modeCompact, 28-lead TSSOP packageAPPLICATIONSQAM/QPSK demodulatorW-CDMA/CDMA/GSM/NADCWireless local loopLMDS FUNCTIONAL BLOCK DIAGRAM3678-1Figure 1.GENERAL DESCRIPTIONThe AD8348 is a broadband quadrature demodulator with an integrated intermediate frequency (IF), variable gain amplifier (VGA), and integrated baseband amplifiers. It is suitable for use in communications receivers, performing quadrature demodulation from IF directly to baseband frequencies. The baseband amplifiers are designed to interface directly with dual-channel ADCs, such as the AD9201, AD9283, and AD9218, for digitizing and post-processing.The IF input signal is fed into two Gilbert cell mixers through an X-AMP® VGA. The IF VGA provides 44 dB of gain control.A precision gain control circuit sets a linear-in-decibel gain char-acteristic for the VGA and provides temperature compensation. The LO quadrature phase splitter employs a divide-by-2 frequency divider to achieve high quadrature accuracy and amplitude balance over the entire operating frequency range.Optionally, the IF VGA can be disabled and bypassed. In this mode, the IF signal is applied directly to the quadrature mixer inputs via the MXIP and MXIN pins. Separate I- and Q-channel baseband amplifiers follow the baseband outputs of the mixers. The voltage applied to the VCMO pin sets the dc common-mode voltage level at the baseband outputs. Typically, VCMO is connected to the internal VREF voltage, but it can also be connected to an external voltage. This flexibility allows the user to maximize the input dynamic range to the ADC. Connecting a bypass capacitor at each offset compensation input (IOFS and QOFS) nulls dc offsets produced in the mixer. Offset compensation can be overridden by applying an external voltage at the offset compensation inputs.The mixers’ outputs are brought off-chip for optional filtering before final amplification. Inserting a channel selection filter before each baseband amplifier increases the baseband amplifiers’ signal handling range by reducing the amplitude of high level, out-of-channel interferers before the baseband signal is fed into the I/Q baseband amplifiers. The single-ended mixer output is amplified and converted to a differential signal for driving ADCs.AD8348Rev. A | Page 2 of 28TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Equivalent Circuits...........................................................................9 Typical Performance Characteristics...........................................11 VGA and Demodulator.............................................................11 Demodulator Using MXIP and MXIN....................................14 Final Baseband Amplifiers........................................................15 VGA/Demodulator and Baseband Amplifier.........................16 Theory of Operation......................................................................18 VGA..............................................................................................18 Downconversion Mixers...........................................................18 Phase Splitter...............................................................................18 I/Q Baseband Amplifiers...........................................................18 Enable...........................................................................................18 Baseband Offset Cancellation...................................................18 Applications.....................................................................................20 Basic Connections......................................................................20 Power Supply...............................................................................20 Device Enable.............................................................................20 VGA Enable................................................................................20 Gain Control...............................................................................20 LO Inputs.....................................................................................20 IF Inputs......................................................................................20 MX Inputs...................................................................................20 Baseband Outputs......................................................................21 Output DC Bias Level................................................................21 Interfacing to Detector for AGC Operation...............................21 Baseband Filters..........................................................................22 LO Generation............................................................................23 Evaluation Board........................................................................23 Outline Dimensions.......................................................................28 Ordering Guide.. (28)REVISION HISTORY4/06—Rev. 0 to Rev. AUpdated Format..................................................................Universal Changes to Specifications................................................................3 Changes to IF Inputs Section........................................................20 Changes to Evaluation Board Section..........................................23 Changes to Table 6..........................................................................27 Changes to Ordering Guide..........................................................28 8/03—Revision 0: Initial VersionAD8348Rev. A | Page 3 of 28SPECIFICATIONSV S = 5 V , T A = 25o C, F LO = 380 MHz, F IF = 381 MHz, P LO = −10 dBm, R S (LO) = 50 Ω, R S (IFIP and MXIP/MXIN) = 200 Ω, unless otherwise noted. Table 1.Parameter Conditions Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range External input = 2 × LO frequency 100 2000 MHz IF Frequency Range 50 1000 MHz Baseband Bandwidth 75 MHz LO Input Level 50 Ω source −12 −10 0 dBm V SUPPLY (V S ) 2.7 5.5 V Temperature Range −40 +85 °C IF FRONT END WITH VGA IFIP to IMXO (QMXO), ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ Input Impedance Measured differentially across MXIP/MXIN 200||1.1 Ω||pF Gain Control Range 44 dB Maximum Conversion Voltage Gain VGIN = 0.2 V (maximum voltage gain) 25.5 dB Minimum Conversion Voltage Gain VGIN = 1.2 V (minimum voltage gain) −18.5 dB 3 dB Bandwidth 500 MHz Gain Control Linearity VGIN = 0.4 V (+21 dB) to 1.1 V (−14 dB) ±0.5 dB IF Gain Flatness F IF = 380 MHz ± 5% (VGIN = 1.2 V) 0.1 dB p-p F IF = 900 MHz ± 5% (VGIN = 1.2 V) 1.3 dB p-p Input 1 dB Compression Point (P1dB) VGIN = 0.2 V (maximum gain) −22 dBmVGIN = 1.2 V (maximum gain) +13 dBm Second-Order Input Intercept (IIP2) IF1 = 385 MHz, IF2 = 386 MHz+3 dBm each tone from 200 Ω source, 65 dBm VGIN = 1.2 V (minimum gain)−42 dBm each tone from 200 Ω source, 18 dBmVGIN = 0.2 V (maximum gain) Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz Each tone 10 dB below P1dB from 200 Ω source,28 dBm VGIN = 1.2 V (minimum gain)Each tone 10 dB below P1dB from 200 Ω source,−8 dBmVGIN = 0.2 V (maximum gain)LO Leakage Measured at IFIP , IFIN −80 dBm Measured at IMXO/QMXO (LO = 50 MHz) −60 dBm Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz Quadrature Phase Error 1LO = 380 MHz (LOIP/LOIN 760 MHz) −0.7 ±0.1 +0.7 Degrees vs. temperature −0.0032 °/°C vs. baseband frequency (dc to 30 MHz) +0.01 °/MHzI/Q Amplitude Imbalance 1−0.3 ±0.05 +0.3 dB vs. temperature 0 dB/°C vs. baseband frequency (dc to 30 MHz) ±0.0125 dB Noise Figure (Double Sideband) Maximum gain, from 200 Ω source,F IF = 380 MHz10.75 dB Mixer Output Impedance 40 Ω Capacitive Load Shunt from IMXO, QMXO to VCMO 0 10 pF Resistive LoadShunt from IMXO, QMXO to VCMO 200 1.5 kΩ Mixer Peak Output Current 2.5 mAAD8348Rev. A | Page 4 of 28Parameter Conditions Min Typ Max Unit IF FRONT END WITHOUT VGA From MXIP , MXIN to IMXO (QMXO), ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ Input Impedance Measured differentially across MXIP/MXIN 200||1.5 Ω||pF Conversion voltage Gain 10.5 dB 3 dB Output Bandwidth 75 MHz IF Gain Flatness F IF = 380 MHZ ± 5% 0.1 dB p-p F IF = 900 MHZ ± 5% 0.15 dB p-p Input 1 dB Compression Point (P1dB) −4 dBm Third-Order Input Intercept (IIP3) IF1 = 381 MHz, IF2 = 381.02 MHz 14 dBm Each tone 10 dB below P1dB from200 Ω sourceLO Leakage Measured at MXIP/MXIN −70 dBm Measured at IMXO, QMXO −60 dBm Demodulation Bandwidth Small signal 3 dB bandwidth 75 MHz Quadrature Phase Error LO = 380 MHz (LOIP/LOIN 760 MHz,single-ended)−2 ±0.5 +2 Degrees I/Q Amplitude Imbalance 0.25 dB Noise Figure (Double Sideband) From 200 Ω source, F IF = 380 MHz 21 dB I/Q BASEBAND AMPLIFIER From IAIN to IOPP/IOPN and QAIN to QOPP/QOPN, R LOAD = 2 kΩ, single-ended to groundGain 20 dB Bandwidth 10 pF differential load 125 MHz Output DC Offset (Differential) LO leakage offset corrected using 500 pFcapacitor on IOFS, QOFS (V IOPP − V IOPN )−50 ±12 +50 mV Output Common-Mode Offset (V IOPP + V IOPN )/2 − VCMO −75 ±35 +75 mV Group Delay Flatness 0 MHz to 50 MHz 3 ns p-p Input-Referred Noise Voltage Frequency = 1 MHz 8 nV/√Hz Output Swing Limit (Upper) V S −1 V Output Swing Limit (Lower) 0.5 V Peak Output Current 1 mA Input Impedance 50||1 kΩ||pF Input Bias Current 2 μARESPONSE FROM IF AND MX INPUTS TO BASEBAND AMPLIFIER OUTPUT IMXO and QMXO connected directly toIAIN and QAIN, respectivelyGain From MX I P/MX I N 30.5 dB From IFIP/IFIN, VGIN = 0.2 V 45.5 dB From IFIP/IFIN, VGIN = 1.2 V 1.5 dB CONTROL INPUT/OUTPUTS VCMO Input Range V S = 5 V 0.5 1 4 V V S = 2.7 V 0.5 1 1.7 V VREF Output Voltage 0.95 1 1.05 V Gain Control Voltage Range VGIN 0.2 1.2 V Gain Slope −55 −50 −45 dB/V Gain Intercept Linear extrapolation back to theoreticalgain at VGIN = 0 V55 61 67 dB Gain Control Input Bias Current 1 μA LO INPUTSLOIP Input Return Loss LOIN ac-coupled to ground(760 MHz applied to LOIP)−6 dBAD8348Rev. A | Page 5 of 28Parameter Conditions Min Typ Max Unit POWER-UP CONTROL ENBL Threshold Low Low = standby 0 V S /2 1 V ENBL Threshold High High = enable V S − 1 V S /2 V S V Input Bias Current 2 μA Power-Up Time Time for final baseband amplifiers to bewithin 90% of final amplitude45 μs Power-Down Time Time for supply current to be <10% ofenabled value700 ns POWER SUPPLIES VPOS1, VPOS2, VPOS3Voltage 2.7 5.5 V Current (Enabled) V S = 5 V, V ENBL = 5 V 38 48 58 mA Current (Standby) V S = 5 V, V ENBL = 0 V 75 μA1These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean.AD8348Rev. A | Page 6 of 28ABSOLUTE MAXIMUM RATINGSTable 2.Parameter RatingSupply Voltage on VPOS1, VPOS2, VPOS3 Pins 5.5 VLO Input Power 10 dBm (re: 50 Ω)IF Input Power 18 dBm (re: 200 Ω)Internal Power Dissipation 450 mWθJA 68°C/WMaximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°CLead Temperature (Soldering, 60 sec) 300°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or anyother conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performancedegradation or loss of functionality.AD8348Rev. A | Page 7 of 28PIN CONFIGURATION AND FUNCTION DESCRIPTIONSLOIPVPOS1IOPN IOPP VCMO IAIN COM3IMXO COM2IFIN IFIP VPOS2IOFS VREF 03678-002Figure 2. 28-Lead TSSOP Pin ConfigurationTable 3. Pin Function Descriptions—28-Lead TSSOPPin No. Mnemonic DescriptionEquivalent Circuit 1, 28LOIP , LOINLO Inputs. For optimum performance, these inputs should be ac-coupled and driven differentially. Differential drive from single-ended sources can be achieved via a balun. To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between LOIP and LOIN. Typical input drive level is equal to −10 dBm.A2, 12, 20 VPOS1, VPOS2, VPOS3 Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pinsshould be decoupled with 0.1 μF and 100 pF capacitors.3, 4, 25, 26 IOPN, IOPP , QOPP , QOPN I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-pdifferential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.B 5 VCMO Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dccommon-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP , IOPN, QOPP , QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference voltage from another device (typically an ADC).C6, 23 IAIN, QAIN I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins arereferenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.D7, 22 COM3 Ground for Biasing and Baseband Sections. 8, 21 IMXO, QMXO I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whosebias levels are set by the voltage applied to the VCMO pin. These pins are typically connected to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a maximum current of 2.5 mA.H9 COM2 IF Section Ground. 10, 11 IFIN, IFIP IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal shouldbe ac-coupled into IFIP . The nominal differential input impedance of these pins is 200 Ω. For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; R SERIES = 174 Ω, R SHUNT = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348 does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor can be placed between IFIP and IFIN.E13, 16 IOFS, QOFS I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can extend the operating frequency range to include dc. The QOFS pin can likewise be used to null offsets on the Q-channel mixer output (QMXO).F14 VREF Reference Voltage Output. This output voltage (1 V) is the main bias level for the deviceand can be used to externally bias the inputs and outputs of the baseband amplifiers. The typical maximum drive current for this output is 2 mA.GAD8348Rev. A | Page 8 of 28Pin No. Mnemonic Description EquivalentCircuit 15 ENBL Chip Enable Input. Active high. Threshold is equal to V S /2. D 17 VG IN Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative sense (that is, increasing voltage decreases gain).D18, 19 MXIP , MXIN Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully differential inputs that should be ac-coupled to the signal source.I24 ENVG Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and IFIP and IFIN inputs are disabled.D27 COM1 LO Section Ground.AD8348Rev. A | Page 9 of 28EQUIVALENT CIRCUITSLOIN LOIP03678-003Figure 3. Circuit A VCMOVPOS3IOPP , IOPN,QOPP , QOPN 03678-004Figure 4. Circuit BVCMO03678-005Figure 5. Circuit C 03678-006Figure 6. Circuit DVPOS2IFIPIFIN03678-007Figure 7. Circuit E03678-008Figure 8. Circuit FAD8348Rev. A | Page 10 of 2803678-009Figure 9. Circuit G03678-010Figure 10. Circuit H03678-011Figure 11. Circuit IRev. A | Page 11 of 28TYPICAL PERFORMANCE CHARACTERISTICSVGA AND DEMODULATORVGIN (V)V G A A N D M I X E R G A I N (d B )L I N E A R I T Y E R R O R (d B )0.20.30.4–20–5–10–15105030252015–6–3–4–50–1–243210.50.60.70.80.9 1.0 1.1 1.203678-012Figure 12. Mixer Gain and Linearity Error vs. VGIN, V POS = 5 V, F IF = 380 MHz,F BB = 1 MHz, Temperature = −40°C, +25°C, +85°CVGIN (V)V G A A N D M I X E R G A I N (d B )L I N E A R I T Y E R R O R (d B )0.20.30.4–25–10–15–2050–525201510–6–3–4–50–1–243210.50.60.70.80.9 1.0 1.1 1.203678-013Figure 13. Mixer Gain and Linearity Error vs. VGIN, V POS = 5 V, F IF = 900 MHz,F BB = 1 MHz, Temperature = −40°C, +25°C, +85°C VGIN (V)V G A A N D M I X E R G A I N (d B )L I N E A R I T Y E R R O R (d B )0.20.30.4–6–3–4–50–1–243210.50.60.70.80.91.01.11.203678-014Figure 14. Mixer Gain and Linearity Error vs. VGIN, V POS = 2.7 V, F IF = 380 MHz,F BB = 1 MHz, Temperature = −40°C, +25°C, +85°CVGIN (V)V G A A N D M I X E R G A I N (d B )L I N E A R I T Y E R R O R (d B )0.20.30.4–25–10–15–2050–525201510–6–3–4–50–1–243210.50.60.70.80.91.01.11.203678-015Figure 15. Mixer Gain and Linearity Error vs. VGIN, V POS = 2.7 V, F IF = 900 MHz,F BB = 1 MHz, Temperature = −40°C, +25°C, +85°CIF FREQUENCY (MHz)V G A A N D M I X E R G A I N (d B )100182022242628200300400500600700800900100003678-016Figure 16. Gain vs. F IF , VGIN = 0.2 V, F BB = 1 MHz,Temperature = −40°C, +25°C, +85°CIF FREQUENCY (MHz)V G A A N D M I X E R G A I N (d B )100–30–25–20–15200300400500600700800900100003678-017Figure 17. Gain vs. F IF , VGIN = 1.2 V, F BB = 1 MHz,Temperature = −40°C, +25°C, +85°CRev. A | Page 12 of 28BASEBAND FREQUENCY (MHz)V G A A N D M I X E R G A I N (d B )1001718192021222325262427203040506070809010003678-018Figure 18. Gain vs. F BB , VGIN = 0.2 V, F IF = 380 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CBASEBAND FREQUENCY (MHz)V G A A N D M I X E R G A I N (d B )10–26–23–20–17203040506070809010003678-019Figure 19. Gain vs. F BB , VGIN = 1.2 V, F IF = 380 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°C VGIN (V)I N P U T 1d B C O M P R E S S I O N P O I N T (d B m ) (r e 200Ω)0.30.2–25–10–15–20–515100.40.50.60.70.80.91.01.11.203678-020Figure 20. Input 1 dB Compression Point (IP1dB) vs. VGIN, F IF = 380 MHz, F BB = 1 MHz, V POS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°CVGIN (V)I N P U T 1d B C O M P R E S S I O N P O I N T (d B m ) (r e 200Ω)0.30.2–20–5–10–15105020150.40.50.60.70.80.91.01.11.203678-021Figure 21. Input 1 dB Compression Point (IP1dB) vs. VGIN, F IF = 900 MHz, F BB = 1 MHz, V POS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°CIF FREQUENCY (MHz)I N P U T I I P 3 (d B m ) (r e 200Ω)20010024262528273029300400500600700800900100003678-022Figure 22. IIP3 vs. F IF , VGIN = 1.2 V, F BB = 1 MHz, V POS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C, Tone Spacing = 20 kHzIF FREQUENCY (MHz)I N P U T I I P 3 (dB m ) (r e 200Ω)100200–15–10–5300400500600700800900100003678-023Figure 23. IIP3 vs. F IF , VGIN = 0.2 V, F BB = 1 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CRev. A | Page 13 of 28BASEBAND FREQUENCY (MHz)V G A A N D M I X E R I N P U T I I P 3 (d B m ) (r e 200Ω)100202226242830323040506070809010003678-024Figure 24. IIP3 vs. F BB , VGIN = 1.2 V, F IF = 380 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°C BASEBAND FREQUENCY (MHz)V G A A N D M I X E R I N P U T I I P 3 (d B m ) (r e 200Ω)10020–20–15–10–53040506070809010003678-025Figure 25. IIP3 vs. F BB , VGIN = 0.2 V, F IF = 380 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°C IF FREQUENCY (MHz)N O I S E F I G U R E (d B )15050250891011121314151635045055065075085095003678-026Figure 26. Noise Figure vs. F IF , T = 25°C, VGIN = 0.2 V, F BB = 1 MHzVGIN (V)N O I S E F I G U R E (d B )I N P U T I I P 3 (d B m ) (r e 200Ω)0.20.30.4015105302520454035–1050–51510353025200.50.60.70.80.9 1.0 1.11.203678-027NFIIP3Figure 27. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,F IF = 380 MHz, F BB = 1 MHz, V POS = 2.7 VVGIN (V)N O I S E F I G U R E (d B )I N P U T I I P 3 (d B m ) (r e 200Ω)0.20.30.40151053025204035–1050–51510353025200.50.60.70.80.9 1.0 1.11.203678-028NFIIP3Figure 28. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,F IF = 380 MHz, F BB = 1 MHz, V POS = 5 VLO INPUT LEVEL (V)N O I S E F I G U R E (d B )P H A S E E R R OR (D e g r e e s )–12–108111091413121615–2.0–0.5–1.0–1.502.01.51.00.5–8–6–4–203678-029Figure 29. Noise Figure and Quadrature Phase Error IMXO/QMXO vs. LO InputLevel, Temperature = 25°C, VGIN = 0.2 V, V POS = 5 V for F IF = 50 MHz,380 MHz, and 900 MHzRev. A | Page 14 of 28DEMODULATOR USING MXIP AND MXINIF FREQUENCY (MHz)M I X E R G A I N (d B )1002008.58.010.09.59.011.010.5300400500600700800900100003678-030Figure 30. Mixer Gain vs. F IF , V POS = 2.7 V, 5 V, F BB = 1 MHz,Temperature = −40°C, +25°C, +85°CIF FREQUENCY (MHz)M I X E R I N P U T P 1d B (d B m ) (r e 200Ω)100200–8.0–6.5–7.0–7.5–3.0–2.5–2.0–3.5–4.0–4.5–5.0–5.5–6.0–1.5300400500600700800900100003678-031Figure 31. Input 1 dB Compression Point vs. F IF , F BB = 1 MHz, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CIF FREQUENCY (MHz)I N P U T I I P 3 (d B m ) (r e 200Ω)50150101421.01312111716151825035045055065075085095003670-032N O I S E F I G U R E (d B )19.020.520.019.523.022.522.021.5Figure 32. IIP3 and Noise Figure vs. F IF , V POS = 2.7 V, 5 V, Temperature = 25°CRev. A | Page 15 of 28FINAL BASEBAND AMPLIFIERSBASEBAND FREQUENCY (MHz)G A I N (d B )0.1141317161520191821110100100003678-033Figure 33. Gain vs. F BB , V VCMO = VREF = 1 V, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°C BASEBAND FREQUENCY (MHz)O P 1d B (d B V )0.1–15–20–10–55110100100003678-034Figure 34. OP1dB Compression vs. F BB , V VCMO = VREF = 1 V, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CBASEBAND FREQUENCY (MHz)O I P 3 (d B V )10–101015202530–15–505355070903013011015017019003678-035Figure 35. OIP3 vs. F BB , V VCMO = VREF = 1 V, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CFREQUENCY (kHz)11010010001000010000003678-036Figure 36. Noise Spectral DensityRev. A | Page 16 of 28VGA/DEMODULATOR AND BASEBAND AMPLIFIERIF FREQUENCY (MHz)Q U A D R A T U R E P H A S E E R R O R (D e g r e e s )100–1.50.51.01.5–2.0–1.0–0.52.0200300400500600700800900100003678-037Figure 37. Quadrature Phase Error vs. F IF , VGIN = 0.7 V, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°CBASEBAND FREQUENCY (MHz)Q U A D R A T U R E P H A S E E R R O R (D e g r e e s )–1.50.51.01.5–2.0–1.0–0.52.0501015202530354003678-038Figure 38. Quadrature Phase Error vs. F BB , VGIN = 0.7 V, V POS = 2.7 V, 5 V,Temperature = −40°C, +25°C, +85°C, F IF = 380 MHzBASEBAND FREQUENCY (MHz)I /QA M P L I T U D E M I S M A T C H (dB )–0.4–0.20.20.451015202530354003678-039Figure 39. I/Q Amplitude Imbalance vs. F BB , Temperature = 25°C, V POS = 5 VIF FREQUENCY (MHz)I /Q A M PL I T U D E M I S M A T C H (d B )–1.500.51.01.5–2.0–1.0–0.52.020*******400500600700800900100003678-040Figure 40. I/Q Amplitude Imbalance vs. F IF , Temperature = 25°C, V POS = 5 VIF FREQUENCY (MHz)S H U N T R E S I S T A N C E (Ω)S H U N T C A P A C I T A N C E (p F )501502501001601401202202001803002802602400.20.80.60.41.41.21.02.22.01.81.635045055065075085095003678-041Figure 41. Input Impedance of IF Input vs. F IF , VGIN = 0.7 V, V POS = 5 V03678-042Figure 42. S11 of IF Input vs. F IF , F IF = 50 MHz to 1 GHz, VGIN = 0.7 V,V POS = 5 V (with L Pad, with No Pad, Normalized to 50 Ω)。