英特尔将推进到10纳米,但在7纳米将告别硅元素
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Intel forges ahead to 10nm, will move away from silicon at 7nm
英特尔将推进到10纳米，但在7纳米将告别硅元素
This week at the 2015 International Solid-State Circuits Conference (ISSCC), Intel will provide an update on its new 10nm manufacturing process and new research on how it's maintaining the march of Moore's law to 7nm and beyond. The first chips based on Intel's new 10nm process are expected in late 2016/early 2017, and the company says it's hoping to avoid the delays that haunted the belabored release of 14nm Broadwell. To hit 7nm, Intel says new materials will be required—as in, it looks like 10nm will finally be the end of the road for silicon. The most likely replacement for silicon is a III-V semiconductor such as indium gallium arsenide (InGaAs), though Intel hasn't provided any specific details yet.
大意：英特尔将对10纳米进行升级，并继续研究如何跟随摩尔定律将制程推进到7纳米。
10纳米制程预计将在2016年或2017年早期到来。
为达到7纳米，英特尔将采用新材料，最有可能是元素周期表中III族和V族的化合物----铟镓砷化物。
ISSCC 2015, being held in San Francisco this week, is where all the big players in silicon (Intel, Samsung, TSMC, IBM, etc.) meet to talk about their latest manufacturing processes and how they might go about overcoming the current barriers to smaller, faster, and denser computer chips. It's not unusual for Intel to have one of the largest presences at the conference, and this year is no different: it will be presenting three papers on its 14nm technology, hosting sessions on a variety of topics, and Mark Bohr—one of Intel's most esteemed researchers—will be sitting on a panel that discusses Moore's law beyond 10nm.
大意：略
The steady march of new CMOS processes driving ever smaller transistors
On a conference call last week, Intel gave reporters a preview of what to expect at ISSCC, along with some updates on its upcoming 10nm process and the difficult step down to 7nm. On the call, Intel acknowledged that its Broadwell chips were delayed due to the unforeseen complexity of manufacturing at 14nm, but the company says it hopes to avoid the same delays with 10nm, even though it will require even more steps than 14nm.
大意：在电话会议上，英特尔承认由于14纳米不可预见的制造的复杂性，导致Broadwell 芯片跳票。
但是英特尔希望10纳米不要再跳票，尽管其工艺要比14纳米有着更多的工序。
More interesting than 10nm, though, is the news that Intel is looking to move away from silicon FinFETs for its 7nm process. While Intel didn't provide any specifics, we strongly suspect that we're looking at the arrival of transistors based on III-V semiconductors. III-V semiconductors have higher electron mobility than silicon, which means that they can be fashioned into smaller and faster (as in higher switching speed) transistors. The topic of extreme UV (EUV) lithography also came up during the call, but due to continued problems with EUV deployment, it sounds like Intel is planning to do both 10nm and 7nm without it.
大意：更有意思的是，英特尔将在7纳米将告别硅元素。
尽管英特尔没有细谈，我们推测可能采用元素周期表中III族和V族的化合物来制造晶体管。
III族和V族的半导体化合物比硅元素具有更高的电子移动性，意味着可以制造更小、更快的晶体管。
电话会议也谈到极紫外光刻，但是由于极紫外光刻设备的部署问题，看起来英特尔在10纳米、7纳米上还用不到极紫外光刻
Due to other constraints—thermals, power consumption, and form factor—Intel is also looking into new types of packaging: 2.5D, where separate dies are placed side by side on an interposer, and 3D, where each die is stacked directly on top of each other. Both 2.5D and 3D packaging are good for reducing power consumption, with 3D really coming into its own with mobile and wearable devices.
大意：由于热量、功耗、体积等因素的限制，英特尔正在寻求新的封装方式，即，第一，2.5D 方式，就是芯片核心是以平面置放在载板上；第二，3D方式，就是芯片核心堆栈起来。
2.5D 与3D 封装能够很好减低功耗。
3D特别适合移动与可穿戴设备。
