Atmega16开发板V1.1

1.概述本单片机小系统板为一单元实验板，使用一颗基于A VR构架的A Tmega16单片机。

A Tmega16有16KB的程序存储空间，1KB内部SRAM，512B内置EEPROM。

外部共有32个GPIO，一路USART，一路主从SPI，一路I2C，两个8位定时器，一个16位定时器，4通道PWM输出，8路10位AD输入。

还有各种丰富的管脚中断和不同的时钟可供使用。

2.硬件说明1．本单片机小系统板的电源输入电压为DC 2.7--5V，科创课程实验建议使用DC 5V。

2．小系统板上的P1为下载口，可供程序烧录、eeprom数据读写、熔断丝设置。

3．小系统板上的接插件PB、PC、PD分别对应A Tmega16芯片引脚的PB、PC、PD口。

PB、PC、PD口是八位数据端口，可作为通用IO口，也可用作第二功能使用，具体请参见datasheet的相关部分。

4．小系统板上的接插件PA的1-5脚分别连接A Tmega16芯片PA口的PA0-PA4，PA0-PA4是AD转换的模拟电压输入端口，也可作为通用IO口使用。

5．小系统板上的接插件PA的9脚连接A Tmega16芯片的V ref ，10脚接地。

A Tmega16有一个标称值为2.56V的内部基准源，每颗芯片的实际值会有所不同。

6．A Tmega16 PA口的PA5-PA7作为串行数据输出到小系统板上的74HC595上，有二片74HC595驱动4位数码管和4个LED灯。

小系统板上的P2作为串行数据输出总线，可级联74HC595。

7．小系统板上的四个按钮SW1-4分别连接在A Tmega16芯片PC4-7。

按钮RST为复位键。

3.开发环境推荐的入门开发环境为A VR studio 4 + WinA VR，即使用Atmel的免费IDE A VR studio 4和基于gcc的WinA VR编译器。

软件安装这两个软件的安装非常简单，双击之后一路回车即可。

官方下载地址：A VR studio 4：/dyn/products/tools_card.asp?tool_id=2725WinA VR：/projects/winavr/files/课程FTP://202.120.39.248也会提供软件包。

北京科技大学微型计算机原理实验报告学院：____自动化学院________________专业、年级：_自动化1101_ ______________ 姓名：__廖文骏_ ________________学号：_ 20111002124 ____________ 指导教师：___ _____王粉花____________2013年12 月综合实验一按键控制流水灯实验（查询方式）实验学时：2学时一、实验目的1．掌握ATmega16 I/O口操作相关寄存器2．掌握CodeVision AVR软件的使用3. 复习C语言，总结单片机C语言的特点二、实验内容1. 设计一个简单控制程序，功能是8个LED逐一循环发光0.5s，构成“流水灯”。

2. 用两个按键K1和K2控制流水灯（中断方式）：（1）当按下K1时，流水灯从左向右流动；（2）当按下K2时，流水灯从右向左流动。

三、实验所用仪表及设备硬件：PC机一台、AVR_StudyV1.1实验板软件：CodeVision AVR集成开发软件、SLISP下载软件四、实验原理ATmega16芯片有PORTA、PORTB、PORTC、PORTD（简称PA、PB、PC、PD）4组8位，共32路通用I/O接口，分别对应于芯片上32根I/O引脚。

所有这些I/O口都是双（有的为3）功能复用的。

其中第一功能均作为数字通用I/O接口使用，而复用功能则分别用于中断、时钟/计数器、USRAT、I2C和SPI串行通信、模拟比较、捕捉等应用。

这些I/O口同外围电路的有机组合，构成各式各样的单片机嵌入式系统的前向、后向通道接口，人机交互接口和数据通信接口，形成和实现了千变万化的应用。

每组I/O口配备三个8位寄存器，它们分别是方向控制寄存器DDRx，数据寄存器PORTx，和输入引脚寄存器PINx（x=A\B\C\D）。

I/O口的工作方式和表现特征由这3个I/O口寄存器控制。

AVR通用I/O端口的引脚配置情况：I/O口引脚配置表表中的PUD为寄存器SFIOR中的一位，它的作用相当AVR全部I/O口内部上拉电阻的总开关。

一、开展本课题的意义及工作内容：课题意义：数字存储示波器是集数据采集和模拟示波器优点于一身的一种精密测量设备，可以将其看作带有显示功能的数据采集系统，亦可将其看作是具有量化存储功能的模拟示波器。

与数据采集系统比，它一般有很多优点：如（1）更宽的输入频带；（2）更高的采样速率；（3）更深的存储深度，并有着数据采集系统所不具备的：直观屏幕显示功能；等效采样等等。

工作内容：利用单片机设计数字存储示波器。

用软件和硬件相结合快速把模拟信号转换为数字量，核心是用avr 单片机内带的10位AD 的转换器技术。

其模拟量通过示波器显示出来。

包括：数据采集模块，数据存储模块，数据输出模块。

二、课题预期达到的效果：(1)要求单边输入,不需要加入前级，可测0-5V 20K 以下任意波形。

双边输入，需要接入前级电路。

+ - 5V 范围。

(2)要求仪器的输入阻抗大于100k,垂直分辨率为12级/div ，水平分辨率为12点/div ；设示波器显示屏水平刻度为7div ，垂直刻度为4div 。

(3)要求设置2s/div 、0.2ms/div 二档扫描速度，仪器的频率范围为DC~500hz ，误差≤5%，。

(4)要求设置1.0V/div 、1.2V/div 二挡垂直灵敏度，误差≤5%。

(5)观测波形无明显失真。

二、文献综述(1) 前言示波器是最常用的一种电子测量仪器，能够直接有效地将被测信号显示出来，方便观察和测试被测信号的各种参数，完成其它测量仪器达不到的目的，是电子工程师完成电路设计、调试的有利工具。

主要研究内容目标特色 数字存储示波器是随着数字集成电路技术的发展而出现的新型智能化示波器，已经成为电子测量领域的基础测试仪器。

随着新技术、新器件的发展，它正在向宽带化、模块化、多功能和网络化的方向发展。

数字存储示波器的优势是可以实现高带宽及强大的分析功能.现在高端数字存储示波器的实时带宽已达到20GHZ ，可以广泛应用于各种千兆以太网、光通讯等测试领域。

Atmega16寄存器Atmega16寄存器一.引脚说明表1 引脚说明引脚序号 引脚名称 引脚功能PB5 8 位双向I/O 口, 具有可编程的内部上拉电阻。

其输出缓冲器具有对称的驱动特性，可以输出和吸收大电流。

作为输入使用时， 若内部上拉电阻使能，端口被外部电路拉低时将输出电流。

在复位过程中，即使系统时钟还未起振，端口A 处于高阻状态。

1MOSI SPI 总线的主机输出/ 从机输入信号PB6 8 位双向I/O 口2MISO SPI 总线的主机输入/ 从机输出信号PB7 8 位双向I/O 口3SCK SPI 总线的串行时钟4 RESET 复位输入引脚。

持续时间超过最小门限时间的低电平将引起系统复位。

5 VCC 数字电路的电源6 GND 地7 XTAL2 反向振荡放大器的输出端8 XTAL1 反向振荡放大器与片内时钟操作电路的输入端PD0 8 位双向I/O 口9RXD USART 输入引脚PD1 8 位双向I/O 口10TXD USART 输出引脚PD2 8 位双向I/O 口11INT0 外部中断0 的输入PD3 8 位双向I/O 口12INT1 外部中断1 的输入Atmega16寄存器PD4 8 位双向I/O 口13OC1B T/C1 输出比较B 匹配输出PD5 8 位双向I/O 口14OC1A T/C1 输出比较A 匹配输出PD6 8 位双向I/O 口15ICP1 T/C1 输入捕捉引脚PD7 8 位双向I/O 口16OC2 T/C2 输出比较匹配输出17 VCC 数字电路的电源18 GND 地PC0 8 位双向I/O 口19SCL 两线串行总线时钟线PC1 8 位双向I/O 口20SDA 两线串行总线数据输入/ 输出线PC2 8 位双向I/O 口21TCK JTAG 测试时钟PC3 8 位双向I/O 口22TMS JTAG 测试模式选择PC4 8 位双向I/O 口23TDO JTAG 测试数据输出PC5 8 位双向I/O 口24TDI JTAG 测试数据输入PC6 8 位双向I/O 口25TOSC1 定时振荡器引脚1PC7 8 位双向I/O 口26TOSC2 定时振荡器引脚227 AVCC 端口A与A/D转换器的电源。

ATmega16 主要特性如下：•高性能、低功耗的8位AVR微处理器•先进的RISC结构o 131条指令-大多数指令执行时间为单个时钟周期o 32个8位通用工作寄存器o全静态工作o 工作于16 MHz时性能高达16 MIPSo只需两个时钟周期的硬件乘法器*非易失性程序和数据存储器o 16K字节的系统内可编程Flash擦写寿命：10,000次o具有独立锁定位的可选Boot代码区通过片上Boot程序实现系统内编程真正的同时读写操作o 512 字节的EEPROM擦写寿命：100,000次o 1K字节的片内SRAMo可以对锁定位进行编程以实现用户程序的加密• JTAG 接口（与IEEE 1149.1 标准兼容）o符合JTAG标准的边界扫描功能o支持扩展的片内调试功能o 通过JTAG接口实现对Flash、EEPROM、熔丝位和锁定位的编程.外设特点o两个具有独立预分频器和比较器功能的8位定时器/计数器o 一个具有预分频器、比较功能和捕捉功能的16位定时器/计数器o具有独立振荡器的实时计数器RTCo 四通道PWMo 8 路10 位ADC8个单端通道TQFP封装的7个差分通道2个具有可编程增益（1x, 10x,或200x ）的差分通道o面向字节的两线接口o 两个可编程的串行USARTo可工作于主机/从机模式的SPI串行接口o具有独立片内振荡器的可编程看门狗定时器o片内模拟比较器•特殊的微控制器特点o上电复位以及可编程的掉电检测o片内经过标定的RC振荡器o片内/外中断源o 6种休眠模式：空闲模式、ADC噪声抑制模式、省电模式、掉电模式和待机模式以式* I/O和封装o 32个可编程的I/O 口 o 40引脚PDIP 封装,44引脚TQFP 封装,与44引脚MLF 封装 •工作电压： o ATmega16L : 2.7 - 5.5V o ATmega16 : 4.5 - 5.5V •速度等级o 0 - 8 MHz ATmega16L o 0 - 16 MHz ATmega16 ・ ATmega16 在 1 MHz, 3V, 25 C 时的功耗o 正常模式：1.1 mAo 空闲模式：0.35 mA o 掉电模式：< 1叭加二卍十二PB ：I L; PB F IWT2/AIN0) PB2 OC 沙1皆；PB3 焼：F'B< ：M0&i i P'B5 M 的］PM 严』D .2■二 4 2 芒曲九TAJ M 州阳 Kt ;m e rol PCIA) 2'' 3 4 £ 厂 □眈 ADSL ： □ AM ［ADC1) 二I FA2 ADCS 1 □ RM gDC 旳 □ PM MS □ F^5 ADCJ ： □吨 AD 26： □时［ADC7： □ AREF □ GhiD □ WCC □ pc ：厂力sea 3 PCS 】n □ PCS :'-Dr □ PC4 'DO 3 PCS T WS L □ PC2 TCK ： □ PC * SDA ： □ POD 'SCL! □ POT OC2-。

ATMEGA16开发板本系统包含内容：1、绘制电路板的原理图和pcb图2、下载软件使用中的一些问题3、基于NRF905模块的测试源代码说明：本系统由沧海一声笑原创。

博客地址：画了将近四天的时间做了一块atmega16的开发板，用覆铜板做的。

提供的接口有1602液晶，12864液晶，nrf905无线模块，SPI接口，串口。

同时12864兼容浩豚电子的TFT彩屏。

原理图如下：pcb图如下：说明：1、由于做的是覆铜板，pcb图中，max232附近的有两根线尚未接上。

2、由于个人疏忽，电源部分的ams117芯片管脚不对，可以不焊接进去，依然可以照常使用。

但是如果要焊接的话，须仔细比对原理图。

3、液晶的数据接口采用的是PORTC，jtag下载的相关接口就在其内，开始没注意，不论怎么写程序，测得的PORTC2,3,4,5管脚电压都是高电平。

这也是液晶测试程序仿真时正确，下载上去却无法正常工作的原因。

解决方法是，在下载的时候需对下载的软件进行设置熔丝位，把JTAGEN前面的钩钩去掉即可。

下面以SLISP为例：1）2）3）整整花了四天的时间。

1602的测试程序已经写好,如下：#define uchar unsigned char#define uint unsigned int#include<iom16v.h>#define RS 4#define RW 5#define EN 6#define PORT_CTL PORTA#define DDR_CTL DDRA#define DATA_PORT PORTC#define DATA_DDR DDRC#define DATA_PIN PINCvoid s_ms(uint ms){for(;ms>1;ms--);}//查忙void busy(void){uchar temp;s_ms(500);PORT_CTL&=~(1<<RS); //RS=0 s_ms(500);PORT_CTL|=(1<<RW); //RW=1 s_ms(500);while(temp){PORT_CTL|=(1<<EN); //EN=1s_ms(500);DATA_DDR=0x00; //A口变输入DATA_PORT =0xff; //上拉使能s_ms(500);temp =DATA_PIN&0x80; //读取A口 s_ms(500);DATA_DDR=0xff;DATA_PORT =0xff; //A口变输出 s_ms(500);PORT_CTL&=~(1<<EN); //EN=0s_ms(500);}}//写指令void writecom(uchar com){busy();s_ms(500);PORT_CTL&=~(1<<RS); //RS=0s_ms(500);PORT_CTL&=~(1<<RW); //RW=0 s_ms(500);PORT_CTL|=(1<<EN); //EN=1s_ms(500);DATA_PORT = com; //输出指令s_ms(500);PORT_CTL&=~(1<<EN); //EN=0 s_ms(500);}//1602初始化void LcdInit(void){writecom(0x38);s_ms(1000);writecom(0x01);s_ms(10000);s_ms(1000);s_ms(1000);s_ms(1000);s_ms(1000);s_ms(1000);s_ms(1000);writecom(0x02);s_ms(1000);writecom(0x06);s_ms(1000);writecom(0x0c);s_ms(1000);writecom(0x38);s_ms(1000);}//写数据void writedata(uchar data){busy();s_ms(500);PORT_CTL|=(1<<RS); //RS=1s_ms(500);PORT_CTL&=~(1<<RW); //RW=0 s_ms(500);PORT_CTL|=(1<<EN); //EN=1s_ms(500);DATA_PORT= data; //输出数据s_ms(500);PORT_CTL&=~(1<<EN); //EN=0 s_ms(500);}//读数据uchar readdata(void){uchar temp;busy();s_ms(500);PORT_CTL|=(1<<RS); //RS=1s_ms(500);PORT_CTL|=(1<<RW); //RW=1s_ms(500);PORT_CTL|=(1<<EN); //EN=1s_ms(500);DATA_DDR=0x00; //A端口变输入s_ms(500);temp = DATA_PIN; //读A端口s_ms(500);DATA_DDR=0xff; //A端口变输出s_ms(500);PORT_CTL&=~(1<<EN); //EN=0s_ms(500);return temp;}//================================================= // 描述：写LCD内部CGRAM函数// 入口：‘num’要写的数据个数// ‘pbuffer’要写的数据的首地址// 出口：无//================================================ void WriteCGRAM(uint num, const uint *pBuffer){uint i,t;writecom(0x40);PORT_CTL|=(1<<RS);PORT_CTL&=~(1<<RW);for(i=num;i!=0;i--){t = *pBuffer;PORT_CTL|=(1<<EN);DATA_PORT = t;PORT_CTL&=~(1<<EN);pBuffer++;}}//================================================= //描述：写菜单函数，本程序使用的LCD规格为16 * 2//入口：菜单数组首地址//出口：无//================================================= void WriteMenu(const uchar *pBuffer){uchar i,t;writecom(0x80); //数据地址PORT_CTL|=(1<<RS);PORT_CTL&=~(1<<RW);s_ms(50);for(i=0;i<16;i++){t = *pBuffer;DATA_PORT = t;PORT_CTL|=(1<<EN);s_ms(50);PORT_CTL&=~(1<<EN);pBuffer++;}writecom(0xC0);PORT_CTL|=(1<<RS);PORT_CTL&=~(1<<RW);s_ms(50);for(i=0;i<16;i++){t = *pBuffer;DATA_PORT = t;PORT_CTL|=(1<<EN);s_ms(50);PORT_CTL&=~(1<<EN);pBuffer++;}}//====================================================// 描述：在任意位置写数字函数// 入口：’row‘表示要写数字所在的行地址，只能为1或2// ’col‘表示要写数字所在的列地址，只能为0--15// ‘num’表示要写的数字，只能为0--9// 出口：无//===================================================void WriteNum(uchar row,uchar col,uchar num){if (row == 1) row = 0x80 + col;else row = 0xC0 + col;writecom(row);PORT_CTL|=(1<<RS);s_ms(500);PORT_CTL&=~(1<<RW);s_ms(500);DATA_PORT = num;s_ms(500);PORT_CTL|=(1<<EN);s_ms(500);PORT_CTL&=~(1<<EN);s_ms(500);}//================================================================ // 描述：在任意位置写任意多个字符// 入口：’row‘要写的字符所在的行，只能为1或2；// ‘col’要写的字符所在的列，只能为0---15// ‘num’要写字符的个数// ‘pbuffer’要写字符的首地址//================================================================== void WriteChar(uchar row,uchar col,uint num,uchar *pBuffer){uchar i,t;if (row == 1) row = 0x80 + col;else row = 0xC0 + col;writecom(row);PORT_CTL|=(1<<RS);s_ms(500);PORT_CTL&=~(1<<RW);s_ms(500);for(i=num;i!=0;i--){t = *pBuffer;s_ms(500);DATA_PORT = t;s_ms(500);PORT_CTL|=(1<<EN);s_ms(500);PORT_CTL&=~(1<<EN);s_ms(500);pBuffer++;}}uchar wz[]={""};uchar gd[]={"Good Luck!"};main(){DATA_DDR=0xff;DATA_PORT=0xff;DDR_CTL=0xff;PORT_CTL=0xff;LcdInit();while(1){WriteChar(1,1,13,wz);WriteChar(2,3,10,gd);}}NRF905无线模块双向计数测试程序：发送部分：/*注：发送部分的硬件电路是用以前做的16的最小系统版和数码管模块用杜邦线搭建的。

Features•High-performance, Low-power AVR® 8-bit Microcontroller •Advanced RISC Architecture–131 Powerful Instructions – Most Single-clock Cycle Execution –32 x 8 General Purpose Working Registers–Fully Static Operation–Up to 16 MIPS Throughput at 16 MHz–On-chip 2-cycle Multiplier•Nonvolatile Program and Data Memories–16K Bytes of In-System Self-Programmable FlashEndurance: 10,000 Write/Erase Cycles–Optional Boot Code Section with Independent Lock BitsIn-System Programming by On-chip Boot ProgramTrue Read-While-Write Operation–512 Bytes EEPROMEndurance: 100,000 Write/Erase Cycles–1K Byte Internal SRAM–Programming Lock for Software Security•JTAG (IEEE std. 1149.1 Compliant) Interface–Boundary-scan Capabilities According to the JTAG Standard–Extensive On-chip Debug Support–Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface •Peripheral Features–Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes–One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode–Real Time Counter with Separate Oscillator–Four PWM Channels–8-channel, 10-bit ADC8 Single-ended Channels7 Differential Channels in TQFP Package Only2 Differential Channels with Programmable Gain at 1x, 10x, or 200x–Byte-oriented Two-wire Serial Interface–Programmable Serial USART–Master/Slave SPI Serial Interface–Programmable Watchdog Timer with Separate On-chip Oscillator–On-chip Analog Comparator•Special Microcontroller Features–Power-on Reset and Programmable Brown-out Detection–Internal Calibrated RC Oscillator–External and Internal Interrupt Sources–Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby•I/O and Packages–32 Programmable I/O Lines–40-pin PDIP, 44-lead TQFP, and 44-pad MLF•Operating Voltages–2.7 - 5.5V for ATmega16L–4.5 - 5.5V for ATmega16•Speed Grades–0 - 8 MHz for ATmega16L–0 - 16 MHz for ATmega16•Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L–Active: 1.1 mA–Idle Mode: 0.35 mA–Power-down Mode: < 1 µA 8-bit Microcontrollerwith 16K BytesNote: This is a summary document. A complete document is available on our Web site at .2ATmega16(L)2466HS–AVR–12/03Pin ConfigurationsFigure 1. Pinouts ATmega16DisclaimerTypical values contained in this datasheet are based on simulations and characteriza-tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.3ATmega16(L)2466HS–AVR–12/03OverviewThe ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.Block DiagramFigure 2. Block Diagram4ATmega16(L)2466HS–AVR–12/03The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATmega16 provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only),a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchro-nous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high density nonvolatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Soft-ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications.The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.Pin DescriptionsVCC Digital supply voltage.GNDGround.Port A (PA7..PA0)Port A serves as the analog inputs to the A/D Converter.Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.5ATmega16(L)2466HS–AVR–12/03Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B also serves the functions of various special features of the ATmega16 as listed on page 56.Port C (PC7..PC0)Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti-vated even if a reset occurs.Port C also serves the functions of the JTAG interface and other special features of the ATmega16 as listed on page 59.Port D (PD7..PD0)Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port D also serves the functions of various special features of the ATmega16 as listed on page 61.RESETReset Input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 36. Shorter pulses are not guaranteed to generate a reset.XTAL1Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting Oscillator amplifier.AVCCAVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to V CC , even if the ADC is not used. If the ADC is used, it should be con-nected to V CC through a low-pass filter.AREFAREF is the analog reference pin for the A/D Converter.6ATmega16(L)2466HS–AVR–12/03Register Summary7ATmega16(L)2466HS–AVR–12/03Notes:1.When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug-ger specific documentation for details on how to use the OCDR Register.2.Refer to the USART description for details on how to access UBRRH and UCSRC.3.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.4.Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate onall bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.$01 ($21)TWSR TWS7TWS6TWS5TWS4TWS3–TWPS1TWPS0179$00 ($20)TWBRTwo-wire Serial Interface Bit Rate Register178AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page8ATmega16(L)2466HS–AVR–12/03Instruction Set SummaryMnemonicsOperandsDescriptionOperationFlags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two RegistersRd ← Rd + Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2SUB Rd, Rr Subtract two RegistersRd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2AND Rd, Rr Logical AND RegistersRd ← Rd • Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1OR Rd, Rr Logical OR RegistersRd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K)Z,N,V 1INC Rd Increment Rd ← Rd + 1Z,N,V 1DEC Rd DecrementRd ← Rd − 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← $FF None 1MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2MULS Rd, Rr Multiply SignedR1:R0 ← Rd x Rr Z,C 2MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1Z,C 2FMULS Rd, Rr Fractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C 2FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1Z,C 2BRANCH INSTRUCTIONSRJMP kRelative Jump PC ← PC + k + 1None 2IJMP Indirect Jump to (Z)PC ← ZNone 2JMP k Direct JumpPC ← kNone 3RCALL kRelative Subroutine Call PC ← PC + k + 1None 3ICALL Indirect Call to (Z)PC ← Z None 3CALL k Direct Subroutine Call PC ← kNone 4RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACKI 4CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1 / 2 / 3CP Rd,Rr CompareRd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with CarryRd − Rr − C Z, N,V,C,H 1CPI Rd,K Compare Register with Immediate Rd − KZ, N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1None 1 / 2BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1None 1 / 2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1 / 2BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1 / 2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1 / 2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1 / 2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1 / 2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1 / 2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1 / 2BRPL k Branch if Plusif (N = 0) then PC ← PC + k + 1None 1 / 2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1 / 2BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1 / 2BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1 / 2BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1 / 2BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1 / 2BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1 / 2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1 / 2BRVCk Branch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1 / 29ATmega16(L)2466HS–AVR–12/03BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1 / 2BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1None 1 / 2DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move Between Registers Rd ← RrNone 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:RrNone 1LDI Rd, K Load Immediate Rd ← KNone 1LD Rd, X Load IndirectRd ← (X)None 2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None 2LD Rd, - X Load Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None 2LD Rd, Y Load IndirectRd ← (Y)None 2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None 2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None 2LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None 2LD Rd, Z Load IndirectRd ← (Z)None 2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None 2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None 2LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q)None 2LDS Rd, k Load Direct from SRAM Rd ← (k)None 2ST X, Rr Store Indirect(X) ← RrNone 2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None 2ST - X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None 2ST Y, Rr Store Indirect(Y) ← RrNone 2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None 2ST - Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None 2STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2ST Z, Rr Store Indirect(Z) ← RrNone 2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None 2ST -Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None 2STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2STS k, RrStore Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z)None 3LPM Rd, Z Load Program MemoryRd ← (Z)None 3LPM Rd, Z+Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1None 3SPM Store Program Memory (Z) ← R1:R0None -IN Rd, P In Port Rd ← PNone 1OUT P, Rr Out PortP ← Rr None 1PUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd Pop Register from Stack Rd ← STACKNone 2BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ← 1None 2CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C ←Rd(7)Z,C,N,V 1ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C ←Rd(0)Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None 1BSET s Flag Set SREG(s) ← 1SREG(s)1BCLR s Flag ClearSREG(s) ← 0 SREG(s)1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, b Bit load from T to Register Rd(b) ← TNone 1SEC Set Carry C ← 1C 1CLC Clear Carry C ← 0C 1SEN Set Negative Flag N ← 1N 1CLN Clear Negative Flag N ← 0N 1SEZ Set Zero Flag Z ← 1Z 1CLZ Clear Zero Flag Z ← 0Z 1SEI Global Interrupt Enable I ← 1I 1CLI Global Interrupt Disable I ← 0I 1SES Set Signed Test Flag S ← 1S 1CLS Clear Signed Test FlagS ← 0S 1SEVSet Twos Complement Overflow.V ← 1V1CLVClear Twos Complement Overflow V ← 0 V1SET Set T in SREG T ← 1T 1CLT Clear T in SREG T ← 0 T 1SEH Set Half Carry Flag in SREG H ← 1H 1MnemonicsOperandsDescriptionOperationFlags#Clocks10ATmega16(L)2466HS–AVR–12/03CLHClear Half Carry Flag in SREG H ← 0H1MCU CONTROL INSTRUCTIONS NOP No Operation None 1SLEEP Sleep(see specific descr. for Sleep function)None 1WDR Watchdog Reset (see specific descr. for WDR/timer)None 1BREAKBreakFor On-Chip Debug OnlyNoneN/AMnemonics Operands DescriptionOperationFlags#Clocks11ATmega16(L)2466HS–AVR–12/0312ATmega16(L)2466HS–AVR–12/03Packaging Information44A13ATmega16(L)2466HS–AVR–12/0340P614ATmega16(L)2466HS–AVR–12/0344M115ATmega16(L)2466HS–AVR–12/03ErrataThe revision letter in this section refers to the revision of the ATmega16 device.ATmega16(L) Rev. I•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.ATmega16(L) Rev. H•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.ATmega16(L) Rev. G•IDCODE masks data from TDI input 1.IDCODE masks data from TDI inputThe JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.Problem Fix / Workaround –If A Tmega16 is the only device in the scan chain, the problem is not visible.–Select the Device ID Register of the A Tmega16 by issuing the IDCODE instruction or by entering the T est-Logic-Reset state of the T AP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYP ASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.16ATmega16(L)2466HS–AVR–12/03–If the Device IDs of all devices in the boundary scan chain must be captured simultaneously, the A Tmega16 must be the fist device in the chain.17ATmega16(L)2466HS–AVR–12/03Datasheet Change Log for ATmega16This section contains a log on the changes made to the datasheet for ATmega16.Changes from Rev. 2466G-10/03 to Rev. 2466H-12/03All page numbers refer to this document.1.Updated “Calibrated Internal RC Oscillator” on page 27.Changes from Rev. 2466F-02/03 to Rev. 2466G-10/03All page numbers refer to this document.1.Removed “Preliminary” from the datasheet.2.Changed ICP to ICP1 in the datasheet.3.Updated “JTAG Interface and On-chip Debug System” on page 34.4.Updated assembly and C code examples in “Watchdog Timer Control Regis-ter – WDTCR” on page 41.5.Updated Figure 46 on page 101.6.Updated Table 15 on page 36, Table 82 on page 215 and Table 115 on page274.7.Updated “Test Access Port – TAP” on page 220 regarding JTAGEN.8.Updated description for the JTD bit on page 229.9.Added note 2 to Figure 126 on page 251.10.Added a note regarding JTAGEN fuse to Table 105 on page 259.11.Updated Absolute Maximum Ratings* and DC Characteristics in “ElectricalCharacteristics” on page 289.12.Updated “ATmega16 Typical Characteristics” on page 297.13.Fixed typo for 16 MHz MLF package in “Ordering Information” on page 11.14.Added a proposal for solving problems regarding the JTAG instructionIDCODE in “Errata” on page 15.Changes from Rev. 2466E-10/02 to Rev. 2466F-02/03All page numbers refer to this document.1.Added note about masking out unused bits when reading the ProgramCounter in “Stack Pointer” on page 10.2.Added Chip Erase as a first step in “Programming the Flash” on page 286 and“Programming the EEPROM” on page 287.3.Added the section “Unconnected pins” on page 53.18ATmega16(L)2466HS–AVR–12/034.Added tips on how to disable the OCD system in “On-chip Debug System” onpage 34.5.Removed reference to the “Multi-purpose Oscillator” application note and“32kHz Crystal Oscillator” application note, which do not exist.6.Added information about PWM symmetry for Timer0 and Timer2.7.Added note in “Filling the Temporary Buffer (Page Loading)” on page 252about writing to the EEPROM during an SPM Page Load.8.Removed ADHSM completely.9.Added Table 73, “TWI Bit Rate Prescaler,” on page 180 to describe the TWPSbits in the “TWI Status Register – TWSR” on page 179.10.Added section “Default Clock Source” on page 23.11.Added note about frequency variation when using an external clock. Noteadded in “External Clock” on page 29. An extra row and a note added in Table 118 on page 291. 12.Various minor TWI corrections.13.Added “Power Consumption” data in “Features” on page 1.14.Added section “EEPROM Write During Power-down Sleep Mode” on page 20.15.Added note about Differential Mode with Auto Triggering in “Prescaling andConversion Timing” on page 205.16.Added updated “Packaging Information” on page 12.Changes from Rev. 2466D-09/02 to Rev. 2466E-10/02All page numbers refer to this document.1.Updated “DC Characteristics” on page 289.Changes from Rev. 2466C-03/02 to Rev. 2466D-09/02All page numbers refer to this document.1.Changed all Flash write/erase cycles from 1,000 to 10,000.2.Updated the following tables: Table 4 on page 24, Table 15 on page 36, Table42 on page 83, Table 45 on page 110, Table 46 on page 110, Table 59 on page 141, Table 67 on page 165, Table 90 on page 233, Table 102 on page 257, “DC Characteristics” on page 289, Table 119 on page 291, Table 121 on page 293,and Table 122 on page 295.3.Updated “Errata” on page 15.Changes from Rev. 2466B-09/01 to Rev. 2466C-03/02All page numbers refer to this document.1.Updated typical EEPROM programming time, Table 1 on page 18.19ATmega16(L)2466HS–AVR–12/032.Updated typical start-up time in the following tables:Table 3 on page 23, Table 5 on page 25, Table 6 on page 26, Table 8 on page 27,Table 9 on page 27, and Table 10 on page 28.3.Updated Table 17 on page 41 with typical WDT Time-out.4.Added Some Preliminary Test Limits and Characterization Data.Removed some of the TBD's in the following tables and pages:Table 15 on page 36, Table 16 on page 40, Table 116 on page 272 (table removed in document review #D), “Electrical Characteristics” on page 289, Table 119 on page 291, Table 121 on page 293, and Table 122 on page 295.5.Updated TWI Chapter.Added the note at the end of the “Bit Rate Generator Unit” on page 176.6.Corrected description of ADSC bit in “ADC Control and Status Register A –ADCSRA” on page 217.7.Improved description on how to do a polarity check of the ADC doff results in“ADC Conversion Result” on page 214.8.Added JTAG version number for rev. H in Table 87 on page 227.9.Added not regarding OCDEN Fuse below Table 105 on page 259.10.Updated Programming Figures:Figure 127 on page 261 and Figure 136 on page 272 are updated to also reflect that AVCC must be connected during Programming mode. Figure 131 on page 268added to illustrate how to program the fuses.11.Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 278and “PROG_PAGEREAD ($7)” on page 278.12.Removed alternative algortihm for leaving JTAG Programming mode.See “Leaving Programming Mode” on page 286.13.Added Calibrated RC Oscillator characterization curves in section “ATmega16Typical Characteristics” on page 297.14.Corrected ordering code for MLF package (16MHz) in “Ordering Information”on page 11.15.Corrected Table 90, “Scan Signals for the Oscillators (1)(2)(3),” on page 233.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. 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Atmega16实验板说明书硬件资料介绍 (2)调试软件安装 (3)编译环境的使用 (8)建立新的工程 (15)资料和例程 (18)注意：使用时先把调试器和开发板用数据线连起来，再插上USB线；停止使用时应先断开USB线切断电源，才能拔下数据线，否则可能会损坏调试器。

硬件资料介绍实验套件共分3部分，开发板，调试器，数据线（1根usb线，1根串口线）。

开发板文件夹图片/原理图里面有开发板的原理图图片和protel dxp 原理图文件。

如果开发板是没有焊好的套件可以对照元器件参数表和已焊好的图片（图片文件夹里有）先把开发板焊接完成。

焊接完成后先用万用表测量一下5V 与GND 之间是否短路，确定没有短路之后，插上USB 线接到电脑上，弹上开关SW1电源指示灯D1亮，说明电源已接通。

调试器调试软件安装要实现开发调试需要安装三个软件：PL2303驱动，avr studio 4，WinAVR。

这三个软件都在软件这个文件夹里。

首先安装usb驱动PL2303，如图点下一步。

点完成就可以了。

然后把调试器和电脑通过USB线联机。

如图这时调试器上的电源指示灯和信号指示灯都亮，而且电脑开始发现新硬件，新硬件可以安装使用。

这说明已经建立起连接，然后右击我的电脑—>属性—>硬件—>设备管理器，打开设备管理器界面，点开端口（COM和LPT）的“+”如图。

其中的Prolific usb-to-Serial Comm Port(COMx)就是调试器的usb设备。

端口号是多少根据个人电脑情况可能有差异。

下面我们要修改端口号，因为调试器里只提供COM1-COM3的通讯。

双击Prolific usb-to-Serial Comm Port(COMx)选项，弹出端口设置对话框，如图然后选端口设置—>高级，在端口号中选一个没有被占用且3以内的COM口，我的电脑上没有串口，我选的是COM1，如图然后点确定，重新打开设备管理器再看一下端口情况。