CDBF0140R-HF;中文规格书,Datasheet资料

FDMF8704 High Efficiency / High Frequency FET plus Driver Multi-chip ModulePowertrain Application Circuit5BOOT Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor.21, 40-50, C VSWH Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-thru protection.8, 9, 11-20, B VIN Power Input. Output stage supply voltage.10TEST PAD 1For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to any pin.22-38PGND Power ground. Output stage ground. Source pin of low side MOSFET(s).39TEST PAD 2For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to any pin.55DISB Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low). 56PWM PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.Control Circuit Supply Current I CC f SW = 0Hz, V DISB = 0V13mA f SW = 1MHz, V DISB = 5V50PWM Input High Voltage V IH(PWM) 2.4V PWM Input Low Voltage V IL(PWM)0.8V PWM Input Current I IL(PWM)-22µA DISB Input High Voltage V IHDISB) 2.4V DISB Input Low Voltage V IL(DISB)0.8V DISB Input Current I IL(DISB)-22µAPropagation Delay t PDL(DISB-LDRV)(2)V IN = 12V, V OUT = 1.3V,f sw = 1MHz, I O = 30A8ns t PDH(DISB-LDRV)(2)6ns t PDL(LDRV)(2)9ns t PDL(HDRV)(2)22ns t PDH(LDRV)(2)12ns t PDH(HDRV)(2)20nsNote 2: t PDL(LDRV/HRDV) refers to HIGH-to-LOW transition, t PDH(LDRV/HDRV) refers to LOW-to-HIGH transition.is held low.High-Side DriverThe high-side driver (HDRV) is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit, consisting of the external diode and external bootstrap capacitor (C BOOT). During start-up, VSWH is held at PGND, allowing C BOOT to charge to VCIN through the internal diode. When the PWM input goes high, HDRV will begin to charge the high-side MOSFET's gate (Q1). During this transition, charge is removed from C BOOT and delivered to Q1's gate. As Q1 turns on, VSWH rises to V IN, forcing the BOOT pin to V IN +V C(BOOT), which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling HDRV to VSWH. C BOOT is then recharged to VCIN when VSWH falls to PGND. HDRV output is in phase with the PWM input. When the driver is disabled, the high-side gate is held low.delay t PDH(HDRV). To preclude overlap during the high-to-low transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors the voltage at the SW pin. When the PWM signal goes LOW, Q1 will begin to turn OFF after some propagation delay (t PDL(HDRV)). Once the VSWH pin falls below ~2.2V, Q2 begins to turn ON after adaptive delay t PDH(LDRV). Additionally, V GS of Q1 is monitored. When V GS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, which results in Q2 being driven ON after t PDH(LDRV), regardless of SW state. This function is implemented to ensure C BOOT is recharged each switching cycle, particularly for cases where the power converter is sinking current and SW voltage does not fall below the 2.2V adaptive threshold. Secondary delay t PDH(HDRV) is longer than t PDH(LDRV).FDMF8704 High Efficiency / High Frequency FET plus Driver Multi-chip ModuleFDMF8704 High Efficiency / High Frequency FET plus Driver Multi-chip ModuleModule Power Loss Measurement and CalculationRefer to Figure 18 for module power loss testing method. Power loss calculation are as follows:(a) P IN = (V IN x I IN ) + (V CIN x I CIN ) (W)(b) P OUT = V O x I OUT (W)(c) P LOSS = P IN - P OUT (W)PCB Layout GuidelineFigure 19. shows a proper layout example of FDMF8704 and critical parts. All of high current flow path, such as V IN , VSWH,V OUT and GND copper, should be short and wide for better and stable current flow, heat radiation and system performance. Following is a guideline which the PCB designer should consider:1. Input bypass capacitors should be close to V IN and GND pin of FDMF8704 to help reduce input current ripple component induced by switching operation.2. It is critical that the VSWH copper has minimum area forlower switching noise emission. VSWH copper trace should also be wide enough for high current flow. Other signal routing path, such as PWM IN and BOOT signal, should be considered with care to avoid noise pickup from VSWH copper area.3. Output inductor location should be as close as possible to the FDMF8704 for lower power loss due to copper trace.4. Snubber for suppressing ringing and spiking of VSWH voltage should be placed near the FDMF8704. The resistor and capacitor need to be of proper size for power dissipation.5. Place boot diode, ceramic bypass capacitor and boot capacitor as close to V CIN and BOOT pin of FDMF8704 in order to supply stable power. Routing width and length should also be considered6. Use multiple Vias on each copper area to interconnect each top, inner and bottom layer to help smooth current flow and heat conduction. Vias should be relatively large and of reasonable inductance.DISBPWM CGNDPGNDVINVCIN VSWH DISB PWM InputC VCINV CINC BOOTC OUTV OUTV INC VINBOOT I INAI OUT AV V OI CIN A Figure 18. Power Loss Measurement Block DiagramFigure 19. Typical PCB Layout Example (Top View)HSENLFDMF8704 High Efficiency / High Frequency FET plus Driver Multi-chip Module分销商库存信息: FAIRCHILD FDMF8704。

SPECIFICATION FOR APPROVALCustomerDescription D C F A NPart No. R E V.Delta Model No.GFC0412DS-DF00 REV. 01 Sample Issue No.Sample Issue Date FEB.03.2009PLEASE SEND ONE COPY OF THIS SPECIFICAITONBACK AFTER YOU SIGNED APPROVAL FOR PRODUCTION PRE-ARRANGMENT.APPROVED BY:DATE :DELTA ELECTRONICS, INC.TAOYUAN PLANT252, SHANG YING ROAD, KUEI SAN INDUSTRIAL ZONE TAOYUAN SHIEN, TAIWAN, R.O.C.TEL:886-(0)3-3591968FAX:886-(0)3-3591991Application Notice1.Delta will not guarantee the performance of the products if the application conditionfalls outside the parameters set forth in the specification.2. A written request should be submitted to Delta prior to approval if deviation fromthis specification is required.3.Please exercise caution when handling fans. Damage may be caused when pressure isapplied to the impeller, if the fans are handled by the lead wires, or if the fan washard-dropped to the production floor.4.Except as pertains to some special designs, there is no guarantee that the products willbe free from any such safety problems or failures as caused by the introduction ofpowder, droplets of water or encroachment of insect into the hub.5.The above-mentioned conditions are representative of some unique examples and viewedas the first point of reference prior to all other information.6.I t is very important to establish the correct polarity before connecting the fan to thepower source. Positive (+) and Negative (-). Damage may be caused to the fans ifconnection is with reverse polarity, if there is no foolproof method to protect againstsuch error specifically mentioned in this spec.7.Delta fans without special protection are not suitable where any corrosive fluids areintroduced to their environment.8.Please ensure all fans are stored according to the storage temperature limits specified.Do not store fans in a high humidity environment. We highly recommend performance testing is conducted before shipping, if the fans have been stored over 6 months.9.Not all fans are provided with the Lock Rotor Protection feature. If you impair therotation of the impeller for the fans that do not have this function, the performanceof those fans will lead to failure.10. Please be cautious when mounting the fan. Incorrect mounting of fans may causeexcess resonance, vibration and subsequent noise.11.It is important to consider safety when testing the fans. A suitable fan guard should befitted to the fan to guard against any potential for personal injury.12.Except where specifically stated, all tests are carried out at room (ambient) temperature and relative humidity conditions of 25o C, 65% RH. The test value is only for fan performance itself.13.Be certain to connect an “ 4.7µF or greater” capacitor to the fan externally whenthe application calls for using multiple fans in parallel, to avoid any unstable power.Doc. No: FMBG-ES Form 001 Rev. 0001Date: June 24, 2009分销商库存信息: DELTA-PRODUCT-GROUPS GFC0412DS-DF00。