Allstot Bandwidth Extension Method

TCP拥塞控制算法理论及调优实践TCP（Transmission Control Protocol）是当前Internet上最重要的传输协议之一，其主要特点是提供了可靠的数据传输服务。

然而，在高负载情况下，TCP数据传输过程中容易出现拥塞现象，导致网络性能下降、数据丢失等问题。

因此，TCP拥塞控制算法成为网络性能优化中的重要一环。

TCP拥塞控制算法的原理TCP拥塞控制算法主要基于网络反馈机制实现，在网络出现拥塞时，TCP协议会相应地降低发送数据的速度，以此来缓解网络负载压力。

TCP拥塞控制算法主要包括四种基本算法：Slow Start、Congestion Avoidance、Fast Retransmit和Fast Recovery。

Slow Start算法是TCP拥塞控制算法中最基本的算法之一，其主要原理是当TCP协议开始发送数据时，先以一个较小的速率进行发送，逐渐递增发送速率，同时不断根据网络反馈调整发送速率，直到网络达到拥塞阈值时，TCP协议则根据反馈信息逐渐降低发送速率，以缓解网络拥塞压力。

Congestion Avoidance算法主要是在Slow Start算法的基础上进一步进行优化，其主要想法是当网络出现拥塞时，不仅仅是降低发送速率，同时也要通过降低拥塞窗口大小来减少拥塞现象的发生。

Fast Retransmit算法主要是当发送方在经过一段时间后始终没有收到确认数据包时，则会认为数据包已经丢失，此时会立即重发数据包以避免数据包过多地停留在网络中发生拥塞现象。

这种方式可以大大缩短丢包重传的时间，提高数据传输的时效性。

Fast Recovery算法主要是在Fast Retransmit中进一步进行优化，当收到重复的确认数据包时，TCP协议会认为数据包已经被正确接收，此时会立即完成重传操作并根据网络反馈情况以逐渐增加发送速率的方式来提高数据传输效率。

TCP拥塞控制算法的调优实践TCP拥塞控制算法的调优是一项非常复杂的工作，需要综合考虑网络拓扑结构、流量类型、网络负载情况等多个因素。

UTMI+ Low Pin Interface (ULPI)SpecificationRevision 1.1October 20, 2004Revision HistoryDate CommentRevision Issue0.9 November 12, 2003 Pre-release.1.0rc1 January 3, 2004 Introduce PHY interface “modes”.Update interface timings. Clarify 4-bit data clocking.Clarify sending of RX CMD’s and interrupts.Introduce AutoResume feature.Route int pin to data(3) during 6-pin Serial Mode.Explain VBUS thresholds.Add T&MT diagram and updated text.Add new section to explain how PHY is aborted by Link.Various clarifications.1.0rc2 January 13, 2004 Add block diagram.Tighten interface timing.Modify suspend protocol to more closely resemble UTMI.Add SPKR_L and SPKR_MIC to signal list and T&MTconnector.Various clarifications.1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset.Link + PHY clock startup time of no more than 5.6ms for aperipheral is now mandatory.PHY output delay reduced from 10ns to 9ns.Added link decision time numbers for low speed.Various Clarifications.1.0 February 2, 2004 1.0rc3 adopted as 1.0 release.1.1rc1 September 1, 2004 Various clarifications and fixes to hold time numbers, sendingRXCMDs, FsLsSerialMode, Vbus control and monitoring,Test_J and Tesk_K signalling, Low Power Mode,Hostdisconnect, ID detection, HS SOF packets, interrupts,Carkit Mode, interface protection, No SYNC/EOP mode,linestate filtering, and AutoResume.1.1rc2 October 4, 2004 Re-arranged text in section 3.8.7.3. Updated contributors list.1.1 October 20, 2004 1.1rc2 adopted as 1.1 release.The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification.iiPromotersARC International Inc.Conexant Systems, Inc.Mentor Graphics CorporationPhilipsSMSCTransDimension, Inc.ContributorsVertenten PhilipsBartOkur PhilipsBatuhanBillAnderson MotorolaMcInerney TransDimensionBillBooker CypressBrianARCBelangerChrisKolb ARCChrisChrisSchell PhilipsChung Wing Yan PhilipsSrokaPhilipsDaveWang PhilipsDavidWooten TransDimensionDavidSMSCEricKawamotoPhilipsMackayFarranFrazier ConexantFrankFredRoberts SynopsysFarooqConexantHassanLee TransDimensionHyunParr MentorIanStandiford TransDimensionJayPhilipsTjiaJeromeMentorSaundersMarkMohamed Benromdhane ConexantSMSCMorganMonksISINabilTaklaTengstrand ARCPeterRamanand Mandayam ConexantDouglas MentorRobSaleemMohamed Synopsys(Author)ShaunReemeyer PhilipsCypressSimonNguyenSubramanyam Sankaran PhilipsTexasInstrumentsViningSueRemple QualcommTerryChen ConexantTimothyConexantChangVincentQuestions should be emailed to lpcwg@.iiiTable of Contents1.Introduction (1)1.1General (1)1.2Naming Convention (1)1.3Acronyms and Terms (1)1.4References (1)2.Generic Low Pin Interface (2)2.1General (2)2.2Signals (2)2.3Protocol (3)2.3.1Bus Ownership (3)2.3.2Transferring Data (3)2.3.3Aborting Data (4)3.UTMI+ Low Pin Interface (5)3.1General (5)3.2Signals (6)3.3Block Diagram (7)3.4Modes (9)3.5Power On and Reset (10)3.6Interrupt Event Notification (10)3.7Timing (11)3.7.1Clock (11)3.7.2Control and Data (13)3.8Synchronous Mode (15)3.8.1ULPI Command Bytes (15)3.8.2USB Packets (18)3.8.3Register Operations (30)3.8.4Aborting ULPI Transfers (37)3.8.5USB Operations (39)3.8.6Vbus Power Control (internal and external) (52)3.8.7OTG Operations (52)3.9Low Power Mode (55)3.9.1Data Line Definition For Low Power Mode (55)3.9.2Entering Low Power Mode (55)3.9.3Exiting Low Power Mode (56)3.9.4False Resume Rejection (57)3.10Full Speed / Low Speed Serial Mode (Optional) (58)3.10.1Data Line Definition For FsLsSerialMode (58)3.10.2Entering FsLsSerialMode (59)3.10.3Exiting FsLsSerialMode (60)3.11Carkit Mode (Optional) (61)3.12Safeguarding PHY Input Signals (62)4.Registers (65)4.1Register Map (65)4.2Immediate Register Set (67)4.2.1Vendor ID and Product ID (67)4.2.2Function Control (68)4.2.3Interface Control (69)4.2.4OTG Control (71)4.2.5USB Interrupt Enable Rising (72)4.2.6USB Interrupt Enable Falling (73)4.2.7USB Interrupt Status (74)4.2.8USB Interrupt Latch (75)4.2.9Debug (76)4.2.10Scratch Register (76)4.2.11Carkit Control (77)4.2.12Carkit Interrupt Delay (77)iv4.2.13Carkit Interrupt Enable (78)4.2.14Carkit Interrupt Status (78)4.2.15Carkit Interrupt Latch (79)4.2.16Carkit Pulse Control (79)4.2.17Transmit Positive Width (80)4.2.18Transmit Negative Width (80)4.2.19Receive Polarity Recovery (80)4.2.20Reserved (81)4.2.21Access Extended Register Set (81)4.2.22Vendor-specific (81)4.3Extended Register Set (81)4.4Register Settings for all Upstream and Downstream signalling modes (81)5.T&MT Connector (83)5.1General (83)5.2Daughter-card (UUT) Specification (83)vFiguresFigure 1 – LPI generic data bus ownership (3)Figure 2 – LPI generic data transmit followed by data receive (3)Figure 3 – Link asserts stp to halt receive data (4)Figure 4 – Creating a ULPI system using wrappers (5)Figure 5 – Block diagram of ULPI PHY (7)Figure 6 – Jitter measurement planes (12)Figure 7 – ULPI timing diagram (13)Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface (14)Figure 9 – Sending of RX CMD (17)Figure 10 – USB data transmit (NOPID) (18)Figure 11 – USB data transmit (PID) (19)Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale) (20)Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale) (21)Figure 14 – USB receive while dir was previously low (22)Figure 15 – USB receive while dir was previously high (23)Figure 16 – USB receive error detected mid-packet (24)Figure 17 – USB receive error during the last byte (25)Figure 18 – USB HS, FS, and LS bit lengths with respect to clock (26)Figure 19 – HS transmit-to-transmit packet timing (29)Figure 20 – HS receive-to-transmit packet timing (29)Figure 21 – Register write (30)Figure 22 – Register read (31)Figure 23 – Register read or write aborted by USB receive during TX CMD byte (31)Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive (32)Figure 25 – USB receive in same cycle as register read data. USB receive is delayed (33)Figure 26 – Register read followed immediately by a USB receive (33)Figure 27 – Register write followed immediately by a USB receive during stp assertion (34)Figure 28 – Register read followed by a USB receive (34)Figure 29 – Extended register write (35)Figure 30 – Extended register read (35)Figure 31 – Extended register read aborted by USB receive during extended address cycle (36)Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit (37)Figure 33 – PHY aborted by Link asserting stp. Link performs register read (38)Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir (38)Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) (40)Figure 36 – Preamble sequence (D+/D- timing not to scale) (41)Figure 37 – LS Suspend and Resume (timing not to scale) (43)Figure 38 – FS Suspend and Resume (timing not to scale) (44)Figure 39 – HS Suspend and Resume (timing not to scale) (46)Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) (47)Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) (48)Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) (49)Figure 43 – Automatic resume signalling (timing not to scale) (50)Figure 44 – USB packet transmit when OpMode is set to 11b (51)Figure 45 – RX CMD V A_VBUS_VLD ≤Vbus indication source (54)Figure 46 – Entering low power mode (55)Figure 47 – Exiting low power mode when PHY provides output clock (56)Figure 48 – Exiting low power mode when Link provides input clock (56)Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts (57)Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts (57)Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down (59)Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered (59)Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running (60)Figure 54 – Interface behaviour when exiting Serial Mode and clock is running (60)Figure 55 – PHY interface protected when the clock is running (62)Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected (63)Figure 57 – PHY automatically exits Low Power Mode with interface protected (63)Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running (64)viFigure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) (64)Figure 60 – Recommended daughter-card configuration (not to scale) (83)viiTablesTable 1 – LPI generic interface signals (2)Table 2 – PHY interface signals (6)Table 3 – Mode summary (9)Table 4 – Clock timing parameters (11)Table 5 – ULPI interface timing (13)Table 6 – Transmit Command (TX CMD) byte format (15)Table 7 – Receive Command (RX CMD) byte format (16)Table 8 – USB specification inter-packet timings (26)Table 9 – PHY pipeline delays (27)Table 10 – Link decision times (28)Table 11 – OTG Control Register power control bits (52)Table 12 – Vbus comparator thresholds (52)Table 13 – RX CMD VbusValid over-current conditions (53)Table 14 – Vbus indicators in the RX CMD required for typical applications (54)Table 15 – Interface signal mapping during Low Power Mode (55)Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode (58)Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode (58)Table 18 – Carkit signal mapping (61)Table 19 – Register map (66)Table 20 – Register access legend (67)Table 21 – Vendor ID and Product ID register description (67)Table 22 – Function Control register (68)Table 23 – Interface Control register (70)Table 24 – OTG Control register (71)Table 25 – USB Interrupt Enable Rising register (72)Table 26 – USB Interrupt Enable Falling register (73)Table 27 – USB Interrupt Status register (74)Table 28 – USB Interrupt Latch register (75)Table 29 – Rules for setting Interrupt Latch register bits (75)Table 30 – Debug register (76)Table 31 – Scratch register (76)Table 32 – Carkit Control Register (77)Table 33 – Carkit Interrupt Delay register (77)Table 34 – Carkit Interrupt Enable register (78)Table 35 – Carkit Interrupt Status Register (78)Table 36 – Carkit Interrupt Latch register (79)Table 37 – Carkit Pulse Control (79)Table 38 – Transmit Positive Width (80)Table 39 – Transmit Negative Width (80)Table 40 – Receive Polarity Recovery (81)Table 41 – Upstream and downstream signalling modes (82)Table 42 – T&MT connector pin view (84)Table 43 – T&MT connector pin allocation (84)Table 44 – T&MT pin description (85)viii1. Introduction1.1 GeneralThis specification defines a generic PHY interface in Chapter 2.In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB transceiver implementations supporting On-The-Go, host, and peripheral application spaces.Convention1.2 NamingEmphasis is placed on normal descriptive text using underlined Arial font, e.g. must.Signal names are represented using the lowercase bold Arial font, e.g. clk.Registers are represented using initial caps, bold Arial font, e.g. OTG Control.Register bits are represented using initial caps, bold italic Arial font, e.g. USB Interrupt Enable Falling. 1.3 Acronyms and TermsA-device Device with a Standard-A or Mini-A plug inserted into its receptacleB-device Device with a Standard-B or Mini-B plug inserted into its receptacleDeviceDRD Dual-RoleFPGA Field Programmable Gate ArraySpeedFS FullHNP Host Negotiation ProtocolHS Hi-SpeedLink ASIC, SIE, or FPGA that connects to an ULPI transceiverLPI Low Pin InterfaceSpeedLS LowOTG On-The-GoPHY Physical Layer (Transceiver)PLL Phase Locked LoopSE0 Single Ended ZeroSIE Serial Interface EngineSRP Session Request ProtocolT&MT Transceiver and Macrocell TesterULPI UTMI+ Low Pin InterfaceUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InteraceUUT Unit Under Test1.4 References[Ref 1] Universal Serial Bus Specification, Revision 2.0[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a[Ref 3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, v1.05[Ref 4] UTMI+ Specification, Revision 1.0[Ref 5] CEA-2011, OTG Transceiver Specification[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification[Ref 7] USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.212. Generic Low Pin Interface2.1 GeneralThis section describes a generic low pin interface (LPI) between a Link and a PHY. Interface signals are defined and the basic communication protocol is described. The generic interface can be used as a common starting point for defining multiple application-specific interfaces.Chapter 3 defines the UTMI+ Low Pin Interface (ULPI), which is based on the generic interface described here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2.2.2 SignalsThe LPI transceiver interface signals are described in Table 1. The interface described here is generic, and can be used to transport many different data types. Depending on the application, the data stream can be used to transmit and receive packets, access a register set, generate interrupts, and even redefine the interface itself. All interface signals are synchronous when clock is toggling, and asynchronous when clock is not toggling. Data stream definition is application-specific and should be explicitly defined for each application space for inter-operability.Control signals dir, stp, and nxt are specified with the assumption that the PHY is the master of the data bus. If required, an implementation can define the Link as the master. If the Link is the master of the interface, the control signal direction and protocol must be reversed.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. Both directions are allowed. All interface signals are synchronous to clock.data I/O Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.dir OUT Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.stp IN Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link.nxt OUT Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume.Table 1 – LPI generic interface signals22.3 ProtocolOwnership2.3.1 BusThe PHY is the master of the LPI bi-directional data bus. Ownership of the data bus is determined by the dir signal from the PHY, as shown in Figure 1. When dir is low, the Link can drive data on the bus. When dir is high, the PHY can drive data on the bus. A change in dir causes a turnaround cycle on the bus during which, neither Link nor PHY can drive the bus. Data during the turnaround cycle is undefined and must be ignored by both Link and PHY.The dir signal can be used to directly control the data output buffers of both PHY and Link.Figure 1 – LPI generic data bus ownershipData2.3.2 TransferringAs shown in the first half of Figure 2, the Link continuously drives the data bus to 00h during idle. The Link transmits data to the PHY by driving a non-zero value on the data bus. To signal the end of data transmission, the Link asserts stp in the cycle following the last data byte.In the second half of Figure 2, the Link receives data when the PHY asserts dir. The PHY asserts dir only when it has data to send to the Link, and keeps dir low at all other times. The PHY drives data to the Link after the turnaround cycle.The nxt signal can be used by the PHY to throttle the data during transmit and receive. During transmit, nxt may be asserted in the same cycle that the Link asserts stp.Figure 2 – LPI generic data transmit followed by data receive2.3.3 AbortingDataThe PHY can assert dir to interrupt any data being transmitted by the Link. If the Link needs to interrupt data being received from the PHY, it asserts stp for one clock cycle, as shown in Figure 3. This causes the PHY to unconditionally1 de-assert dir and accept a complete data transmit from the Link. The PHY may re-assert dir again only when the data transmit from the Link has completed.Figure 3 – Link asserts stp to halt receive data1 The PHY will not de-assert dir if the ULPI interface is not usable. For example, if the internal PLL is not stable.3. UTMI+ Low Pin Interface3.1 GeneralThis section describes how any UTMI+ core can be wrapped to convert it to the smaller LPI interface. The generic interface described in chapter 2 is used as a starting point. This section always over-rides anything stated in chapter 2. While this specification details support of UTMI+ Level 3, PHY implementers may choose to support any of the Levels defined in UTMI+.ULPI defines a PHY to Link interface of 8 or 12 signals that allows a lower pin count option for connecting to an external transceiver that may be based on the UTMI+ specification. The pin count reduction is achieved by having relatively static UTMI+ signals be accessed through registers and by providing a bi-directional data bus that carries USB data and provides a means of accessing register data on the ULPI transceiver.This specification relies on concepts and terminology that are defined in the UTMI+ specification [Ref 4]. Specifically, if a ULPI PHY design is based on an internal UTMI+ core, then that core must implement the following UTMI+ features.Linestate must accurately reflect D+/D- to within 2-3 clocks. It is up to individual Link designers to use Linestate to time bus events.Filtering to prevent spurious SE0/SE1 states appearing on Linestate due to skew between D+ and D-. Filtering of 14 clock cycles is required in Low Speed, and 2 clock cycles in Full Speed and Hi-Speed modes.The PHY must internally block the USB receive path during transmit. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.TxReady must be used for all types of data transmitted, including Chirp.Due to noise on the USB, it is possible that RxActive asserts and then de-asserts without any valid data being received, and RxValid will not assert. The Link should operate normally with these data-less RxActive assertions.As shown in Figure 4, a PHY or Link based on this specification can be implemented as an almost transparent wrapper around existing UTMI+ IP cores, preserving the original UTMI+ packet timing, while reducing pin count and leaving all functionality intact. This should not be taken to imply that other implementations are not possible.Figure 4 – Creating a ULPI system using wrappers3.2 SignalsTable 2 describes the ULPI interface on the PHY. The PHY is always the master of the ULPI bus. USB and Miscellaneous signals may vary with each implementation and are given only as a guide to PHY designers.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. The PHY must be capable of providing a 60MHz output clock. Support for an input 60MHz clock is optional. If the PHY supports both clock directions, it must not use the ULPI control and data signals for setting the clock direction.Data bus. Driven to 00h by the Link when the ULPI bus is idle. Two bus widths are allowed:• 8-bit data timed on rising edge of clock.data I/O• (Optional) 4-bit data timed on rising and falling edges of clock.dir OUT Controls the direction of the data bus2. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PLL is not stable. This applies whether Link or PHY is the clock source.stp IN The Link must assert stp to signal the end of a USB transmit packet or a register write operation, and optionally to stop any receive. The stp signal must be asserted in the cycle after the last data byte is presented on the bus.nxt OUT The PHY asserts nxt to throttle all data types, except register read data and the RX CMD. Identical to RxValid during USB receive, and TxReady during USB transmit. The PHY also asserts nxt and dir simultaneously to indicate USB receive activity (RxActive), if dir was previously low. The PHY is not allowed to assert nxt during the first cycle of the TX CMD driven by the Link.USB InterfaceD+ I/O D+ pin of the USB cable. Required.D- I/O D- pin of the USB cable. Required.ID IN ID pin of the USB cable. Required for OTG-capable PHY’s.VBUS I/O V BUS pin of the USB cable. Required for OTG-capable PHY’s. Required for driving V BUS and the V BUS comparators.MiscellaneousXI IN Crystal input pin. Vendors should specify supported crystal frequencies. XO OUT Crystal output pin.C+ I/O Positive terminal of charge pump capacitor.C- I/O Negative terminal of charge pump capacitor.SPKR_L IN Optional Carkit left/mono speaker input signal.SPKR_MIC I/O Optional Carkit right speaker input or microphone output signal.RBIAS I/O Bias current resistor.Table 2 – PHY interface signals2 UTMI+ wrapper developers should note that data bus control has been reversed from UTMI to ensure that USB data reception is not interrupted by the Link.3.3 BlockDiagramAn example block diagram of a ULPI PHY is shown in Figure 5. This example is based on an internal UTMI+ Level 3 core [Ref 4], which can interface to peripheral, host, and On-The-Go Link cores. A description of each major block is given below.ULPI InterfaceUSBCableChargePumpCapacitor Figure 5 – Block diagram of ULPI PHYUTMI+ Level 3 PHY coreThe ULPI PHY may contain a core that is compliant to any UTMI+ level [Ref 4]. Signals for 16-bit data buses are not supported in ULPI. While Figure 5 shows the typical blocks for a Level 3 UTMI+ core, the PHY vendor must specify the intended UTMI+ level, and provide the functionality necessary for compliance to that level.ULPI PHY WrapperThe ULPI PHY wrapper of Figure 5 reduces the UTMI+ interface to the Low Pin Interface described in this document. All signals shown on the UTMI+ Level 3 PHY core are reduced to the ULPI interface signals clock, data, dir, stp, and nxt. The Register Map stores the relatively static signals of the UTMI+ interface. Crystal Oscillator and PLLWhen a crystal is attached to the PHY, the internal clock(s) and the external 60MHz interface clock are generated from the internal PLL. When no crystal is attached, the PHY may optionally generate the internal clock(s) from an input 60MHz clock provided by the Link.General BiasingInternal analog circuits require an accurate bias current. This is typically generated using an external, accurate reference resistor.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external VBUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external VBUS source is provided the PHY may optionally provide for a VBUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.Power-On-ResetA power-on-reset circuit must be provided in the PHY. When power is first applied to the PHY, the power-on-reset will reset all circuitry and leave the ULPI interface in a usable state.Carkit OptionThe PHY may optionally support Carkit Mode [Ref 6]. While in Carkit Mode, the PHY routes speaker and microphone signals between the Link and the USB cable. In carkit mono mode, SPKR_L inputs a mono speaker signal and SPKR_MIC outputs the microphone signal, MIC. In carkit stereo mode, SPKR_L inputs the left speaker signal, and SPKR_MIC inputs the right speaker signal, SPKR_R.3.4 ModesThe ULPI interface can operate in one of five independent modes listed in Table 3. The interface is in Synchronous Mode by default. Other modes are enabled by bits in the Function Control and Interface Control registers. In Synchronous Mode, the data bus carries commands and data. In other modes, the data pins are redefined with different functionality. Synchronous Mode and Low Power Mode are mandatory.Mode Name Mode DescriptionSynchronous Mode This is the normal mode of operation. The clock is running and is stablewith the characteristics defined in section 3.6. The ULPI interface carriescommands and data that are synchronous to clock.Low Power Mode The PHY is powered down with the clock stopped. The PHY keeps dirasserted, and the data bus is redefined to carry LineState and interrupts.See section 3.9 for more information.6-pin FS/LS Serial Mode (optional) The data bus is redefined to 6-pin serial mode, including 6 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. This mode is valid only for implementations with an 8-bit data bus. See section 3.10 for more information.3-pin FS/LS Serial Mode (optional) The data bus is redefined to 3-pin serial mode, including 3 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. See section 3.10 for more information.Carkit Mode (optional) The data bus is redefined to Carkit mode [Ref 6], including 2 pins for serial UART data, and 1 pin to signal interrupt events. The clock may optionally be stopped. See section 3.11 for more information.Table 3 – Mode summary。

IEX-402SeriesIndustrial managed VDSL2/SHDSL EthernetextendersFeatures and Benefits•Automatic CO/CPE negotiation reduces configuration time•Link Fault Pass-Through(LFPT)support and interoperable with Turbo Ringand Turbo Chain•LED indicators to simplify troubleshooting•Easy network management by web browser,Telnet/serial console,Windowsutility,ABC-01,and MXviewCertificationsIntroductionThe IEX-402is an entry-level industrial managed Ethernet extender designed with one10/100BaseT(X)and one DSL port.The Ethernet extender provides a point-to-point extension over twisted copper wires based on the G.SHDSL or VDSL2standard.The device supports data rates of up to 15.3Mbps and a long transmission distance of up to8km for G.SHDSL connection;for VDSL2connections,the data rate supports up to100Mbps and a long transmission distance of up to3km.The IEX-402Series is designed for use in harsh environments.The DIN-rail mount,wide operating temperature range(-40to75°C),and dual power inputs make it ideal for installation in industrial applications.To simplify configuration,the IEX-402uses CO/CPE auto-negotiation.By factory default,the device will automatically assign CPE status to one of each pair of IEX devices.In addition,Link Fault Pass-through(LFP)and network redundancy interoperability enhance the reliability and accessibility of communication networks.In addition,advanced managed and monitored functionality through MXview,including a virtual panel, improve the user experience for quick troubleshooting.Additional Features and Benefits•Standard G.SHDSL data rate up to5.7Mbps,with up to8km transmission distance(performance varies by cable quality)•Moxa proprietary Turbo Speed connections up to15.3Mbps •Supports Link Fault Pass-Through(LFP)and Line-swap fast recovery•Supports SNMP v1/v2c/v3for different levels of network management •Interoperable with Turbo Ring and Turbo Chain network redundancy •Support Modbus TCP protocol for device management and monitoring•Compatible with EtherNet/IP and PROFINET protocols for transparent transmission•IPv6ReadySpecificationsEthernet Interface10/100BaseT(X)Ports(RJ45connector)1Auto negotiation speedFull/Half duplex modeAuto MDI/MDI-X connectionCombo Port,RJ-11(RJ45connector)or Detachable2-Contact Terminal Block1Standards IEEE802.1p for Class of ServiceIEEE802.3for10BaseTIEEE802.3u for100BaseT(X)IEEE802.3x for flow controlIEX-402-VDSL2Series:ITU G.993.2for very high speed digital subscriber linetransceivers2IEX-402-SHDSL Series:ITU-T G.991.2for single-pair high-speed digital subscriber line(G.SHDSL)transceiversEthernet Software FeaturesManagement SNMPv1/v2c/v3,Modbus TCP,Back Pressure Flow Control,DHCP Client,HTTP,LLDP,Syslog,Telnet,TFTPMIB MIB-IITime Management SNTPSwitch PropertiesMAC Table Size1KPacket Buffer Size512kbitsLED InterfaceLED Indicators PWR1,PWR2,FAULT,STATE,LINK/ACT,CO/CPE,10/100(TP port)Serial InterfaceConsole Port RS-232(TxD,RxD,GND),10-pin RJ45(115200,n,8,1)DIP Switch ConfigurationEthernet Interface All models:CO/CPE,SNR/SPEEDIEX-402-VDSL2Series:STD/INPIEX-402-SHDSL Series:ANNEX B/ANNEX A,STD/TURBOPower ParametersPower Connector2removable2-contact terminal block(s)Input Voltage12/24/48VDC,9.6to60VDCInput Current IEX-402-SHDSL Series:0.388A@12VDC,0.196A@24VDC,0.097A@48VDCIEX-402-VDSL2Series:0.34A@24VDCOverload Current Protection SupportedReverse Polarity Protection SupportedPhysical CharacteristicsHousing MetalIP Rating IP30Dimensions35x130x105mm(1.38x5.12x4.13in)Weight IEX-402-SHDSL Series:290g(0.64lb)IEX-402-VDSL2Series:275g(0.61lb)Installation DIN-rail mounting,Rack mounting(with optional kit)Environmental LimitsAltitude2000m1Operating Temperature Standard Models:-10to60°C(14to140°F)Wide Temp.Models:-40to75°C(-40to167°F)Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)1.Please contact Moxa if you require products guaranteed to function properly at higher altitudes.Standards and CertificationsSafety UL508Hazardous Locations IEX-402-VDSL2Series:ATEX,Class I Division2EMC EN55032/24EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:6kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:10V/mIEC61000-4-4EFT:Power:2kVIEC61000-4-5Surge:Power:2kVIEC61000-4-6CS:150kHz to80MHz:10V/m;Signal:10V/mIEC61000-4-8PFMFTraffic Control IEX-402-VDSL2Series:NEMA TS2Railway EN50121-4Shock IEC60068-2-27Freefall IEC60068-2-32Vibration IEC60068-2-6MTBFTime IEX-402-SHDSL Series:1,311,455hrsIEX-402-VDSL2Series:1,498,312hrsStandards Telcordia(Bellcore),GBWarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x IEX-402Series switchCable1x RJ45-to-DB9console cableDocumentation1x document and software CD1x quick installation guide1x warranty card1x product certificates of quality inspection,Simplified Chinese1x product notice,Simplified ChineseDimensions Ordering InformationModel Name ITU G.993.2for veryhigh speed digitalsubscriber linetransceiversITU-T G.991.2forsingle-pair high-speeddigital subscriber line(G.SHDSL)transceivers10/100BaseT(X)PortsRJ45ConnectorCombo Port,RJ-11(RJ45connector)ordetachable2-contactterminalOperating Temp.IEX-402-VDSL2✓–11-10to60°CIEX-402-VDSL2-T✓–11-40to75°CIEX-402-SHDSL–✓11-10to60°CIEX-402-SHDSL-T–✓11-40to75°C Accessories(sold separately)SoftwareMXview Industrial network management software designed for converged automation networksStorage KitsABC-01Configuration backup and restoration tool for managed Ethernet switches and AWK Series wirelessAPs/bridges/clients,0to60°C operating temperaturePower SuppliesDR-120-24120W/2.5A DIN-rail24VDC power supply with universal88to132VAC or176to264VAC input byswitch,or248to370VDC input,-10to60°C operating temperatureDR-452445W/2A DIN-rail24VDC power supply with universal85to264VAC or120to370VDC input,-10to50°C operating temperatureDR-75-2475W/3.2A DIN-rail24VDC power supply with universal85to264VAC or120to370VDC input,-10to60°C operating temperatureMDR-40-24DIN-rail24VDC power supply with40W/1.7A,85to264VAC,or120to370VDC input,-20to70°Coperating temperatureMDR-60-24DIN-rail24VDC power supply with60W/2.5A,85to264VAC,or120to370VDC input,-20to70°Coperating temperatureWall-Mounting KitsWK-30Wall-mounting kit,2plates,4screws,40x30x1mmRack-Mounting KitsRK-4U19-inch rack-mounting kit©Moxa Inc.All rights reserved.Updated Nov12,2018.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。

CONNECTING TO THE GATEWAYPlease note that Multitech Conduit gateways supplied with the demo kit are pre-configured with Nodered for operation with the Demo Application. Please Review Multitech user guides for further information on setup and configuration if required.The gateway is supplied in the demo kit configured in DHCP Client mode and needs to be connected to Network work switch via an Ethernet patch cable to provide access to the internet.The Gateway Is powered via PoE injector supplied as part of the Demo Kits (only for IP67 Gateway).Demo Kit includes Multitech Conduit(LoRa Gateway) as shown belowLoRa ANTPowerMultitech ConduitGateway Ethernet Gateway to NetworkSwitch or Access PointIn order to configure the gateway the user should first connect a PC/Laptop to the gateway via a patch cable and power on the gateway, a standard patch cable should be used a cross over is not required.The default IP address on the Multitech gateway is 192.168.2.1, to connect to the gateway the user must first configure their computers Ip address to be within the same subnet range for example 192.168.2.10.Once this has been configured the user can login onto the gatewayvia their browser by typing in the IP address of the gateway as follows, https://192.168.2.1(MultiTech IP67 setupPOE setup: ‘’Out’’on POE injector connects to IP67, ‘’In’’connects to PC/ Switch/RouterDefault IP: 192.168.2.1On PC Ethernet net adapter setup as Obtained IP address automatically as IP67 serves as DHCP server by defaultConnect IP67 base station directly to PC and access settings from PC’s web browser by 192.168.2.1Initial setupFollow 1st time auto setup from web portalSpecify IP address according to local networkSpecify Gateway as IP of local gatewayPreferred DNS as IP of Local gatewaySecondary DNS as 8.8.8.8)On connection to the gateway the following screen will be displayed.The username is: adminThe password is: adminSETTING UP THE GATEWAYThe first step is to configure the IP settings of the gateway to those of the host network, click the setup tab.Select Network InterfacesClick the pencil icon under OptionsFill in the IP settings for the local network and click FinishNow Click Lora Network Server and enter the values as shown below. (Choose Channel Plan US915 for US gateway)The DCL EUI is: 5370656374726531The DCL Key is: 44434c20476174657761792030303031To complete setup, click finish in the Lora settings tab the click Save and Restart.The Gateway will reboot and save the applied settings.CONFIGURING THE FIREWALLIn order for the Gateway to communicate to the back office the following inbound ports must be opened in the firewall of the local router.Port 443, Port 1882These should be set to forward to the address that you have configured for the gateway.The following shows the settings for a gateway at IP address 192.168.0.51Please consult the literature for your router for the configuration required.INSTALLING NODE RED ON THE GATWAYThe Multitech gateway uses Node Red to configure and manage the flow of data across the network.To open Node Red on your gateway, first connect to the gateway then select the Apps tab and click on Node-Red.Node Red will open as per belowTo upload the Node-Red Script click the 3 line icon top right and select Import from clipboard.Copy and paste the script file.Click OKThe Nodes will be imported.To deploy the solution on the gateway click Deploy.The Gateway is now configured.SETTING MULTITECH GATEWAY UP FORREMOTE MANAGEMENTOn left side PanClick on AdministrationClick on Remote managementCheck EnabledCheck SSL EnabledEnter Server NameEnter Account KeyCheck in Interval: 240GPS Data Interval:720Check Allow Firmware UpgradeCheck Allow ConfigurationUpgradeCheck Allow Configuration Upload*Enter App Store URLClick on Check-in To Device-HQClick on SubmitServer Name: Account Key: FB2E21D5-5975-4231-89CB-6A8754A69C81App Store URL: https://。

idistributedcache 拓展方法全文共四篇示例，供读者参考第一篇示例：idistributedcache是.NET Core中用于在内存中存储缓存数据的接口，它提供了一种方式来管理应用程序中的缓存数据，提高应用程序的性能和响应速度。

通过idistributedcache，我们可以在应用程序中使用不同的缓存实现，例如内存缓存、Redis缓存、SQL Server缓存等。

然而，idistributedcache接口的默认功能是有限的，如果我们想要更加灵活和强大的缓存功能，可以通过拓展方法来扩展idistributedcache的功能。

在本文中，我们将讨论一些常用的idistributedcache拓展方法，并介绍如何在应用程序中使用这些方法。

一、获取缓存数据在默认的idistributedcache接口中，我们可以使用Get方法来获取缓存数据。

然而，通过拓展方法，我们可以实现更多功能，例如通过键名来获取缓存数据，同时支持泛型类型的数据。

下面是一个示例代码：public static T Get<T>(this IDistributedCache cache, string key){var data = cache.Get(key);if (data == null){return default(T);}return JsonSerializer.Deserialize<T>(data);}使用这个拓展方法，我们可以通过键名来获取泛型类型的缓存数据，而不需要手动进行序列化和反序列化的操作。

二、设置缓存数据除了获取缓存数据，设置缓存数据也是应用程序中经常需要的操作。

在默认的idistributedcache接口中，我们可以使用Set方法来设置缓存数据。

通过拓展方法，我们可以实现更多功能，例如设置缓存过期时间、支持泛型类型的数据等。

下面是一个示例代码：public static void Set<T>(this IDistributedCache cache, string key, T value, DistributedCacheEntryOptions options){var data = JsonSerializer.Serialize(value);cache.Set(key, Encoding.UTF8.GetBytes(data), options);}使用这个拓展方法，我们可以设置泛型类型的缓存数据，并指定缓存过期时间和其他缓存项的选项。

英特尔以太网万兆位服务器适配器高级驱动程序设置高级选项卡中的设置让您自定义适配器对QoS 数据包标签、巨帧、分载及其他功能的处理方法。

本页面不适用在其名称中带PRO/10GbE 的适配器。

用于这些适配器，可参阅英特尔® PRO/10GbE 服务器适配器的高级设置。

注意∙某些功能可能不一定可使用，这取决于操作系统和安装的特定适配器。

∙如果安装了英特尔® PROSet Windows 设备管理器版，“高级” 选项卡的布局和功能可用性会有所不同。

∙如果安装了英特尔® PROSet Windows 设备管理器版，便可使用屏幕帮助。

可用设置:流量控制标题数据分割中断节流中断节流率IPv4 校验和卸载巨帧数据包大量接收分载大型发送分载(IPv4)大型发送分载(IPv6)本地管理的地址记录链接状态事件低延迟中断分载TCP 分段优先级和VLAN接收缓冲区接收方调整接收方调整队列TCP 校验和分载(IPv4)TCP 校验和分载(IPv6)传输缓冲区UDP 校验和分载(IPv4)UDP 校验和分载(IPv6)流量控制使适配器能生成流量控制帧或对其作出响应，以帮助调节网络通信量。

流量控制在安装了Windows* 设备管理器英特尔® PROSet 的情况下在性能选项属性下配置。

如果传入帧到达速度超过设备对其处理的速度时，链接伙伴便会超载。

将会丢弃帧，直至超载情况结束。

流量控制机制能解决这种问题，防止丢失帧的情况发生。

如果发生过载的情况，设备会生成流量控制帧。

这会强制传输链接伙伴停止传输，然后尝试再次传输。

注意为使适配器能从此功能获益，链接伙伴必须支持流量控制帧。

Default已启用Rx 和Tx范围禁用: 无流量控制。

启用RX 和TX: 适配器生成流量控制帧并对其作出响应。

启用Rx : 适配器在从链接伙伴接收到流量控制帧时暂停传输。

启用Tx : 适配器在其接收队列达到预定义的限制时生成流量控制帧。

Wavedream NET Network Enhanced TransportOwner’s ManualWAVEDREAM NETOWNER’S MANUALTable of ContentsAbout this document (2)Package Contents (3)Safety Precautions (3)Functional Description (4)Powering UP (5)CD playback (5)Server playback (6)Setting internal storage (8)Setting Roon (8)Remote control function (12)Specification Sheet (13)ROCKNA AUDIO LIMITED WARRANTY (15)About this documentThis manual is aimed at the end user of the Rockna Wavedream NET. It contains an overview of the device’s internal architecture, specific handling details, functional description, safety precautions and product warranty details. This document is not meant for service or repair operations, as these must be carried out only by qualified personnel.More information regarding Rockna Audio and Audiobyte products can be found on-line at the websites owned and operated by the company:https://https://Rockna Electronics S.R.L.Address: Strada Plopului, nr. 5, SuceavaZIP Code: 720145, RomaniaPhone:+40 770 125 694 – General inquiresEmail:************************–Technicalsupport************************–GeneralinquirieThank you for choosing the Rockna Wavedream transport. The Wavedream NET was designed to give you countless hours of musical enjoyment.Package Contents-Wavedream NET-Supply cable-IR remote control-User manual-(Warranty Card)Safety Precautions1) This device is meant for indoor use only.2) Protect device from excessive heat, humidity and liquid filled objects, such as vases.3) Clean only with dry cloth.4) Do not remove product cover while the device is plugged in the mains outlet.5) Use earth grounded outlet if available.6) Do not move the device while operational.7) Lightning or static electricity can affect normal operation of the device. Make sure that it is unplugged during a thunderstorm.8) Make sure the unit is unplugged if it is not to be used for a long period of time.Functional DescriptionFront view:Legend:1.Power switch2.Menu key3.Disc/Server selection key4.Play/next (cd playback)5.Disc/stop (cd playback)6.CD DRIVE tray7.Display8.IR sensor (do not cover)Back view:The conenctors on the back panel are self-explanatory.Powering UPPlug in power cord and WDNET will start in CD mode (no need to use power button on the first time). To use the remote, make sure “CD” key was pressed. This setting is sticky unless other device is selected.Press “L” on remote to switch between CD mode and server mode or D/S key (3) from the front panel. Assuming the unit is left connected to mains, you can shut down/power up the unit normally after first boot. Note: When pressing power button for shut down, a lag of a few seconds is normal before unit display goes off. This is to allow server to properly shut down all services. Do not press the power button multiple times.CD playbackYou can use WDNET as regular cd transport. The unit accepts regular CD’s (redbook) as well wav (up to 384k sample rate) files if burned on a DVD disc (in UDF format).Besides looking as a regular CD transport, NET is actually a true memory player. This means you don’t hear the disc as it spins, but you hear the sound of a solid-state memory. As a funny exercise, try to press eject (disc) button while in play. The disc will be ejected but the music will continue to play for tens of seconds.Basic Operation:1.Press DISC (5) to open drawer in order to insert a cd2.Press DISC again or push gently the drawer.3.Press PLAY (4) for music.4.If unit is in play mode, pressing PLAY again will skip to next track.5.If unit is in play mode, pressing DISC key will stop playback.6.If playback is already stopped, pressing DISC will eject the media.e remote for regular playback functions like direct access, skip,repeat etc.Note : CD playack is completely separated from the server. Thereforeactive outputs are I2S 1&2, AES/EBU, SPDIF and BNC. The USB ports are not used in CD mode.Server playbackTo properly use WDNET server, make sure you connect the unit to your local network via LAN cable. The web interface of WDNET can be accessed on your browser at address wdnetXXXXXXX.local , where XXXXXXXX is your serial number (can be found on the back of the unit).General interfaceVia web interface all relevant settings are available : switching on and off installed services, ripping and network drive settings. For MPD and Airplay, a different output audio device can be set, when a external USB dac is attached. For Roon, this can be made through the Roon settings menu.Network drive settingsRipping tabNote: for ripping, a external usb optical drive is required (internal drive from WDNET is not connected to server).Setting internal storageIf your WDNET comes with internal storage, or is upgraded accordingly, the drive “WDNETXXXXXXXX/SATA” (X is your serial no.) will show as a network share in your network. This is the drive where you can copy your music.Setting up RoonWDNET is a full Roon server. A Roon remote app installation is required on your smartphone or tablet. Additionally, the server can be controlled from another Roon instance installed on your Mac or PC.First, you have to connect to the Roon core installed on WDNET. It will look like below:After connecting to the core, we have to select the folders where music is stored, you should press “add folder”:To set correctly the local storage, use a path like below:After this step, Roon will start to index your local music:Now, let’s set up the audio device. Press “Manage audio devices”. A screen like below will show up.Press “Enable” on WAVEDREAM NET (ROCKNA, ALSA). On playback tab from the next screen and change DSD playback strategy to “DSD over PCM 1.0 (DoP). Press “Save settings”.Now you can give a name to WDNET in the Roon network. You can type “WDNET” for example in the empty field.In the end, all you have to do is to select the defined audio zone and Roon is ready to go.Remote control functionSpecification SheetINPUTS•DISC PLAYBACK 32 bit – 384 KHz PCM, 1 bit – 11.28 MHz DSD;•ETHERNET 32 bit-384 KHz PCM, 1 bit – 5.6 MHz DSD;•USB 1 32 bit – 384 KHz PCM, 1 bit – 11.28 MHz DSD;•USB 2 32 bit – 384 KHz PCM, 1 bit – 11.28 MHz DSD. OUTPUTS•HD-Link 32 bit – 384 KHz PCM, 1 bit – 11.28 MHz DSD;•AES/EBU 24 bit – 384 KHz PCM, 1 bit – 5.6 MHz DoP;•S/PDIF 24 bit – 192 KHz PCM, 1 bit – 5.6 MHz DoP;•BNC 24 bit – 192 KHz PCM, 1 bit – 5.6 MHz DoP;•VGA 1920×1080 max. resolution.General•Disc playback: CD audio, DSD & WAV files from Blu-Ray and DVD disc;•NETWORK playback: all usual files, PCM & DSD;•LOCAL STORAGE PLAYBACK: ALL USUAL FILES, PCM & DSD•PCM 44.1K-384K, DSD64-DSD256;•Local storage (ssd only): 1,2,4 or 8TB.System updateIn NET webpage you can check the right bottom corner – you can find the current software version. Press check for updates link to see if your unit is up to date.ROCKNA AUDIO LIMITED WARRANTYThree (3) YearsWARRANTY COVERAGE:ROCKNA AUDIO warranty obligation is limited to the terms set forth below.WHO IS COVERED:Rockna Audio warrants the product to the original purchaser or the person receiving the product as a gift against defects in materials and workmanship as based on the date of original purchase from an Authorized Dealer. The original sales receipt showing the product name and the purchase date from an authorized retailer is considered such proof. WHAT IS COVERED:The Rockna Audio warranty covers new products if a defect arises and a valid claim is received by Rockna Audio within the Warranty Period. At its option, Rockna Audio will either (1)repair the product at no charge, using new or refurbished replacement parts, or (2)exchange the product with a product that is new or which has been manufactured from new, or serviceable used parts and is at least functionally equivalent or most comparable to the original product in Rockna Audio current inventory, or (3)refund the original purchase price of the product. Rockna Audio warrants replacement products or parts provided under this warranty against defects in materials and workmanship from the date of the replacement or repair for one(1) year or for the remaining portion of the original product’s warranty, whichever provides longer coverage for you. When a product or part is exchanged, any replacement item becomes your property and the replaced item becomes Rockna Audio’s property. When a refund is given, your product becomes Rockna Audio’s property. Note: Any product sold and identified as refurbished or renewed carries a one(1) year limited warranty. Replacement product can only be sent if all warranty requirements are met. Failure to follow all requirements can result in delay.WHAT IS NOT COVERED - EXCLUSIONS AND LIMITATIONS:This Limited Warranty applies only to the new products manufactured by or for Rockna Audio that can be identified by the trade-mark, trade name, or logo affixed to it. This Limited Warranty does not apply to any non-Rockna Audio hardware product or any firmware, even if packaged or sold with the product. Non-Rockna Audio manufacturers, suppliers, or publishers may provide a separate warranty for their own products packaged with the bundled product. Rockna Audio is not liable for any damage to or loss of any programs, data, or other information stored on any media contained within the product, or any non-Rockna Audio product or part not covered by this warranty. Recovery or reinstallation of programs, data or other information is not covered under this Limited Warranty.This warranty does not apply (a)to damage caused by accident, abuse, misuse, misapplication, or non-Rockna Audio product, (b)to damage caused by service performed by anyone other than Rockna Audio or Rockna Audio Authorized Service Location, (c)to a product or a part that has been modified without the written permission of Rockna Audio, or (d)if any Rockna Audio serial number has been removed or defaced, or (e) product,accessories or consumables sold “AS IS” without warranty of any kind by including refurbished Rockna Audio product sold “AS IS” by some retailers.This Limited Warranty does not cover:• Shipping charges to return defective product to Rockna Audio.• Labor charges for installation or setup of the product, adjustment of customer controls on the product, and installation or repair of systems outside of the product.• Product repair and/or part replacement because of improper installation, connections to improper voltage supply, abuse, neglect, misuse, accident, unauthorized repair or other cause not within the control of Rockna Audio. • Damage or claims for products not being available for use, or for lost data or lost firmware.• Damage occurring to product during shipping.• A product that requires modification or adaptation to enable it to operate in any country other than the country for which it was designed, manufactured, approved and/or authorized, or repair of products damaged by these modifications.• A product used for commercial or institutional purposes(including but not limited to rental purposes).• Product lost in shipment and no signature verification receipt can be provided.• Failure to operate as per Owner’s Manual.REPAIR OR REPLACEMENT AS PROVIDED UNDER THIS WARRANTY IS THE EXCLUSIVE REMEDY FOR THE CONSUMER. ROCKNA AUDIO SHALL NOT BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR BREACH OF ANY EXPRESS OR IMPLIED WARRANTY ON THIS PRODUCT. EXCEPT TO THE EXTENT PROHIBITED BY APPLICABLE LAW, ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ON THIS PRODUCT IS LIMITED IN DURATION TO THE DURATION OF THIS WARRANTY.Some states do not allow the exclusions or limitation of incidental or consequential damages, or allow limitations on how long an implied warranty lasts, so the above limitations or exclusions may not apply to you.Page | 17©Rockna Electronics S.R.L., Suceava, Romania。