(完整版)数字信号处理英文文献及翻译

Signal processingSignal processing is an area of electrical engineering and applied mathematics that deals with operations on or analysis of signals, in either discrete or continuous time, to perform useful operations on those signals. Signals of interest can include sound, images, time-varying measurement values and sensor data, for example biological data such as electrocardiograms, control system signals, telecommunication transmission signals such as radio signals, and many others. Signals are analog or digital electrical representations of time-varying or spatial-varying physical quantities. In the context of signal processing, arbitrary binary data streams and on-off signalling are not considered as signals, but only analog and digital signals that are representations of analog physical quantities.HistoryAccording to Alan V. Oppenheim and Ronald W. Schafer, the principles of signal processing can be found in the classical numerical analysis techniques of the 17th century. They further state that the "digitalization" or digital refinement of these techniques can be found in the digital control systems of the 1940s and 1950s.[2]Categories of signal processingAnalog signal processingAnalog signal processing is for signals that have not been digitized, as in classical radio, telephone, radar, and television systems. This involves linear electronic circuits such as passive filters, active filters, additive mixers, integrators and delay lines. It also involves non-linear circuits such ascompandors, multiplicators (frequency mixers and voltage-controlled amplifiers), voltage-controlled filters, voltage-controlled oscillators andphase-locked loops.Discrete time signal processingDiscrete time signal processing is for sampled signals that are considered as defined only at discrete points in time, and as such are quantized in time, but not in magnitude.Analog discrete-time signal processing is a technology based on electronic devices such as sample and hold circuits, analog time-division multiplexers, analog delay lines and analog feedback shift registers. This technology was a predecessor of digital signal processing (see below), and is still used in advanced processing of gigahertz signals.The concept of discrete-time signal processing also refers to a theoretical discipline that establishes a mathematical basis for digital signal processing, without taking quantization error into consideration.Digital signal processingDigital signal processing is for signals that have been digitized. Processing is done by general-purpose computers or by digital circuits such as ASICs, field-programmable gate arrays or specialized digital signal processors (DSP chips). Typical arithmetical operations include fixed-point and floating-point, real-valued and complex-valued, multiplication and addition. Other typical operations supported by the hardware are circular buffers and look-up tables. Examples of algorithms are the Fast Fourier transform (FFT), finite impulseresponse (FIR) filter, Infinite impulse response (IIR) filter, and adaptive filters such as the Wiener and Kalman filters1.Digital signal processingDigital signal processing (DSP) is concerned with the representation of signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing. DSP includes subfields like: audio and speech signal processing, sonar and radar signal processing, sensor array processing, spectral estimation, statistical signal processing, digital image processing, signal processing for communications, control of systems, biomedical signal processing, seismic data processing, etc.The goal of DSP is usually to measure, filter and/or compress continuousreal-world analog signals. The first step is usually to convert the signal from an analog to a digital form, by sampling it using an analog-to-digital converter (ADC), which turns the analog signal into a stream of numbers. However, often, the required output signal is another analog output signal, which requires a digital-to-analog converter (DAC). Even if this process is more complex than analog processing and has a discrete value range, the application of computational power to digital signal processing allows for many advantages over analog processing in many applications, such as error detection and correction in transmission as well as data compression.[1]DSP algorithms have long been run on standard computers, on specialized processors called digital signal processors (DSPs), or on purpose-built hardware such as application-specific integrated circuit (ASICs). Today thereare additional technologies used for digital signal processing including more powerful general purpose microprocessors, field-programmable gate arrays (FPGAs), digital signal controllers (mostly for industrial apps such as motor control), and stream processors, among others.[2]2. DSP domainsIn DSP, engineers usually study digital signals in one of the following domains: time domain (one-dimensional signals), spatial domain (multidimensional signals), frequency domain, autocorrelation domain, and wavelet domains. They choose the domain in which to process a signal by making an informed guess (or by trying different possibilities) as to which domain best represents the essential characteristics of the signal. A sequence of samples from a measuring device produces a time or spatial domain representation, whereas a discrete Fourier transform produces the frequency domain information, that is the frequency spectrum. Autocorrelation is defined as the cross-correlation of the signal with itself over varying intervals of time or space.3. Signal samplingMain article: Sampling (signal processing)With the increasing use of computers the usage of and need for digital signal processing has increased. In order to use an analog signal on a computer it must be digitized with an analog-to-digital converter. Sampling is usually carried out in two stages, discretization and quantization. In the discretization stage, the space of signals is partitioned into equivalence classes and quantization is carried out by replacing the signal with representative signal of the corresponding equivalence class. In the quantization stage the representative signal values are approximated by values from a finite set.The Nyquist–Shannon sampling theorem states that a signal can be exactly reconstructed from its samples if the sampling frequency is greater than twice the highest frequency of the signal; but requires an infinite number of samples . In practice, the sampling frequency is often significantly more than twice that required by the signal's limited bandwidth.A digital-to-analog converter is used to convert the digital signal back to analog. The use of a digital computer is a key ingredient in digital control systems. 4. Time and space domainsMain article: Time domainThe most common processing approach in the time or space domain is enhancement of the input signal through a method called filtering. Digital filtering generally consists of some linear transformation of a number of surrounding samples around the current sample of the input or output signal. There are various ways to characterize filters; for example:• A "linear" filter is a linear transformation of input samples; other filters are "non-linear". Linear filters satisfy the superposition condition, i.e. if an input is a weighted linear combination of different signals, the output is an equally weighted linear combination of the corresponding output signals.• A "causal" filter uses only previous samples of the input or output signals; while a "non-causal" filter uses future input samples. A non-causal filter can usually be changed into a causal filter by adding a delay to it.• A "time-invariant" filter has constant properties over time; other filters such as adaptive filters change in time.•Some filters are "stable", others are "unstable". A stable filter produces an output that converges to a constant value with time, or remains bounded within a finite interval. An unstable filter can produce an output that grows without bounds, with bounded or even zero input.• A "finite impulse response" (FIR) filter uses only the input signals, while an "infinite impulse response" filter (IIR) uses both the input signal and previous samples ofthe output signal. FIR filters are always stable, while IIR filters may be unstable.Filters can be represented by block diagrams which can then be used to derive a sample processing algorithm to implement the filter using hardware instructions. A filter may also be described as a difference equation, a collection of zeroes and poles or, if it is an FIR filter, an impulse response or step response.The output of a digital filter to any given input may be calculated by convolving the input signal with the impulse response.5. Frequency domainMain article: Frequency domainSignals are converted from time or space domain to the frequency domain usually through the Fourier transform. The Fourier transform converts the signal information to a magnitude and phase component of each frequency. Often the Fourier transform is converted to the power spectrum, which is the magnitude of each frequency component squared.The most common purpose for analysis of signals in the frequency domain is analysis of signal properties. The engineer can study the spectrum todetermine which frequencies are present in the input signal and which are missing.In addition to frequency information, phase information is often needed. This can be obtained from the Fourier transform. With some applications, how the phase varies with frequency can be a significant consideration.Filtering, particularly in non-realtime work can also be achieved by converting to the frequency domain, applying the filter and then converting back to the time domain. This is a fast, O(n log n) operation, and can give essentially any filter shape including excellent approximations to brickwall filters.There are some commonly used frequency domain transformations. For example, the cepstrum converts a signal to the frequency domain through Fourier transform, takes the logarithm, then applies another Fourier transform. This emphasizes the frequency components with smaller magnitude while retaining the order of magnitudes of frequency components.Frequency domain analysis is also called spectrum- or spectral analysis.6. Z-domain analysisWhereas analog filters are usually analysed on the s-plane; digital filters are analysed on the z-plane or z-domain in terms of z-transforms.Most filters can be described in Z-domain (a complex number superset of the frequency domain) by their transfer functions. A filter may be analysed in the z-domain by its characteristic collection of zeroes and poles.7. ApplicationsThe main applications of DSP are audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications, RADAR, SONAR, seismology, and biomedicine. Specific examples are speech compression and transmission in digital mobile phones, room matching equalization of sound in Hifi and sound reinforcement applications, weather forecasting, economic forecasting, seismic data processing, analysis and control of industrial processes, computer-generated animations in movies, medical imaging such as CAT scans and MRI, MP3 compression, image manipulation, high fidelity loudspeaker crossovers and equalization, and audio effects for use with electric guitar amplifiers8. ImplementationDigital signal processing is often implemented using specialised microprocessors such as the DSP56000, the TMS320, or the SHARC. These often process data using fixed-point arithmetic, although some versions are available which use floating point arithmetic and are more powerful. For faster applications FPGAs[3] might be used. Beginning in 2007, multicore implementations of DSPs have started to emerge from companies including Freescale and Stream Processors, Inc. For faster applications with vast usage, ASICs might be designed specifically. For slow applications, a traditional slower processor such as a microcontroller may be adequate. Also a growing number of DSP applications are now being implemented on Embedded Systems using powerful PCs with a Multi-core processor.（翻译）信号处理信号处理是电气工程与应用数学领域，在离散的或连续时间域处理和分析信号，以对这些信号进行所需的有用的处理。

数字信号处理一、导论数字信号处理（DSP）是由一系列的数字或符号来表示这些信号的处理的过程的。

数字信号处理与模拟信号处理属于信号处理领域。

DSP包括子域的音频和语音信号处理，雷达和声纳信号处理，传感器阵列处理，谱估计，统计信号处理，数字图像处理，通信信号处理，生物医学信号处理，地震数据处理等。

由于DSP的目标通常是对连续的真实世界的模拟信号进行测量或滤波，第一步通常是通过使用一个模拟到数字的转换器将信号从模拟信号转化到数字信号。

通常，所需的输出信号却是一个模拟输出信号，因此这就需要一个数字到模拟的转换器。

即使这个过程比模拟处理更复杂的和而且具有离散值，由于数字信号处理的错误检测和校正不易受噪声影响，它的稳定性使得它优于许多模拟信号处理的应用（虽然不是全部）。

DSP算法一直是运行在标准的计算机，被称为数字信号处理器（DSP）的专用处理器或在专用硬件如特殊应用集成电路（ASIC）。

目前有用于数字信号处理的附加技术包括更强大的通用微处理器，现场可编程门阵列（FPGA），数字信号控制器（大多为工业应用，如电机控制）和流处理器和其他相关技术。

在数字信号处理过程中，工程师通常研究数字信号的以下领域：时间域（一维信号），空间域（多维信号），频率域，域和小波域的自相关。

他们选择在哪个领域过程中的一个信号，做一个明智的猜测（或通过尝试不同的可能性）作为该域的最佳代表的信号的本质特征。

从测量装置对样品序列产生一个时间或空间域表示，而离散傅立叶变换产生的频谱的频率域信息。

自相关的定义是互相关的信号本身在不同时间间隔的时间或空间的相关情况。

二、信号采样随着计算机的应用越来越多地使用，数字信号处理的需要也增加了。

为了在计算机上使用一个模拟信号的计算机，它上面必须使用模拟到数字的转换器（ADC）使其数字化。

采样通常分两阶段进行，离散化和量化。

在离散化阶段，信号的空间被划分成等价类和量化是通过一组有限的具有代表性的信号值来代替信号近似值。

信号处理中英文对照外文翻译文献（文档含英文原文和中文翻译）译文：一小波研究的意义与背景在实际应用中，针对不同性质的信号和干扰，寻找最佳的处理方法降低噪声，一直是信号处理领域广泛讨论的重要问题。

目前有很多方法可用于信号降噪，如中值滤波，低通滤波，傅立叶变换等，但它们都滤掉了信号细节中的有用部分。

传统的信号去噪方法以信号的平稳性为前提，仅从时域或频域分别给出统计平均结果。

根据有效信号的时域或频域特性去除噪声，而不能同时兼顾信号在时域和频域的局部和全貌。

更多的实践证明，经典的方法基于傅里叶变换的滤波，并不能对非平稳信号进行有效的分析和处理，去噪效果已不能很好地满足工程应用发展的要求。

常用的硬阈值法则和软阈值法则采用设置高频小波系数为零的方法从信号中滤除噪声。

实践证明，这些小波阈值去噪方法具有近似优化特性，在非平稳信号领域中具有良好表现。

小波理论是在傅立叶变换和短时傅立叶变换的基础上发展起来的，它具有多分辨分析的特点，在时域和频域上都具有表征信号局部特征的能力，是信号时频分析的优良工具。

小波变换具有多分辨性、时频局部化特性及计算的快速性等属性，这使得小波变换在地球物理领域有着广泛的应用。

随着技术的发展，小波包分析 (Wavelet Packet Analysis) 方法产生并发展起来，小波包分析是小波分析的拓展，具有十分广泛的应用价值。

它能够为信号提供一种更加精细的分析方法，它将频带进行多层次划分，对离散小波变换没有细分的高频部分进一步分析，并能够根据被分析信号的特征，自适应选择相应的频带，使之与信号匹配，从而提高了时频分辨率。

小波包分析 (wavelet packet analysis) 能够为信号提供一种更加精细的分析方法，它将频带进行多层次划分，对小波分析没有细分的高频部分进一步分解，并能够根据被分析信号的特征，自适应地选择相应频带 , 使之与信号频谱相匹配，因而小波包具有更广泛的应用价值。

利用小波包分析进行信号降噪，一种直观而有效的小波包去噪方法就是直接对小波包分解系数取阈值，选择相关的滤波因子，利用保留下来的系数进行信号的重构，最终达到降噪的目的。

英文原文The simulation and the realization of the digital filterWith the information age and the advent of the digital world, digital signal processing has become one of today's most important disciplines and door technology. Digital signal processing in communications, voice, images, automatic control, radar, military, aerospace, medical and household appliances, and many other fields widely applied. In the digital signal processing applications, the digital filter is important and has been widely applied.1、 figures Unit on :Analog and digital filtersIn signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range.The following block diagram illustrates the basic idea.There are two main kinds of filter, analog and digital. They are quitedifferent in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equalisers in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. Adigital filter uses a digital processor to perform numerical calculations on sampled values of the signal. The processor may be a general-purpose computersuch as a PC, or a specialised DSP (Digital Signal Processor) chip. The analog input signal must first be sampled and digitised using an ADC (analog todigital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to theprocessor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form.Note that in a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current.The following diagram shows the basic setup of such a system.Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y.According to figures filter function 24-hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIRfilters have the advantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables mayfacilitate simple. It is the shortcomings of the nonlinear phase; Linear phase if required, will use the entire network phase-correction. Image processing and transmission of data collection is required with linear phase filters identity. And FIR linear phase digital filter to achieve, but an arbitrary margincharacteristics. Impact from the digital filter response of the units can be divided into two broad categories : the impact of the limited response (FIR) filters, and unlimited number ofshocks to (IIR) digital filters.FIR filters can be strictly linear phase, but because the system FIR filter function extremity fixed at the original point, it can only use the higher number of bands to achieve their high selectivity for the same filter design indicators FIR filter called band than a few high-IIR 5-10 times, the cost is higher, Signal delay is also larger. But if the same linear phase, IIR filters must be network-wide calibration phase, the same section also increase the number of filters and network complexity. FIR filters can be used to achieve non-Digui way, not in a limited precision of a shock, and into the homes and quantitative factors of uncertainty arising from the impact of errors than IIR filter small number, and FIR filter can be used FFT algorithms, the computational speed. But unlike IIR filter can filter through the simulation results, there is no ready-made formula FIR filter must use computer-aided design software (such as MATLAB) to calculate. So, a broader application of FIR filters, and IIR filters are not very strict requirements on occasions.Unit from sub-functions can be divided into the following four categories :(1) Low-filter (LPF);(2) high-filter (HPF);(3) belt-filter (BPF);(4) to prevent filter (BSF).The following chart dotted line for the ideals of the filter frequency characteristics :A1(f) A2(f)10 c2f c2 f(a) (b)A3(f) A4(f)0 c1c2f c1c2 f(c) (d)(a)LPF (b)HPF (c)BPF (d)BSF2、 MATLAB introducedMATLAB is a matrix laboratory (Matrix Laboratory) is intended. In addition to an excellent value calculation capability, it also provides professional symbols terms, word processing, visualization modeling, simulation and real-time control functions. MATLAB as the world's top mathematical software applications, with a strong engineering computing, algorithms research, engineering drawings, applications development, data analysis and dynamic simulation, and other functions, in aerospace, mechanical manufacturing and construction fields playing an increasingly important role. And the C language function rich, the use of flexibility, high-efficiency goals procedures. High language both advantages as well as low level language features. Therefore, C language is the most widely used programming language. Although MATLAB is a complete, fully functional programming environment, but in some cases, data and procedures with the external environment of the world is very necessary and useful. Filter design using Matlab, could be adjusted with the design requirements and filter characteristics of the parameters, visual simple, greatly reducing the workload for the filter design optimization.In the electricity system protection and secondary computer control, many signal processing and analysis are based on are certain types Yeroskipou and the second harmonics of the system voltage and current signals (especially at D process), are mixed with a variety of complex components, the filter has been installed power system during the critical components. Current computer protection and the introduction of two digital signal processing software main filter. Digital filter design using traditional cumbersome formula, the need to change the parameters after recalculation, especially in high filters, filter design workload. Uses MATLAB signal processing boxes can achieve rapid and effective digital filter design and simulation.MATLAB is the basic unit of data matrix, with its directives Biaodashi mathematics, engineering, commonly used form is very similar, it is used to solve a problem than in MATLAB C, Fortran and other languages End precision much the same thing. The popular MATLAB 5.3/Simulink3.0 including hundreds of internal function with the main pack and 30 types of tool kits (Toolbox). kits can be divided into functional tool kits and disciplines toolkit. MATLAB tool kit used to expand the functional symbols terms, visualization simulation modelling, word processing and real-time control functions. professional disciplines toolkit is a stronger tool kits, tool kits control, signal processing tool kit, tool kits, etc. belonging to such communicationsMATLAB users to open widely welcomed. In addition to the internal function, all the packages MATLAB tool kits are readable document and the document could be amended, modified or users through Yuanchengxu the construction of new procedures to prepare themselves for kits.3、 Digital filter designDigital filter design of the basic requirementsDigital filter design must go through three steps :(1) Identification of indicators : In the design of a filter, there must be some indicators. These indicators should be determined on the basis of the application. In many practical applications, digital filters are often used to achieve the frequency operation. Therefore, indicators in the form of general jurisdiction given frequency range and phase response. Margins key indicators given in two ways. The first is absolute indicators. It provides a function to respond to the demands of the general application of FIR filter design. The second indicator is the relative indicators. Its value in the form of answers to decibels. In engineering practice, the most popular of such indicators. For phase response indicators forms, usually in the hope that the system with a linear phase frequency bands human. Using linear phase filter design with thefollowing response to the indicators strengths：①it only contains a few algorithms, no plural operations；②there is delay distortion, only a fixed amount of delay; ③the filter length N (number of bands for N-1), the volume calculation for N/2 magnitude.(2) Model approach : Once identified indicators can use a previous study of the basic principles and relationships, a filter model to be closer to the target system.(3) Achieved : the results of the above two filters, usually by differential equations, system function or pulse response to describe. According to this description of hardware or software used to achieve it.4、 Introduced FPGA Programmable logic device is a generic logic can use a variety of chips, which is to achieve ASIC ASIC (Application Specific Integrated Circuit) semi-customized device, Its emergence and development of electronic systems designers use CAD tools to design their own laboratory in the ASIC device. Especially FPGA (Field Programmable Gate Array) generated and development, as a microprocessor, memory, the figures for electronic system design and set a new industry standard (that is based on standard product sales catalogue in the market to buy). Is a digital system for microprocessors, memories, FPGA or three standard building blocks constitute their integration direction.Digital circuit design using FPGA devices, can not only simplify the design process and can reduce the size and cost of the entire system, increasing system reliability. They do not need to spend the traditional sense a lot of time and effort required to create integrated circuits, to avoid the investment risk and become the fastest-growing industries of electronic devices group. Digital circuit design system FPGA devices using the following main advantages (1) Design flexibleUse FPGA devices may not in the standard series device logic functional limitations. And changes in system design and the use of logic in any one stage of the process, and only through the use of re-programming the FPGA device can be completed, the system design provides for great flexibility.(2) Increased functional densityFunctional density in a given space refers to the number of functional integration logic. Programmable logic chip components doors several high, a FPGA can replace several films, film scores or even hundreds of small-scale digital IC chip illustrated in the film. FPGA devices using the chip to use digital systems in small numbers, thus reducing the number of chips used to reduce the number of printed size and printed, and will ultimately lead to a reduction in the overall size of the system.(3) Improve reliabilityPrinting plates and reduce the number of chips, not only can reduce system size, but it greatly enhanced system reliability. A higher degree ofintegration than systems in many low-standard integration components for the design of the same system, with much higher reliability. FPGA device used to reduce the number of chips required to achieve the system in the number printed on the cord and joints are reduced, the reliability of the system can be improved.(4) Shortening the design cycleAs FPGA devices and the programmable flexibility, use it to design a system for longer than traditional methods greatly shortened. FPGA device master degrees high, use printed circuit layout wiring simple. At the same time, success in the prototype design, the development of advanced tools, a high degree of automation, their logic is very simple changes quickly. Therefore, the use of FPGA devices can significantly shorten the design cycle system, and speed up the pace of product into the market, improving product competitiveness.(5) Work fastFPGA/CPLD devices work fast, generally can reach several original Hertz, far larger than the DSP device. At the same time, the use of FPGA devices, the system needed to achieve circuitclasses and small, and thus the pace of work of the entire system will be improved.(6) Increased system performance confidentialityMany FPGA devices have encryption functions in the system widely used FPGA devices can effectively prevent illegal copying products were others(7) To reduce costsFPGA device used to achieve digital system design, if only device itself into the price, sometimes you would not know it advantages, but there are many factors affecting the cost of the system, taken together, the cost advantages of using FPGA is obvious. First, the use of FPGA devices designed to facilitate change, shorten design cycles, reduce development costs for system development; Secondly, the size and FPGA devices allow automation needs plug-ins, reducing the manufacturing system to lower costs; Again, the use of FPGA devices can enhance system reliability, reduced maintenance workload, thereby lowering the cost of maintenance services for the system. In short, the use of FPGA devices for system design to save costs.FPGA design principles :FPGA design an important guiding principles : the balance and size and speed of exchange, the principles behind the design of the filter expression of a large number of certification.Here, "area" means a design exertion FPGA/CPLD logic resources of the FPGA can be used to the typical consumption (FF) and the search table (IUT) to measuremore general measure can be used to design logic equivalence occupied by the door is measured. "pace" means stability operations in the chip design can achieve the highest frequency, the frequency of the time series design situation, and design to meet the clock cycle -- PADto pad, Clock Setup Time, Clock Hold Beijing, Clock-to-Output Delay, and other characteristics of many time series closely related. Area (area) and speed (speed) runs through the two targets FPGA design always is the ultimate design quality evaluation criteria. On the size and speed of the two basic concepts : balance of size and speed and size and speed of swap.One pair of size and speed is the unity of opposites contradictions body. Requirements for the design of a design while the smallest, highest frequency of operation is unrealistic. More scientific goal should be to meet the design requirements of the design time series (includes requirements for the design frequency) premise, the smallest chip area occupied. Or in the specified area, the design time series cushion greater frequency run higher. This fully embodies the goals of both size and speed balanced thinking. On the size and speed requirements should not be simply interpreted as raising the level and design engineers perfect sexual pursuit, and should recognize that they are products and the quality and cost of direct relevance. If time series cushion larger design, running relatively high frequency, that the design Jianzhuangxing stronger, more quality assurance system as a whole; On the other hand, the smaller size of consumption design is meant to achieve in chip unit more functional modules, the chip needs fewer, the entire system has been significantly reduced cost. As a contradiction of the two components, the size and speed is not the same status. In contrast, meet the timetables and work is more important for some frequency when both conflicts, the use of priority guidelines.Area and the exchange rate is an important FPGA design ideas. Theoretically, if a design time series cushion larger, can run much higher than the frequency design requirements, then we can through the use of functional modules toreduce the consumption of the entire chip design area, which is used for space savings advantages of speed; Conversely, if the design of a time series demanding, less than ordinary methods of design frequency then generally flow through the string and data conversion, parallel reproduction of operational module, designed to take on the whole "string and conversion" and operate in the export module to chip in the data "and string conversion" from the macro point of view the whole chip meets the requirements of processing speed, which is equivalent to the area of reproduction - rate increase.For example. Assuming that the digital signal processing system is 350Mb/s input data flow rate, and in FPGA design, data processing modules for maximum processing speed of 150Mb/s, because the data throughput processing module failed to meet requirements, it is impossible to achieve directly in the FPGA. Such circumstances, they should use "area-velocity" thinking, at least three processing modules from the first data sets will be imported and converted, and then use these three modules parallel processing of data distribution, then the results "and string conversion," we have complete data rate requirements. We look at both ends of the processing modules, data rate is 350Mb/s, and in view of the internal FPGA, each sub-module handles the data rate is 150Mb/s, in fact, all the data throughput is dependent on three security modules parallel processing subsidiary completed, that is used by more chip area achieve high-speed processing through "the area of reproduction for processing speed enhancement" and achieved design.FPGA is the English abbreviation Field of Programmable Gate Array for the site programmable gate array, which is in Pal, Gal, Epld, programmable device basis to further develop the product. It is as ASIC (ASIC) in the field of a semi-customized circuit and the emergence of both a customized solution to the shortage circuit, but overcome the original programmable devices doors circuit few limited shortcomings.FPGA logic module array adopted home (Logic Cell Array), a new concept of internal logic modules may include CLB (Configurable Logic Block), export import module IOB (Input Output Block) and internal links (Interconnect) 3. FPGA basic features are :(1) Using FPGA ASIC design ASIC using FPGA circuits, the chip can be used,while users do not need to vote films production.(2) FPGA do other customized or semi-customized ASIC circuits throughout the Chinese specimen films.3) FPGA internal capability and rich I/O Yinjue.4) FPGA is the ASIC design cycle, the shortest circuit, the lowest development costs, risks among the smallest device5) FPGA using high-speed Chmos crafts, low consumption, with CMOS, TTL low-power compatibleIt can be said that the FPGA chip is for small-scale systems to improve system integration, reliability one of the bestCurrently FPGA many varieties, the Revenue software series, TI companies TPC series, the fiex ALTERA company series FPGA is stored in films from theinternal RAM procedures for the establishment of the state of its work, therefore, need to programmed the internal Ram. Depending on the different configuration, users can use a different programming methodsPlus electricity, FPGA, EPROM chips will be read into the film, programming RAM 中 data, configuration is completed, FPGA into working order. Diaodian, FPGA resume into white films, the internal logic of relations disappear, FPGA to repeated use. FPGA's programming is dedicated FPGA programming tool, using generic EPROM, prom programming device can. When the need to modify functional FPGA, EPROM can only change is. Thus, with a FPGA, different programming datato produce different circuit functions. Therefore, the use of FPGA very flexible.There are a variety of FPGA model : the main model for a parallel FPGA plus a EPROM manner; From the model can support a number of films FPGA; serial prom programming model could be used serial prom FPGA programming FPGA; The external model can be engineered as microprocessors from its programming microprocessors.Verilog HDL is a hardware description language for the algorithm level, doors at the level of abstract level to switch-level digital system design modelling. Modelling of the target figure by the complexity of the system can be something simple doors and integrity of electronic digital systems. Digital system to the levels described, and in the same manner described in Hin-time series modelling.Verilog HDL language with the following description of capacity : design behaviour characteristics, design data flow characteristics, composition and structure designed to control and contain the transmission and waveform design a certification mechanism. All this with the use of a modelling language. In addition, Verilog HDL language programming language interface provided by the interface in simulation, design certification from the external design of the visit, including specific simulation control and operation.Verilog HDL language grammar is not only a definition, but the definition of each grammar structure are clear simulation, simulation exercises. Therefore, the use of such language to use Verilog simulation models prepared by a certification. From the C programming language, the language inherited multiple operating sites and structures. Verilog HDL provides modelling capacity expansion, many of the initial expansion would be difficult to understand. However, the core subsets of Verilog HDL language very easy to learn and use, which is sufficient for most modelling applications. Of course, the integrityof the hardware description language is the most complex chips from theintegrity of the electronic systems described.historyVerilog HDL language initially in 1983 by Gateway Design Automation companies for product development simulator hardware modelling language. Then it is only a dedicated language. Since their simulation, simulation devices widely used products, Verilog HDL as a user-friendly and practical language for many designers gradually accepted. In an effort to increase the popularity of the language activities, Verilog HDL language in 1990 was a public area. Open Verilog International (OVI) is to promote the development of Verilog international organizations. 1992, decided to promote OVI OVI standards as IEEE Verilog standards. The effort will ultimately succeed, a IEEE1995 Verilog language standard, known as IEEE Std 1364-1995. Integrity standards in Verilog hardware description language reference manual contains a detailed description.Main capacity：Listed below are the main Verilog hardware description language ability*Basic logic gate, and, for example, or have embedded in the language and nand * Users of the original definition of the term (UDP), the flexibility. Users can be defined in the original language combinations logic original language, the original language of logic could also be time series* Switches class infrastructure models, such as the nmos and pmos also be embedded in the language* Hin-language structure designated for the cost of printing the design and trails Shi Shi and design time series checks.* Available three different ways to design or mixed mode modelling. These methods include : acts described ways - use process of structural modelling; Data flow approach - use of a modelling approach Fuzhi expression; Structured way - using examples of words to describe modular doors and modelling.* Verilog HDL has two types of data : data types and sequence data line network types. Line network types that the physical links between components and sequence types that abstract data storage components.* To describe the level design, the structure can be used to describe any level module example * Design size can be arbitrary; Language is design size (size) impose any restrictions* Verilog HDL is no longer the exclusive language of certain companies but IEEE standards. * And the machine can read Verilog language, it may as EDA tools and languages of the world between the designers* Verilog HDL language to describe capacity through the use of programming language interface (PLI) mechanism further expansion. PLI is to allow external functions of the visit Verilog module information, allowing designers and simulator world Licheng assembly* Design to be described at a number of levels, from the switch level, doors level, register transfer level (RTL) to the algorithm level, including thelevel of process and content* To use embedded switching level of the original language in class switch design integrity modelling* Same language can be used to generate simulated incentive and certification by the designated testing conditions, such as the value of imports of the designated*Verilog HDL simulation to monitor the implementation of certification, the certification process of implementing the simulation can be designed to monitorand demonstrate value. These values can be used to compare with the expectations that are not matched in the case of print news reports.* Acts described in the class, not only in the RTL level Verilog HDL design description, and to describe their level architecture design algorithm level behavioural description* Examples can use doors and modular structure of language in a class structure described* Verilog HDL mixed mode modelling capabilities in the design of a different design in each module can level modelling* Verilog HDL has built-in logic function, such as*Structure of high-level programming languages, such as conditions of expression, and the cycle of expression language, language can be used* To it and can display regular modelling* Provide a powerful document literacy* Language in the specific circumstances of non-certainty that in the simulator, different models can produce different results; For example, describing events in the standard sequence of events is not defined.5、In troduction of DSPToday, DSP is w idely used in the modern techno logy and it has been the key part of many p roducts and p layed more and mo re impo rtant ro le in our daily life.Recent ly, Northw estern Po lytechnica lUniversity Aviation Microelect ronic Center has comp leted the design of digital signal signal p rocesso r co re NDSP25, w h ich is aim ing at TM S320C25 digital signal p rocesso r of Texas Inst rument TM S320 series. By using top 2dow n design flow , NDSP25 is compat ible w ith inst ruct ion and interface t im ing of TM S320C25.Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital signal processors Lane. Digital signal processing is a cover many disciplines applied to many areas and disciplines, refers to the use of computers or specialized processing equipment, the signals in digital form for the collection, conversion, recovery, valuation, enhancement, compression, identification, processing, the signals are compliant form. Digital signal processors for digital signal processing devices, it is accompanied by a digital signal processing to produce. DSP development process is broadly divided into three phases : the 20th century to the 1970s theorythat the 1980s and 1990s for the development of products. Before the emergence of the digital signal processing in the DSP can only rely on microprocessors (MPU) to complete. However, the advantage of lower high-speed real-time processing can not meet the requirements. Therefore, until the 1970s, a talent made based DSP theory and algorithms. With LSI technology development in 1982 was the first recipient of the world gave birth to the DSP chip. Years later, the second generation based on CMOS工艺 DSP chips have emerged. The late1980s, the advent of the third generation of DSP chips. DSP is the fastest-growing 1990s, there have been four successive five-generation and the generation DSP devices. After 20 years of development, the application of DSP products has been extended to people's learning, work and all aspects of life and gradually become electronics products determinants.中文翻译。

1。

"In most cases, these signals originate as sensory data from the real world：seismic vibrations visual images， sound waves， etc。

DSP isthe mathematics，the algorithms, and the techniques used to manipulate these signals after they have been converted into a digital form.”在大多数情况下，这些信号来源于人对真实世界的感觉，比如地震的震动，视觉图像,声音波形等。

数字信号处理是一种数学工具,是一种用来处理那些将上述信号转换成数字形式后的信号的算法和技术.2.Fourier’s representation of functionsas a superposition of sines and cosines has become Ubiquitous for both the analytic and numerical solution of differential equations and for the analysis and treatment of communication signals 函数的傅里叶表示,即将函数表示成正弦和余弦信号的叠加，这种方法已经广泛用于微分方程的解析法和数值法求解过程以及通信信号的分析和处理。

3。

If f （t ） is a nonperiodic signal, the summation of the periodic functions ,such as sine and cosine, does not accurately represent the signal. You couldartificially extend thesignal to make it periodicbut it would requireadditional continuity at the endpoints . 如果f(t)是非周期信号，那么用周期函数例如正弦和余弦的和，并不能精确的表示该信号f(t).你可以人为的拓展这个信号使其具有周期性，但是这要求在端点处附加连续性4。

文献翻译TMS320LF2407, TMS320LF2406, TMS320LF2402TMS320LC2406, TMS320LC2404, MS320LC2402DSP CONTROLLERSThe TMS320LF240x and TMS320LC240x devices, new members of the ‘24x family of digital signal processor (DSP) controllers, are part of the C2000 platform of fixed-point DSPs. The ‘240x devices offer the enhanced TMS320 architectural design of the ‘C2xx core CPU for low-cost, low-power, high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single chip DSP controller. While code-compatible with the existing ‘24x DSP controller devices, the ‘240x offers increased processing performance (30 MIPS) and a higher level of peripheral integration. See the TMS320x240x device summary section for device-specific features.The ‘240x family offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash-based devices of up to 32K words offer a reprogrammable solution useful for: Applications requiring field programmability upgrades.Development and initial prototyping of applications that migrate to ROM-based devices.Flash devices and corresponding ROM devices are fully pin-to-pin compatible. Note that flash-based devices contain a 256-word boot ROM to facilitate in-circuit programming.All ‘240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include centered- and/or edge-aligned PWM generation, programmabledeadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single ‗240x DSP controller.The high performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to 16 channels of analog input. The auto sequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring ad ditional communication interfaces; the ‘2407, ‘2406, and ‘2404 offer a 16-bit synchronous serial peripheral interface (SPI). The ‘2407 and ‘2406 offer a controller area network (CAN) communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as general purpose inputs/outputs (GPIO).To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code generation tools from C compilers to the industry-standard Code Composerdebugger supports this family. Numerous third party developers not only offer device-level development tools, but also system-level design and development support.PERIPHERALSThe integrated peripherals of the TMS320x240x are described in the following subsections:1Two event-manager modules (EV A, EVB)2Enhanced analog-to-digital converter (ADC) module3Controller area network (CAN) module3Serial communications interface (SCI) module4Serial peripheral interface (SPI) module5PLL-based clock module6Digital I/O and shared pin functions7External memory interfaces (‘LF2407 only)8Watchdog (WD) timer moduleEvent manager modules (EV A, EVB)The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EV A‘s and EVB‘s timers, compare units, and capture units function identically. However, timer/unit names differ for EV A and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the event-manager modules and highlights EV A nomenclature.Event managers A and B have identical peripheral register sets with EV A starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EV A nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ.Table 1. Module and Signal Names for EV A and EVBEVENT MANAGER MODULESEV AMODULESIGNALEVBMODULESIGNALGP Timers Timer 1Timer 2T1PWM/T1CMPT2PWM/T2CMPTimer 3Timer 4T3PWM/T3CMPT4PWM/T4CMPCompare Units Compare 1Compare 2Compare 3PWM1/2PWM3/4PWM5/6Compare 4Compare 5Compare 6PWM7/8PWM9/10PWM11/12Capture Units Capture 1Capture 2Capture 3CAP1CAP2CAP3Capture 4Capture 5Capture 6CAP4CAP5CAP6QEP QEP1QEP2QEP1QEP2QEP3QEP4QEP3QEP4External Inputs DirectionExternalClockTDIRATCLKINADirectionExternal ClockTDIRBTCLKINBGeneral-purpose (GP) timersThere are two GP timers: The GP timer x (x = 1 or 2 for EV A; x = 3 or 4 for EVB) includes:1.A 16-bit timer, up-/down-counter, TxCNT, for reads or writes2.A 16-bit timer-compare register, TxCMPR (double-buffered with shadowregister), for reads or writes3.A 16-bit timer-period register, TxPR (double-buffered with shadow register),for reads or writes4.A 16-bit timer-control register,TxCON, for reads or writes5.Selectable internal or external input clocks6.A programmable prescaler for internal or external clock inputs7.Control and interrupt logic, for four maskable interrupts: underflow, overflow,timer compare, and period interrupts8.A selectable direction input pin (TDIR) (to count up or down when directionalup-/down-count mode is selected)The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.Full-compare unitsThere are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.Programmable deadband generatorThe deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 24 µs) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register.PWM waveform generationUp to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.PWM characteristicsCharacteristics of the PWMs are as follows:●16-bit registers●Programmable deadband for the PWM output pairs, from 0 to 24 µs●Minimum deadband width of 50 ns●Change of the PWM carrier frequency for PWM frequency wobbling asneeded●Change of the PWM pulse widths within and after each PWM period asneeded●External-maskable power and drive-protection interrupts●Pulse-pattern-generator circuit, for programmable generation of asymmetric,symmetric, and four-space vector PWM waveforms●Minimized CPU overhead using auto-reload of the compare and periodregistersCapture unitThe capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EV A; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.Capture units include the following features:●One 16-bit capture control register, CAPCON (R/W)●One 16-bit capture FIFO status register, CAPFIFO (eight MSBs areread-only, eight LSBs are write-only)●Selection of GP timer 2 as the time base●Three 16-bit 2-level-deep FIFO stacks, one for each capture unit●Three Schmitt-triggered capture input pins (CAP1, CAP2, and CAP3)—oneinput pin per capture unit. [All inputs are synchronized with the device (CPU)clock. In order for a transition to be captured, the input must hold at itscurrent level to meet two rising edges of the device clock. The input pinsCAP1 and CAP2 can also be used as QEP inputs to the QEP circuit.]●User-specified transition (rising edge, falling edge, or both edges) detection●Three maskable interrupt flags, one for each capture unitEnhanced analog-to-digital converter (ADC) moduleA simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:●10-bit ADC core with built-in S/H●Fast conversion time (S/H + Conversion) of 500 ns●16-channel, muxed inputs●Autosequencing capability provides up to 16 ―autoconversions‖ in a sing lesession. Each conversion can be programmed to select any 1 of 16 inputchannels●Sequencer can be operated as two independent 8-state sequencers or as onelarge 16-state sequencer (i.e., two cascaded 8-state sequencers)●Sixteen result registers (individually addressable) to store conversion values●Multiple triggers as sources for the start-of-conversion (SOC) sequence✧S/W – software immediate start✧EV A – Event manager A (multiple event sources within EV A)✧EVB – Event manager B (multiple event sources within EVB)✧Ext – External pin (ADCSOC)●Flexible interrupt control allows interrupt request on every end of sequence(EOS) or every other EOS●Sequencer can operate in ―start/stop‖ mode, allowing multiple―time-sequenced triggers‖ to synchronize conversions●EV A and EVB triggers can operate independently in dual-sequencer mode●Sample-and-hold (S/H) acquisition time window has separate prescalecontrol●Built-in calibration mode●Built-in self-test modeThe ADC module in the ‘240x has been enhanced to provide flexib le interface to event managers A and B. The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Figure 2 shows the block diagram of the ‘240x ADC module.The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.Figure 2. Block Diagram of the ‘240x ADC ModuleTMS320LF2407, TMS320LF2406, TMS320LF2402TMS320LC2406, TMS320LC2404, MS320LC2402数字信号处理控制器TMS320LF240x和TMS320LC240x系列芯片作为’24x系列DSP控制器的新成员，是C2000平台下的一种定点DSP芯片。