zl30111中文资料_数据手册_IC数据表

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•Synchronizes to 8kHz, 2.048MHz, 8.192MHz or 19.44MHz input•Provides a range of clock outputs: 2.048MHz, 4.096MHz and 8.192MHz•Provides 2 styles of 8kHz framing pulses•Automatic entry and exit from freerun mode on reference fail•Provides DPLL lock and reference fail indication•DPLL bandwidth of 922Hz for all rates of input reference and 58 Hz for an 8kHz input reference•Less than 0.6 nspp intrinsic jitter on all output clocks•20 MHz external master clock source: clock oscillator or crystal•Simple hardware control interfaceApplications

•Synchronizer for POTS line cards•Rate convert NTR 8kHz or GPON physical interface clock to TDM clock

Description

The ZL30111 POTS line card PLL contains a digitalphase-locked loop (DPLL), which provides timing andsynchronization for SLIC/CODEC devices.

The ZL30111 generates TDM clock and framingsignals that are phase locked to the input reference.It helps ensure system reliability by monitoring itsreference for stability and by maintaining stableoutput clocks during short periods when thereference is unavailable.January 2007ZL30111POTS Line Card PLL

Data Sheet

Figure 1 - Functional Block Diagram

ReferenceMonitor

Mode ControlState MachineRST

C4C8

F4F8

OSCoOSCiMaster ClockREFLOCK

DPLLC2oREF_FAILOrdering InformationZL30111QDG64 Pin TQFPTrays, Bake & DrypackZL30111QDG164 Pin TQFP*Trays, Bake & Drypack*Pb Free Matte Tin-40°C to +85°CZL30111Data Sheet

Table of Contents

2Zarlink Semiconductor Inc.1.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.1 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.2 Digital Phase Lock Loop (DPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.5 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.0 DPLL Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2 Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.2 Jitter Generation (Intrinsic Jitter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.1 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

电子元器件zr25d中文资料_数据手册_IC数据表

V R

G ndDEVICE DESCRIPTION

The ZR25D uses a bandgap circuit design toachieve a precision micropower voltagereference of 2.5 volts. The device is availablein a small outline SOT23 surface mountpackage, ideal for applications where spacesaving is important.

The ZR25D design provides a stable voltagewithout an external capacitor and is stablewith capacitive loads. The ZR25D isrecommended for operation between 50µAand 5mA and so is ideally suited to lowpower and battery powered applications.

Excellent performance is maintained to anabsolute maximum of 25mA, however therugged design and 20 volt processing allowsthe reference to withstand transient effectsand currents up to 200mA. Superiorswitching capability allows the device toreach stable operating conditions in only afew microseconds.FEATURES

•Small outline SOT23 package.•No stabilising capacitor required•Typical TC 30ppm/°C•Typical slope resistance 0.4Ω•± 3%, 2% and 1% tolerance•Industrial temperature range•Operating current 50µA to 5mA•Transient response, stable in less than10µs•Alternative package options available

电子元器件zms2811中文资料_数据手册_IC数据表

SOD323 SCHOTTKY BARRIER DIODESISSUE 1 – NOVEMBER 19987FEATURES*Miniature Surface Mount Packages*Low turn-on voltage*Pico second switching speed*High breakdown voltageAPPLICATIONS*Mixers*Detectors*SwitchingPARTMARKZMS2800 - BAZMS2811 - BCZMS5800 - BBABSOLUTE MAXIMUM RATINGS.PARAMETERSYMBOLVALUEUNITForward Current (1µs pulse)IF1APower Dissipation at Tamb = 25°CPtot250mWOperating and Storage Temperature RangeTj:Tstg-55 to +150°CELECTRICAL CHARACTERISTICS (at Tamb = 25°C).PARAMETERTYPESYMBOLMIN.TYP.MAX.UNITCONDITIONS.Breakdown VoltageZMS2800ZMS2811ZMS5800VBR701550VVVIR=10µAReverse LeakageCurrentZMS2800ZMS2811ZMS5800IR200100200nAnAnAVR=50VVR=10VVR=35VForward VoltageZMS2800ZMS2811ZMS5800VF410410410mVmVmVIF=1mAForward CurrentZMS2800ZMS2811ZMS5800IF152015mAmAmAVF=1VCapacitanceZC2800EZC2811EZC5800ECT1.21.02.01.22.0pFpFpFVR=0 V, f=1MHzEffective MinorityLifetime (1)ZC2800EZC2811EZC5800Eτ100100100pspspsf= 54 MHzIpk= 20mAZMS2800ZMS2811ZMS5800C

ZL30110资料

•Synchronizes to 8kHz, 2.048MHz, 8.192MHz or 16.384MHz •Provides a range of output clocks:•65.536MHz TDM clock locked to the input reference

•General purpose 25MHz fan-out to 6 outputs locked to the external crystal or oscillator

•General purpose 125MHz and 66MHz or 100MHz locked to the external crystal or oscillator

•Provides DPLL lock and reference fail indication•Automatic free run mode on reference fail•DPLL bandwidth of 922Hz for all rates of input reference and 58Hz for an 8kHz input reference•Less than 5 psecrms on 25MHz outputs, and less than 0.6 nspp intrinsic jitter on the all other outputs•Minimal input to output and output to output skew•25MHz external master clock source: clock oscillator or crystal•Simple hardware control interfaceApplications