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sl521中文资料_数据手册_IC数据表

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SL521150MHz WIDEBAND LOG AMPLIFIER

The SL521A, B and C are bipolar monolithic Integratedcircuit wideband amplifiers, intended primarily for use insuccessive detection logarithmic IF strips, operating at centrefrequencies between 10MHz and 100MHz The devicesprovide amplification, limiting and rectification, are suitable fordirect coupling and incorporate supply line decoupling Themid-band voltage gain of the SL521 is typically12dB(4times)The SL521A, B and C differ mainly in the tolerance of voltagegain and upper cut-off frequencyThe device is also available as the 5962-90792 which hasguaranteed operation over the full Military TemperatureRange and is screened to MIL-STD-883 Class B. Data isavailable separately

FEATURES

sWide Defined Gains4dB Noise FiguresHlgh I/P impedancesLow O/Pi mpedances165MHz BandwidthsOn Chip Supply DecouplingsLow External Component Count

ORDERING INFORMATION

SL521 A CM5962-90792 (SMD)SL521 B CMSL521 C CM ABSOLUTE MAXIMUM RATINGS (Non-simultaneous)

Storage temperature range-65°C to +150°COperating temperature range-55°C to +125°CChip operating temperature+175°C Chip-to-ambient thermal resistance225°C/W Chip-to-case thermal resistance65°C/WMaximum instantaneous voltage at Video output+12VSupply voltage+9V

APPLICATIONS

sLogarithmic IF Strips wlth Gains up to 108dB andLinearity better than 1dB

Fig.1 Pin connections - bottom viewCM8

Fig.2 Circuit diagram SL521DS3606 - 2.0ADVANCE INFORMATIONSL521

ELECTRICAL CHARACTERISTICS These characteristics are guaranteed over the following conditions (unless otherwise stated)Temperature = +22°C + 2°CSupply voltage = +6VDC connection between input and bias pins.Min.Typ.Max.

Voltage gain, f = 30MHz A11.512.5 dB B11 .31 2.7 dB C11.013.0 dB10 ohms source, 8pF loadVoltage gain, f = 60MHz A11.312.7 dB B11.013.0 dB C10.713.3 dBUpper cut-off frequency (Fig. 3) A150170 MHz B140170 MHz10 ohms source, 8pF load C130170 MHzLower cut-off frequency (Fig. 3) A B C 5 7 MHz10 ohms source, 8pF loadPropagation delay A B C 2 nsMaximum rectified video output A1.001.10 mAcurrent (Fig. 4 and 5) B0.951.15 mAf = 60MHz, 0.5V rms input C0.901.20 mAVariation of gain with supply voltage A B C 0.7 db/VVariation of maximum rectified A B C 25 %/Voutput current with supply voltageMaximum input signal before overload A B C 1.8 1.9 V rmsSee note belowNoise figure (Fig. 6) 45.25 dBf = 60MHz, Rs = 450 ohmsSupply current A12.515.018.0 mA B12.515.018.0 mA C11.515.019.0 mA

Maxiumum RF output voltage 1.2 Vp-pValueUnitsConditionsCircuitsCharacteristic

Note: Overload occurs when the input signal reaches a level sufficient to forward bias the base-collector junction to TR2 on peaks.

Fig.3 Voltage gain v. frequency (typical)Fig.4 Rectified output current v. input signal (typical)SL521

Fig.5 Maximum rectified output current v. temperature(typical)Fig.6 Noise figure v. temperature (typical)Fig.7 Input admittance with open-circuit output (typical)Fig.8 Direct Coupled amplifiers

Fig.9 Suitable interstagetuned circuitOPERATING NOTES

The amplifiers are intended for use directly coupled, asshown in Fig 8.The seventh stage in an untuned cascade will be givingvirtually full output on noise.Noise may be reduced by inserting a single tuned circuit inthe chain As there is a large mismatch between stages asimple shunt or series circuit cannot be used The choice ofnetwork is also controlled by the need to avoid distorting thelogarithmic law; the network must give unity voltage transfer atresonance A suitable network is shown in Fig 9. The value ofC1 must be chosen so that at resonance its admittance equalsthe total loss conductance across the tuned circuit Resistor R1may be introduced to improve the symmetry of filter response,providing other values are adjusted for unity galn atresonance.A simple capacitor may not be suitable for decoupling theoutput line if many stages and fast rise times are required.Alternative arrangements may be derived, based on theparasitic parameters given.Values of positive supply line decoupling capacitorrequlred for untuned cascades are given below. Smallervalues can be used in high frequency tuned cascades.

Number of stages 6 or more 5 4 3

Minimum capacitance 30nF 10nF 3nF lnFThe amplifiers have been provided with two earth leads toavoid the introduction of common ground lead inductancebetween input and output circuits. The equipment designershould take care to avoid the subsequent introduction of suchinductance.The 500pF supply decoupling capacitor has a resistanceof, typically, 1 0Q. It is a junction type having a low breakdownvoltage and consequently the positive supply current willincrease rapidly if the supply voltage exceeds 7.5V (seeAbsolute Maximum Ratings).SL521

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[整理]REX521技术参考手册.

[整理]REX521技术参考手册.

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------------- REX 521型微机保护继电器

技术参考手册 汇编

上海ABB工程有限公司

2002,08,18

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------------- 1. 概述

REX521建立在RED500平台上，是REF54_型馈线终端的一种简化产品。它是综合保护、控制、测量、监视和通信为一体的微机终端。本手册阐述REX521终端的概貌、及其配置。首先是概述，第二部分逐项描述了基本配置和中级配置等两种的标准配置的概况，第三部分到第六部分介绍了信号路径及其功能，第七部分为应用举例。最后是附录，为原版Copy的技术数据和外部结线图，以供查阅防止误导。

REX 521 和RED 500 平台在功能模块介绍上的不同

在CD-ROM“功能的技术介绍” (1MRS 750889-MUM)的功能 模块的介绍方面， REX521

和RED 500 平台在某些方面有所不同。首先，某些术语是指其他产品而不是REX521，其

次，有某些数据仅适用于REX521：

• 在试验某一功能模块时，READY 指示灯闪烁。

• 事件标识位1仅适用于SPA 通讯。

• 不能实现直接控制自动重合闸的功能。

REX521输入、输出量一览表：

硬件版本 模拟量输入AI量 二进制输入DI量 大功率输出PO量 信号输出SO量

基本版本 4I 9 4 2

中级版本 5I+1U 9 4 2

注：以上输出量指可编程的数量，另还有反映装置故障或直流电源消失的IRF报警输出。

REX521的输出继电器接点能力

输出继电器名称 HSPO / PO SO / IRF

连续载流能力 5 A 5 A

0.5秒载流能力 30 A 10 A

3秒载流能力 15 A 8 A

在DC 48/110/220伏，控制回路时间常数L/R<40ms下的遮断能力 5 / 3 / 1 A 1 / 0.25 / 0.15 A

mt8941中文资料_数据手册_IC数据表

mt8941中文资料_数据手册_IC数据表

1Zarlink Semiconductor Inc.Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.Features•Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse)•Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock•Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak•Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz ≥ 64 dB•Jitter-free “FREE-RUN” mode•Uncommitted two-input NAND gate•Low power CMOS technologyApplications•Synchronization and timing control for T1 and CEPT digital trunk transmission links•ST- BUS clock and frame pulse sourceDescriptionThe MT8941B is a dual digital phase-locked loopproviding the timing and synchronization signals for theT1 or CEPT transmission links and the ST-BUS. Thefirst PLL provides the T1 clock (1.544 MHz)synchronized to the input frame pulse at 8 kHz. Thetiming signals for the CEPT transmission link and theST-BUS are provided by the second PLL locked to aninternal or an external 8 kHz frame pulse signal.The MT8941B offers improved jitter performance overthe MT8940. The two devices also have somefunctional differences, which are listed in the section on“Differences between MT8941B and MT8940”.February 2005Ordering InformationMT8941BE24 Pin PDIPTubesMT8941BP28 Pin PLCCTubesMT8941BPR28 Pin PLCCTape & ReelMT8941BP128 Pin PLCC*TubesMT8941BPR128 Pin PLCC*Tape & Reel*Pb Free Matte Tin-40°C to +85°CMT8941B Advanced T1/CEPT Digital Trunk PLLData SheetFigure 1 - Functional Block DiagramF0iC12iMS0MS1MS2MS3C8KbC16iAiBiYoVDDVSSRSTCVbCVENCVF0bC4bC4oENC4oC2oC2oENC2o2:1 MUXVariableClockControlModeSelectionLogicDPLL #2InputSelectorClockGeneratorFrame PulseControl4.096 MHzClockControl2.048 MHzClockControlDPLL #1https://MT8941BData Sheet

p10c68中文资料_数据手册_IC数据表

p10c68中文资料_数据手册_IC数据表

P10C68/P11C68

1DS3600-1.2 September 1992PRELIMINARY INFORMATION

P10C68/P11C68

(Previously PNC10C68 and PNC11C68)

CMOS/SNOS NVSRAM

HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM

(Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1)

The P10C68 and P11C68 are fast static RAMs (35 and 45

ns) with a non-volatile electically-erasable PROM (EEPROM)

cell incorporating in each static memory cell. The SRAM can

be read and written an unlimited number of times while

independent non-volatile data resides in PROM.

On the P10C68 data may easily be transferred from the

SRAM to the EEPROM (STORE) and from the EEPROM back

to the SRAM ( RECALL) using the NE (bar) pin. The Store and

Recall cycles are initiated through software sequences on the

P11C68. These devices combine the high performance and

ease of use of a fast SRAM with the data integrity of non-

zl30116中文资料_数据手册_IC数据表

zl30116中文资料_数据手册_IC数据表

1Zarlink Semiconductor Inc.Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.Copyright 2005-2006, Zarlink Semiconductor Inc. All Rights Reserved.A full Design Manual is available to qualified customers.To register, please send an email toTimingandSync@.Features•Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks•Internal APLL provides standard output clock frequencies up to 622.08MHz that meet jitter requirements for interfaces up to OC-192/STM-64•Programmable output synthesizers generate clock frequencies from any multiple of 8kHz up to 77.76MHz in addition to 2kHz•Provides two DPLLs which are independently configurable through a serial software interface•DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range•DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other general purpose clocks•Provides 8 reference inputs which support clock frequencies with any multiples of 8kHz up to 77.76MHz in addition to 2kHz•Supports master/slave configuration for AdvancedTCATM•Configurable input to output delay and output to output phase alignment•Optional external feedback path provides dynamic input to output delay compensation•Provides 3 sync inputs for output frame pulse alignment•Generates several styles of output frame pulses with selectable pulse width, polarity and frequency•Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities•Supports IEEE 1149.1 JTAG Boundary ScanJune 2006