An Intelligent...(IJEME-V6-N5-3)

Proprietary Flex SDK 3.4.2.0 GAGecko SDK Suite 4.1September 28, 2022less applications.Per its namesake, Flex offers two implementation options.The first uses Silicon Labs RAIL (Radio Abstraction Interface Layer), an intuitive and eas-ily-customizable radio interface layer designed to support both proprietary and standards-based wireless protocols.The second uses Silicon Labs Connect, an IEEE 802.15.4-based networking stack de-signed for customizable broad-based proprietary wireless networking solutions that re-quire low power consumption and operates in either the sub-GHz or 2.4 GHz frequencybands. The solution is targeted towards simple network topologies.The Flex SDK is supplied with extensive documentation and sample applications. All ex-amples are provided in source code within the Flex SDK sample applications.These release notes cover SDK version(s):3.4.2.0 GA released September 28, 20223.4.1.0 GA released August 17, 20223.4.0.0 GA released June 8, 2022Compatibility and Use NoticesFor information about security updates and notices, see the Security chapter of the Gecko Platform Release notes installed with this SDK or on the TECH DOCS tab on https:///developers/flex-sdk-connect-networking-stack. Silicon Labs also strongly recommends that you subscribe to Security Advisories for up-to-date information. For instructions, or if you are new to the Silicon Labs Flex SDK, see Using This Release.Compatible Compilers:IAR Embedded Workbench for ARM (IAR-EWARM) version 9.20.4•Using wine to build with the IarBuild.exe command line utility or IAR Embedded Workbench GUI on macOS or Linux could result in incorrect files being used due to collisions in wine’s hashing algorithm for generating short file names.•Customers on macOS or Linux are advised not to build with IAR outside of Simplicity Studio. Customers who do should carefully verify that the correct files are being used.GCC (The GNU Compiler Collection) version 10.3-2021.10, provided with Simplicity Studio.Contents Contents1Connect Applications (1)1.1New Items (1)1.2Improvements (1)1.3Fixed Issues (1)1.4Known Issues in the Current Release (1)1.5Deprecated Items (1)1.6Removed Items (1)2Connect Stack (2)2.1New Items (2)2.2Improvements (2)2.3Fixed Issues (2)2.4Known Issues in the Current Release (2)2.5Deprecated Items (3)2.6Removed Items (3)3RAIL Applications (4)3.1New Items (4)3.2Improvements (4)3.3Fixed Issues (4)3.4Known Issues in the Current Release (4)3.5Deprecated Items (4)3.6Removed Items (4)4RAIL Library (5)4.1New Items (5)4.2Improvements (5)4.3Fixed Issues (5)4.4Known Issues in the Current Release (6)4.5Deprecated Items (7)4.6Removed Items (7)5Using This Release (8)5.1Installation and Use (8)5.2Security Information (8)5.3Support (9)Connect Applications 1 Connect Applications1.1 New ItemsAdded in release 3.4.0.0•PSA Crypto API usage•Major update of Connect - SoC ECDH Key Exchange1.2 ImprovementsNone1.3 Fixed IssuesNone1.4 Known Issues in the Current ReleaseIssues in bold were added since the previous release. If you have missed a release, recent release notes are available on the TECH DOCS tab on https:///developers/flex-sdk-connect-networking-stack.652925 EFR32XG21 is not supported for “Flex (Connect) - SoC LightExample DMP” and “Flex (Connect) - SoC Switch Example”1.5 Deprecated ItemsNone1.6 Removed ItemsNone2 Connect Stack2.1 New ItemsAdded in release 3.4.0.0•All of the crypto operations are now made through ARM PSA Crypo API, enabling the storage of the network security key in the Secure Vault.•Added a new API emberSetPsaSecurityKey() that indicates which PSA Crypto key handler has to be used by the stack. It is the application’s responsibility to create the key. The old emberSetSecurityKey()no longer designates the key used by the network. It can be used to erase an old key from its previous location in NVM.•Added a new API emberRemovePsaSecurityKey()that cancels the effects of emberSetPsaSecurityKey(). It does not erase the key. It is the application’s responsibility to destroy the key.2.2 ImprovementsNone2.3 Fixed IssuesFixed in release 3.4.2.01022904Fixed an error that was causing the application task to be blocked by the stack task during an active scan. As a result, the application was missing beacons.Fixed in release 3.4.0.0833232 Fixed an error that was causing Connect Application Framework IPC to write to the address 0.2.4 Known Issues in the Current ReleaseIssues in bold were added since the previous release. If you have missed a release, recent release notes are available on the TECH DOCS tab on https:///developers/gecko-software-development-kit.When running the RAIL Multiprotocol Library (used forexample when running DMP Connect+BLE), IR Calibrationis not performed because of a known issue in the RAILMultiprotocol Library. As result, there is an RX sensitivityloss in the order of 3 or 4 dBm.501561 In the Legacy HAL component,the PA configuration is hard-coded regardless of the user or board settings. Until this is changed to properly pull from the configuration header, the file ember-phy.c in the user's project will need to be modified by hand to reflect the desired PA mode, voltage, and ramp time.711804 Connecting multiple devices simultaneously may fail with a timeout error.2.5 Deprecated Items None2.6 Removed Items NoneRAIL Applications 3 RAIL Applications3.1 New ItemsAdded in release 3.4.0.0•EFR32xG24 support•FGM230S support•RAIL Bluetooth DMP - SoC Range Test BLE and IEEE802.15.4 demos for some XGM210 boards3.2 ImprovementsNone3.3 Fixed IssuesNone3.4 Known Issues in the Current ReleaseNone3.5 Deprecated ItemsNone3.6 Removed ItemsNone4 RAIL Library4.1 New ItemsAdded in release 3.4.2.0•Added early support for IEEE802.15.4G dynamic forward error correction PHYs on the EFR32xG12 platform. Use requires help from support to create an appropriate PHY.Added in release 3.4.0.0•The RAIL channel of a received packet is now available in the packet's RAIL_RxPacketDetails_t::channel field. This can be of value when scanning or hopping across multiple channels while letting packets accumulate in the receive FIFO for later processing.•Added the RAIL_ConfigPaAutoEntry API to allow for easier configuration of PA auto mode operation in RAIL.•Added the RAIL_SetRssiDetectThreshold API to allow the user to detect when the RSSI is at or above a configurable threshold.Once configured, the RAIL_EVENT_DETECT_RSSI_THRESHOLD event can be used to detect when this happens.•Added support for the MGM240L022RNF module.•Added support for the FGM230SA27HGN and FGM230SBHGN modules.•Added the RAIL_GetChannelAlt API. This function returns the channel the radio is currently using. If using DMP and run on the inactive protocol it returns the channel that will be used when next switching to that protocol. When using channel hopping, mode switch, and other features that change channels dynamically this may be different than what is returned by RAIL_GetChannel, as this function will track what channel the radio is actually on at that moment and not what it started on.4.2 ImprovementsChanged in release 3.4.2.0•Improved PA configurations for the xGM240 modules based on additional test data.Changed in release 3.4.1.0•Added support in "RAIL Utility, Coexistence" component for configuring priority options when directional priority is enabled but no static priority GPIO is defined.Changed in release 3.4.0.0•The "RAIL Utility, PTI" component will now validate that the correct set of pins are in use for the desired PTI mode.•RAIL will now error if attempting to start a CSMA or LBT transmit while a scheduled RX is still in progress or vice versa.•Added PA curves for BGM240P and MGM240P modules.•Restricted the SL_RAIL_UTIL_PA_RAMP_TIME_US to 10us on some EFR32 modules to match the certification conditions.4.3 Fixed IssuesFixed in release 3.4.2.0844377 Fixed a Bluetooth LE 2 Mbps AoX issue on EFR32xG24 when using a 38.4 MHz crystal.1029710 Fixed an issue with RAIL's PA auto mode that would cause it to select an unsupported RAIL_TxPowerMode_t on chip OPNs that are missing the higher power PAs.Fixed in release 3.4.1.0819544 Improved reception on EFR32xG23 and EFR32xG24 when using a PHY with fast detect enable (preamble sense mode).843708 Moved function declarations from rail_features.h to rail.h to avoid a convoluted include dependency order.844325 Fixed RAIL_SetTxFifo() to properly return 0 (error) rather than 4096 for an undersized FIFO.844936 Fixed an issue where using RAIL_SetNextTxRepeat() could cause a brownout reset on EFR32xG23.853714 Fixed an issue with xGM240 modules causing them to assert during initialization.988518 Fixed an issue where the radio sequencer would leave portions of the chip enabled after AoX CTE packet reception, preventing the device from going into EM2 sleep and potentially causing missed packet receive events.Fixed in release 3.4.0.0376658 Fixed an issue with the Bluetooth LE coded PHY on EFR32xG21 where a packet received with a corrupt coding indicator would result in an invalid start-of-packet timestamp.759793 Fixed an issue with Bluetooth LE long-range reception on EFR32xG21 that corrupted packet data and tripped RAIL_ASSERT_FAILED_UNEXPECTED_STATE_RX_FIFO.772769 Fixed an issue when running IR Calibration on the EFR32xG23 using RAIL_CalibrateIrAlt where we could compute an invalid IRCAL value for certain PHYs and chips.777427 Fixed support for using the signal identifier CCA modes simultaneously with a user-enabled signal identifier trigger event.819644 Fixed an issue with frame-type decoding PHYs running at more than 500 kbps on EFR32xG22 and later.825083 Fixed an issue on EFR32xG23 and EFR32xG24 where PTI could merge multiple receive packets into the same transaction when interrupt latency is significant.829499 Fixed an issue where RAIL_GetRadioStateDetail would not report the correct state information when frame detection was disabled or during an LBT operation.830214 Ensure that the RAIL_RadioConfigChangedCallback_t is called for all RAIL handles in a dynamic multiprotocol application where multiple handles use the same underlying PHY configuration.835299 Fixed an issue with dynamic handling of whitening and FCS in FSK when onlyRAIL_IEEE802154_E_OPTION_GB868 was enabled.844600 Fixed an issue of not being able to receive packets during a RAIL_ScheduleRx configured with a zero relative start time when Power Manager sleep is enabled and configured with an EM2 or lower energy requirement.4.4 Known Issues in the Current ReleaseIssues in bold were added since the previous release.Using direct mode (or IQ) functionality on EFR32xG23requires a specifically set radio configuration that is notyet supported by the radio configurator. For theserequirements, reach out to technical support who couldprovide that configuration based on your specification641705 Infinite receive operations where the frame's fixed lengthis set to 0 are not working correctly on the EFR32xG23series chips.732659 On EFR32xG23:•Wi-SUN FSK mode 1a exhibits a PER floor with fre-quency offsets around ± 8 to 10 KHz• Wi-SUN FSK mode 1b exhibits a PER floor with fre-quency offsets around ± 18 to 20 KHz1019590When using the “RAIL Utility, Coexistence”component with Bluetooth LE thesl_bt_system_get_counters() function will alwaysreturn 0 for GRANT denied counts.Contact support for a patch to coexistence-ble.c to fix this issue.4.5 Deprecated Items None4.6 Removed Items NoneUsing This Release 5 Using This ReleaseThis release contains the following•Radio Abstraction Interface Layer (RAIL) stack library•Connect Stack Library•RAIL and Connect Sample Applications•RAIL and Connect Components and Application FrameworkThis SDK depends on Gecko Platform. The Gecko Platform code provides functionality that supports protocol plugins and APIs in the form of drivers and other lower layer features that interact directly with Silicon Labs chips and modules. Gecko Platform components include EMLIB, EMDRV, RAIL Library, NVM3, and mbedTLS. Gecko Platform release notes are available through Simplicity Studio’s Documentation tab.For more information about the Flex SDK v3.x see UG103.13: RAIL Fundamentals and UG103.12: Silicon Labs Connect Fundamentals. If you are a first time user, see QSG168: Proprietary Flex SDK v3.x Quick Start Guide.5.1 Installation and UseThe Proprietary Flex SDK is provided as part of the Gecko SDK (GSDK), the suite of Silicon Labs SDKs. To quickly get started with the GSDK, install Simplicity Studio 5, which will set up your development environment and walk you through GSDK installation. Simplicity Studio 5 includes everything needed for IoT product development with Silicon Labs devices, including a resource and project launcher, software configuration tools, full IDE with GNU toolchain, and analysis tools. Installation instructions are provided in the online Simplicity Studio 5 User’s Guide.Alternatively, Gecko SDK may be installed manually by downloading or cloning the latest from GitHub. See https:///Sili-conLabs/gecko_sdk for more information.Simplicity Studio installs the GSDK by default in:•(Windows): C:\Users\<NAME>\SimplicityStudio\SDKs\gecko_sdk•(MacOS): /Users/<NAME>/SimplicityStudio/SDKs/gecko_sdkDocumentation specific to the SDK version is installed with the SDK. Additional information can often be found in the knowledge base articles (KBAs). API references and other information about this and earlier releases is available on https:///.5.2 Security InformationSecure Vault IntegrationWhen deployed to Secure Vault High devices, sensitive keys are protected using the Secure Vault Key Management functionality. The following table shows the protected keys and their storage protection characteristics.Thread Master Key Exportable Must be exportable to form the TLVsPSKc Exportable Must be exportable to form the TLVsKey Encryption Key Exportable Must be exportable to form the TLVsMLE Key Non-ExportableTemporary MLE Key Non-ExportableMAC Previous Key Non-ExportableMAC Current Key Non-ExportableMAC Next Key Non-ExportableWrapped keys that are marked as “Non-Exportable” can be used but cannot be viewed or shared at runtime.Wrapped keys that are marked as “Exportable” can be used or shared at runtime but remain encrypted while stored in flash.For more information on Secure Vault Key Management functionality, see AN1271: Secure Key Storage.Using This ReleaseSecurity AdvisoriesTo subscribe to Security Advisories, log in to the Silicon Labs customer portal, then select Account Home. Click HOME to go to the portal home page and then click the Manage Notifications tile. Make sure that ‘Software/Security Advisory Notices & Product Change Notices (PCNs)’ is checked, and that you are subscribed at minimum for your platform and protocol. Click Save to save any changes.5.3 SupportDevelopment Kit customers are eligible for training and technical support. Use the Silicon Labs Flex web page to obtain information about all Silicon Labs Thread products and services, and to sign up for product support.You can contact Silicon Laboratories support at /support.Silicon Laboratories Inc.400 West Cesar Chavez Austin, TX 78701USA IoT Portfolio /IoT SW/HW /simplicity Quality /quality Support & Community /communityDisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software imple-menters using or intending to use the Silicon Labs products. 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I.J. Education and Management Engineering, 2017, 5, 7-22Published Online September 2017 in MECS ()DOI: 10.5815/ijeme.2017.05.02Available online at /ijemeRealization of Flip Flops using LabVIEW and MATLABMittarpal a, Naresh Kumar b, Priyanka Anand a, Sunita aa BPS Women University, Khanpur Kalan, Sonipat,131305, Indiab SGT University, Gurgaon, Haryana,122505, IndiaReceived: 07 February 2017; Accepted: 13 May 2017; Published: 08 September 2017AbstractDigital electronics is the backbone of current technology, play a pivotal role in the growth of humanity. Digital memory is part of digital electronics consists flip-flops building blocks designed by using logical NAND and NOR gates. Validation of storing information in form of bits can be understood from analysis of working of flip-flops. In the present investigation, VI Model of the different flip flops in LabVIEW has been realized and simulation implementation of flip flops is utilized to analyze the functioning of memory elements. The characteristics table of all kind of flip flop is verified using VI Models. Moreover, different flip-flops are also realized in MATLAB using Simulink. In the phase of digital and internet, this student -centric learning of existing theory of flip-flops can easily understand using simulation environment.Index Terms: Flip-flop, Clock, LabVIEW, Boolean function, Simulation, Sequential circuits, Memory elements, Digital electronics, MATLAB, Simulink.© 2017 Published by MECS Publisher. Selection and/or peer review under responsibility of the Research Association of Modern Education and Computer Science.1.IntroductionSimulation is not only just technology to test the functioning of a system for a set of inputs but also describe the behavior in the practical environment. It gives the view of designing, architecture, process before significant time and cost has been invested, and can be of the great benefit in support of technology implementation [1]. Simulation and modeling are getting knowledge about how a system will behave without actually testing in real life [2]. Simulation modeling provides a powerful methodology for advancing theory and research on complex behaviors and systems [3]. Simulation provides a way to actively engage scholar in making and testing conjunctures about data, developing their reasoning about electronic concepts and procedures. Simulation can encourage them to develop their analytical reasoning by requiring them to analyze * Corresponding author.E-mail address:processes and set up a series of outcomes (i.e. modeling) [4]. In order to reduce costs, improving quality, and shortening the time-to-market for manufactured goods, simulation plays a vital role. The development of new simulation interface standards could help increase the development of simulation technology [5]. Digital electronics is used fundamental scientific computation and internet of things. To provide the platform to students, to test their ideas through simulation laboratory using Labview/Matlab, this paper presents simulation design of different flip flops i.e R-S, J-K, D, T flip-flops using LabVIEW-VI Models [6],[7],[8].bVIEW Simulation ToolLabView stands for Laboratory Virtual Instrument Engineering Workbench. In LabView, the Models developed for a solution of given mathematical or logical problem using graphical programming are known as VI’s and every VI uses various functions that manipulate and map input from the user end and display that information, move it to other files or other computers. To do work with LabView, first, open LabView version and create a project for your work. Every VI block contains the three components:∙Front PanelIn Fig.1, shows an example of front panel [6]. Front panel have numeric, Boolean, string and path array matrix, list table and graph, ring and enum containers I/O variant and CI decoration enum etc∙Block PanelIt contains graphical source code to describe the functionality of the VI. Front panel objects appear as terminals on the block diagram. Block diagram comprises structures, array, cluster, numeric, Boolean, string comparison, timing, dialog & use, file I/O, waveform application, synchronization, graphics etc.∙Icon & Connector PanelIt can be used to identify the VI so that another VI (sub-VI) can be used in VI. Sub VI role is similar to the subroutine in the text - based G programming languages [6]. LabView have a great scope in various areas, to bridging the gap between theories and their practical implementation. LabVIEW is mainly used in data acquisition interface with hardware. The domain and type of usage of virtual platform LabVIEW is depicted in Fig. 1.Fig.1. Usage of LabVIEWIn the previous section, an overview of LabVIEW has been described. In forthcoming section 2 and in section 3, digital circuits systems are classified and flip-flops with their designs using logical gates have beenpresented.2.Types of Digital Circuit SystemsDigital electronics are backbones in electronics and electrical technology in current epoch [8], [9], [10], [11], [12], [13]. In Fig.2, the classification of Digital circuits is depicted and described below.Combinational Digital Circuits: Only present states of input determine the outcome of combinational devices.Sequential Digital Circuits: Sequential digital circuit includes combinational digital circuit in forward path and memory elements in feedback path. Fig.3 shows the block diagram of sequential digital circuit.Fig.2. Classification of Electronic Digital CircuitsFig.3. Block Diagram of Sequential Circuit2.1Memory Element (ME)The memory elements are the flip-flops or latches to store binary information in form of bits.State of the flip-flops define either stored or to store binary information. A state may present state (PS) or next state (NS), which stored in the memory element. Digital circuit systems have the memory elements are known as sequential logic circuits.2.2Sequential Logic circuitOutputs of the sequential digital circuit depend upon external inputs and output of the memory elements. Sequential logic circuits are two types’ synchronous sequential logic circuit and asynchronous sequential logic circuit. Synchronous Sequential logic circuits are those digital circuits whose behavior can be defined from the knowledge of its signals (inputs and present state) at synchronous time intervals.3.Design and Analysis of Latchtch using NOR gateDigital devices may need memory element to carry the previous state of the output. Memory elements can store binary information [1], [2], [3], [9], [10]. Flip-flop is used as the memory element. A latch is an asynchronous circuit where two inputs(S-set and R-r eset) and two outputs Q and Q’, both are a complement to each other. The feedback path is made by cross-coupled connection from the output of the second gate back to the input of the first gate and vice versa.Working on latch: It may be design either using NOR or NAND gates. The working of latch is described as below:Step 1:If SR inputs are 1 and 0 then output Q is 1: NOR Gate-1, consist of two inputs first come from reset is0 and other from the output of NOR gate-2 is 0 and the output Q is 1. Similarly, NOR gate-2, consistof two inputs comes from the set is 1 and other from the output of NOR gate-1 is 0 and the output Q’ is 0.Step 2:If SR inputs are 0 and 1 then output Q is 0: NOR gate G1, consist of two inputs first comes from reset is 1 and other from the output of NOR gate-2 is 0 and the output Q is zero. Similarly, NOR gate-2, consist of two input comes from set is 0 and other from output of NOR gate-1 is 0 and the output Q’ is1.Step 3:If SR inputs are 0 and 0 then the output Q is 0: NOR gate G1, consist of two inputs, first come from reset is 0 and other from the output of NOR gate-2 is 1, then the output Q is 0. Similarly, NOR gate-2, consist of two inputs comes from the set input is zero and other from output of NOR gate-1 is 0 and the output Q’ is 1.Step 4:If SR inputs are 1 and 1 then output Q is not determined: NOR gate G1, consist of two inputs first come from reset is 1 and other from the output of NOR gate-2 are 1; Similarly, NOR gate-2, consist of two inputs comes from set is 1 and other input from the output of NOR gate-1 is 0; As for both NOR gates, one input is already 1, so no one will wait further and both try to give output Q and Q’ as0. That’s why it is almost impossible to predict the output. S-R latch comprising of NOR gates hasbeen shown in Fig.4.Fig.4. Design of Latch Using NOR GatesThe working of latch comprise the nor gates, can be summerised in Table 1.Table 1. Characteristic Table of RS Flip-FlopS R Q Q’0 1 0 100 0 11 1 - -3.2.Realisation of Latch using NAND GateThe design of latch using NAND gates is depicted in Fig.5.Fig.5. Fundamental Flip-Flop with NAND GatesBasic latch have two NAND gates in which S, R are inputs and Q, Q’ as outputs. The G1 have two inputs, one is input S and another from the output Q’ of G2. G2 gate also have two inputs, one is R and another from output Q of G1. Initially, Reset input kept logical 1 and Set at logical 0. Due to these inputs, the normal output returns to logical 1 and Q’ goe s to logical 0. Now if both input Set and Reset has shifted to logical 0, the normal output remain logical 1 and Q’ remain logical 0. Hence at S=0 and R=0, the latch behave like the memory element. If the Reset is at logical 1 and Set is at logical 0 then the normal output becomes logical 0 and inverted output becomes logical 1, are known as the clear state of the memory element. By shifting the S input to logical 0 and R input to logical 0, the outputs remain same present state.It is strongly recommended that the both input S and R never fed logical 1, since both output returns to logical 0, which is inconsistence with normal and inverted output of the latch the behavior of variation of output with changes in inputs of the latch is depicted in Table 2.Table 2. Characteristic Table of SR Flip-FlopS R Q Q’1 1 0 10 1 1 01 1 1 000 1 13.3.Clocked RS Flip-FlopThe latch or basic flip flop discussed above is an asynchronous sequential circuit and if a clock is used in such latches, then it is known as a synchronous sequential circuit, depicted in Fig.6 as clocked R-S flip flop. It has two AND neither gates, two NOR gates. G1 AND gate have two input, one is R and second clock pulse, and G2 the AND gate also consist two input R and CP, the output of G1 fed to G3 NOR gate and output of G2 to G3 NOR gate. Logical AND gate gives output 0 if either of input is 0, output 1 if all inputs are logical 1. If clock Pulse is zero, the output of the G1 and G2 AND gates remain logical 0 because the output of the G1 and G2 are connected to G3 and G4, regardless of S and R input values. When clock is one, information from S and R inputs allowed to reach to the SR latch, if S is 1 and R are 0, CP=1, flip-flop returns to set, and normal output becomes logical 1, inverted output logical 0, are known as set the state of clocked RS flip-flop. The truth table of SR flip-flop is represented in Table3.Fig.6. Circuit for SR Flip-Flop (Clocked) and Symbol of clocked SR Flip-Flop Table 3. Characteristic Table of SR Clocked Flip-Flopn n+10 0 0 0 0 0 1 0 0 1 0 10 1 1 Indeterminate 1 0 0 1 1 0 1 0 1 1 0 1111Indeterminate3.4. D Flip-FlopD flip-flop is modified version of SR flip-flop, and it is depicted in Fig.7, consists input D and inverted D using G5 NAND gate.Fig.7.Logic Diagram D Flip-Flop using NAND Gates and Graphical Representation of D Flip-Flop4. Implimentation Of RS Latch Using LabVIEW and MATALBIn this section, different flip-flops are developed using Labview VI models[11], [14]. 4.1. Asynchronous RS Flip-Flop Using NOR GateIn Fig.8, VI model of RS flip-flop has RS as inputs and Q and Q’ as outputs, with cross -feedback connections is developed in block panel LabVIEW.Fig.8. Fundamental Memory Element with NOR Gates VI Model Using LabviewDesign of R-S Latch Using MATLAB-Simulink: In Fig.9, the Simulink model of R-S latch is depicted.Fig.9. R-S Latch Realization Using NOR gates in MATLAB-Simulink Environment4.2.RS Latch Using NAND Gates in VI ModelLabVIEW VI model of RS flip-flop using NAND gate is shown in Fig.10 which consist two NAND gate, with cross-feedback and S and R inputs.Fig.10. SR Flip-Flop Using NAND Gate in VI Model4.3. Design of S-R Latch Using Simulink in MATLABThe Matlab Simulink ’s model of S -R latch flip-flop is depicted in Fig.11. The model is developed in a graphical user-friendly environment known as Simulink.QQ'SQ'QQ Q'R -+VV.S.-+VVf(x)=0SolverQ, Q'S PS PS-SS PS PSG2G15V0VFig.11. MATLAB-Simulink Model of S-R Latch4.4. Clocked R-S Flip Flop VI ModelIn Fig.12, LabVIEW VI model for clocked RS Flip-Flop is depicted. This shows the analysis report for the clocked RS VI model, where light green colour shows the logic 1 and blackish colour shows the logic 0.Fig.12. VI Model of Clocked RS Flip-Flop4.5. VI Model of RS Flip-Flop Consists NAND GatesThe VI model of RS flip-flop using universal NAND gate has designed and depicted in Fig.13.Fig.13. VI Model of RS Flip-Flop Using NAND Gate4.6.VI model of JK Flip-FlopThe VI LabVIEW model of JK flip-flop VI is depicted in Fig.14, consists J, K as inputs and clock as the control variable, Q and Q’ two outputs. An output of J-K flip-flop is a function of inputs and present state of the flip-flop.Fig.14. VI Model of JK Flip-Flop Using NAND Gates4.7.VI Model of D Flip FlopsD stands for a delay in the input signal, and the D flip-flop as VI model in LabVIEW using AND, NOR, NAND gates has been depicted in Fig.15.Fig.15. VI Model D Flip-Flop Using AND, NOR Gates and another model using NAND gates4.8. VI Model T Flip-FlopT stands for toggle and T flip-flop is modified version of JK flip-flop, depicted in Fig.16.Fig.16. VI Model of T Flip-Flop4.9. J-K Flip Flop Using MATLAB-SimulinkThe Simulation model of the J-K flip-flop in MATLAB-Simulink is designed and depicted in Fig.17.Q'S-V-VFig.17. MATLAB Simulink Model of J-K Flip Flop4.10.VI Model of Master Slave JK Flip-FlopVI model of master-slave JK flip-flop using LabVIEW has been depicted in Fig.18.Fig.18. VI Model of Master Slave JK Flip-Flop5.Results And ConclusionIn Fig.19, Output simulation result of VI.Model of SR latch composite of NOR gated depicted in Fig.8. From the VI.Model of NOR-based l S-R latch, it is obeserved, input S-R tempted the output Q and Q’.∙First Observation: If S is kept high and R low, the output Q is high and Q’ is low∙Second Observation: If S and R both kept low, out remain the same pervious state.∙Third Observation: If S keep low and R at high, result output Q goes to low and Q’ become high.∙Fourth observation: If both input S and R are high then both of output low as shown in Fig.21, clearly it is undefined state of S-R latch.Fig.19. Simulation Output of SR flips-flop using VI.ModelIn Fig.22, output simulation result of VI.Model of SR latch composite of NAND gates depicted in Fig.9. The Logical input to R and S is 0 or 1, predict Q and Q’. It is observed in Fig. 21, R kept high, and S low, the output Q is high and Q’ is low. Secondly, when both of inputs S-R are high, output remains as previous state. Thirdly, if R is low and S high, then output Q high and Q’ low as per observation from Fig. 19, Moreover, if both of R-S kept low, turns both output high, which is a case of the undetermined.Fig.20. Clocked RS Flip Flop Fed with Low Clock and High Clock, Simulation Output of the Low ClockIn Fig.21, simulation output result of VI.Model of R-S flip-flops is depicted. Firstly, the flip-flop is analyzed for a clock of the state. It is obesreved that if clock is low, output does not change with the change in inputs R-S as clear from Fig. 21(a). The generic R-S flip-flop operation took palace when the clock kept high as shown in Fig.21 (b). The working of the R-S flip flop as according to change in R-S inputs, output is obviousely observed in Fig. 21(b). First obervation, R kept high and S low, the output Q is low and Q’ high, Second observation, if both input kept low then output remain same as according to pervious state.Thirdly, if R is low and S high, then the output Q turns h igh and Q’ become low as per obse rvation. Fourthly, if both input change to high, then the output Q and Q’ become low which is an undefined condition of S-R flip-flops.(a)Clock off(b)Clock OnFig.21. Front Panel logical analysis of Clocked RS Flip-Flop using NOR GatesFig.22. Front Panel VI Model of RS Flip-Flop Clocked using NAND gatesSimulation output result of R-S flip flop is concluded in Table 4.Table 4. RS Flip-Flop Truth Table verified using LabviewS. No. RS Flip-FlopClock S, Input R, Input Q, Output Q’, Output. 1 0 0 0 1 0. 2 0 1 0 1 0. 3 0 0 1 1 0. 4 0 1 1 1 0. 5 1 0 0 1 0. 6 1 0 1 0 1.7 1 1 0 1 0.8 1 1 1 1 1The simulation output of J-K flip-flop of VI.Model on the execution of Fig.14 is depicted in Fig.23.(a)VI Model (Front Panel) JK Flip-Flop (Clock off)(b)VI Model (Front Panel) JK Flip-Flop (Clock on)Fig.23. Simulation Results J-K Flip-flop VI.ModelObservations of Fig.25 are depicted in Table 5.Table 5. JK Flip-Flop Truth Table verified using LabviewS. No. JK Fli-FlopOutput. 1 0(off) 0 0 1 0. 2 0(off) 1 0 1 0. 3 0(off) 0 1 1 0. 4 0(off) 1 1 1 0. 5 1(on) 0 0 1 Q n. 6 1(on) 0 1 0 1.7 1(on) 1 0 1 0.8 1(on) 1 1 1 Q n’The characteristics behavior of D flip-flop is depicted in Fig.24. It is versatile memory element used in counter designs.Fig.24. VI Model (Front Panel) of D Flip-FlopIn Fig. 25, the output simulation result of S-R Latch composite of NAND gates designed in MATLAB-Simulink, Fig.11 is depicted.(a)S=1 and R=0(a) (b) S=0 and R=0 (c) S=1, R=1 (d) S=0, R=1Fig.25. S-R Latch Simulink Simulation OutputIn Fig.26, Simulation output result J-K flip modelled in MATLAB Simulink is depicted. It is noticed that in first observation by keeping J=0 and K=0, the output are high for Q’ and low Q. Now different combination of input-output is determined their representation clearly depicted in Fig.29.(a) Simulation output at J=0, K=0 (b) J=1, K=0 (c) J=0, K=1 (d) J=1, K=1Fig.26. Output Result MATLAB Simulink Model of J-K Flip-flopOperations of flip-flop circuits are verified using the LabVIEW and MATLAB. Different flip-flops are explained with their characteristic table in theoretically and virtually in VI models and MATLAB Simulink models. A student centeric learning is developed, to create the interest of the student in the modeling of digital circuits and systems and in horizontal and vertical curricula for the different domain of subjects at the graduate level and postgraduate level. It is also observed that it is easy to study flip-flops in LabVIEW than MATLAB. References[1]Blackslee, Thomas R., Digital Design with Standard LSI and MSI, John Wiley, New York, 1979.[2]John F. Wakerley, Digital Design Principles and practices, Pearson, 3rd edition, 2001.[3]Simulation: An Enabling Technology in software Engineering Alan M. Christe.[4]Studying the Role of Simulation in Developing Students’ Statistical Reasoning, Andrew Zieffer, andJoan B. Garfield.[5]National Instruments, Labview, /labview/.[6]Elbert Pual Malvinoand Donal Leach, Digital Principles and Applications, 4th Edition, Tata McGrawHill Publishing Company Ltd., New Delhi, India, 1991.[7]Digital Integrated Electronics, Herbert Taub, Donald Schiling, Tata McGraw hill, 6th reprint, 2010.[8]Morris Mano, Digital Logic and computer Design, PHI Learning Private Limited New Delhi, 1979.[9]Teyana, Interactive Web based Laboratories in Digital Electronics, International Conference onEducation and e-learning Innovation, vol.1, pp 1-5, 2012.[10]R.P.Jain, Digital Electronic, Tata McGraw hill Education, 4rd edition, (2010).[11]Blackslee, Thomas R., Digital Design with Standard LSI and MSI, John Wiley, New York, 1979.[12]J.A. Fran Cisco, A.D. Castro, and B. Christian, Course on Digital Electronics Oriented DescribingSystem in VHDL, IEEE Transactions on Industrial Electronics, Vol. 50, pp 3308-3316, 2010.[13]Yap Wing Fen, Luq Man Al Hakim Mohamad Sabri, Integration of LabVIEW for Novel InteractiveLearning Courseware on Digital Electronics, IJIER, Vol.2 , Issue 11, pp 156-163, 2014.[14]Professor Barry Paton, “Fundamentals of Digital Electronics” using LABVIEW, March 1998 edition,Part Number 321948A-01.Author s’ ProfilesMittarpal is working as faculty in Department of Electronics and CommunicationEngineering, Bhagat Phool Singh Women University, Sonipat Haryana, India. His area ofspecialization includes Nano Science and Technology, Electromagnetic Wave Theory,Antenna Wave Propagation, Electronic Device and Circuits, Digital Circuit Systems, AdvanceDigital Communication, Advance Digital Signal Processing, Design and Simulation, MatlabProgramming, Simulink-G-programming, PV Module Simulation.Naresh Kumar was born in Haryana, India, on August 15, 1985. He received his PolytechnicDiploma in Information Technology from Board of Technical Education, Haryana in 2004. Heobtained his B.Tech in Electronics & Communication Engineering from Punjab TechnicalUniversity, Punjab in 2008. He obtained his Master in Technology (M.Tech.) in ElectricalEngineering. Specialization in Electronics from YMCA University of Science & Technology,Faridabad, Haryana in 2011. He worked in Aravali college of Engineering & Management, Faridabad, Haryana from 2011 to 2014. From August 2014 to till date, he is working in SGT University, Gurugram, Haryana. His research interests includes VLSI circuit design, develop embedded system withvarious microcontrollers etc.Priyanka Anand received her B.E. in Electrical Engineering in 2004, M.Tech in ElectricalEngineering (Instrumentation & Control) in 2007 and currently pursuing Ph.D in ElectricalEngineering from IKG Punjab Technical University, Kapurthala, Punjab, India. She is presentlyworking as an Assistant Professor in the Department of Electronics and CommunicationEngineering in Bhagat Phool Singh Mahila Vishwavidyalaya, Khanpur-Kalan, Sonepat,Haryana, India and having teaching experience of about 12 years at undergraduate andpostgraduate level. She has published more than 20 research papers in international, national journals and conference proceedings. In addition, she is also the life member of Indian Society of Technical Education (ISTE). Her area of interest includes modeling and simulation, soft computing and renewable energy based hybrid system.Sunita Rani was born in Haryana on October 14, 1989. She received her B.Tech. Degree inElectronics & Communication Engineering from Ch. Devi Lal University, Sirsa, Haryana inthe year 2011. She received her Master in technology (M.Tech.) in VLSI Design from YMCAUniversity of Science &Technology, Faridabad, Haryana in 2014. Presently she is working inthe Department of Electronics and Communication Engineering in Bhagat Phool SinghMahila Vishwavidyalya, Khanpur Kalan, Sonepat, Haryana, India. Her area of interest is design VLSI chip and she also works for Quantum Dot Cellular Automata technology for VLSI design.How to cite this paper: Mittarpal, Naresh Kumar, Priyanka Anand, Sunita,"Realization of Flip Flops using LabVIEW and MATLAB", International Journal of Education and Management Engineering(IJEME), Vol.7, No.5, pp. 7-22, 2017.DOI: 10.5815/ijeme.2017.05.02。

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I.J. Education and Management Engineering, 2016, 5, 32-39Published Online September 2016 in MECS ()DOI: 10.5815/ijeme.2016.05.04Available online at /ijemeRegression Test Suite Prioritization using Residual Test CoverageAlgorithm and Statistical TechniquesAbhinandan H. Patil a*, Neena Goveas a, Krishnan Rangarajan ba BITS Pilani, Goa CS and IS Dept,Goa,Indiab CMRIT, CSE Dept,Bangalore, IndiaAbstractRegression test suite study has been research topic for decades. In this paper we investigate the Regression test suite prioritization using residual test coverage algorithm for white box testing and introduce new statistical technique for black box testing. Our contribution in this paper is mainly problem solution to breaking the tie in residual coverage algorithm. Further we introduce new metric which can be used for prioritizing the regression test suite for black box testing. Towards the end part of the paper we get down to implementation details explaining how this can be done in the industrial or research project. The intended readers of this paper are developers and testers in the research field and practitioners of software engineering in the large scale industrial projects.Index Terms: Residual Test Coverage Algorithm, CodeCover, Test Execution Time, Statistical Techniques.© 2016 Published by MECS Publisher. Selection and/or peer review under responsibility of the Research Association of Modern Education and Computer Science.1.IntroductionWe begin introduction of this paper with the statement, “Developer is also tester and vice versa” of Aditya P. Mathur [1]. A versatile software professional or researcher works in multiple capacities in a typical development life cycle. Missing exposure to either development or testing is partial view of the product development life cycle. The tester without development knowledge can contribute little towards the white box testing and developer without testing knowledge means quality compromise from the product perspective. With this precursor, it is clear that the paper is for both the testers and developers.Regression testing is discussed at lengths in several papers. The main topics of research are: Test selection, minimization and prioritization. There are two measures of coverageRequirement coverage. In this method we trace the test cases to requirements and ensure that all the * Corresponding author. Phone: +919886406214E-mail address: Abhinandan_patil_1414@requirements are covered. The requirement specification document itself serves as test oracle.∙Code coverage. In this method the measures such as statement coverage, branch coverage, loop coverage etc are checked to ensure that nothing is missed as part of testing.Requirements coverage is not the topic of discussion in this paper. It’s the latter which will be focused as the same metric is used in the white box testing and black box testing approaches discussed in the further sections. If P is the product code before bug fixes and enhancement and P’ is the product code after the modification, we can denote the corresponding test suites as T and T’ respecti vely. Now, one way to visualize T is as collection of obsolete, redundant and valid test cases. In other words T is collection of {obsolete, redundant, valid} test cases. The T’ will encompass {valid, newly added test cases}.There are different schools of thoughts when it comes to selecting regression tests between successive releases. Each with their own set of advocates. As Aditya P. Mathur aptly classifies [1], the philosophy for each of these categories is very different. The categories are:∙Test all: Brute force method with long execution cycles. Most widely used technique in the commercial world combined with automation of regression testing∙Random selection: Sampling of the test cases. Better than no regression testing at all. Test cases are picked from the test suite except obsolete test cases randomly.∙Selecting modification traversing tests: Assumes the tester to have the knowhow of the complete product code. Better than test all and random selection process. Usually the testers classify the test cases in buckets where they put related test cases in a given bucket. Depending upon how the test cases are chosen this mode of testing may or may not yield good results.∙Test minimization: Pruning of the test suite by dropping the test cases with similar product trace code as they are redundant. This results in new reduced size of the regression test suite.∙Test Prioritization: Assumes that the test cases can be ranked on the basis of certain criteria.It is the last school of thought which will be investigated in this paper. Regression test suite prioritization is must when there is crunch of resources and time.In some organizations, the organizations may choose combination of the approaches mentioned above. Large execution time means test all approach and may mean drain of resources and time. Therefore good amount of research has already gone in optimizing the regression test suites.In this paper we look at test prioritization using the approach which is implementable given time. The paper can be broadly classified into following sections:∙Residual test coverage algorithm enhancements for regression test suite prioritization using white box testing.∙Statistical techniques for regression test suite prioritization using black box testing.∙Process flow at the implementation level which can aid the above two processes.∙Case study of coverage tool to explain how metrics of choice can be extracted.As already explained earlier, if the current test suite is visualized as the collection of {obsolete, redundant, valid test cases}, the test suite for new version of the product will be {valid test cases, newly added test cases}. The new test cases added are with reason. They cover either the newly added functionality or they cover the modified functionality. In this case some of the valid test cases may become redundant or obsolete. In rare scenarios the obsolete test cases become valid test cases when the removed functionality is added back for some reason. In variably the newly added test cases go through the review process depending upon the organizations process in place. They are always executed. The remaining test cases need to be prioritized. We consider modified test cases as new test cases. Further, the approaches mentioned in further sections for black box and white box testing assume the historical data of the test suite is maintained between successive releases.That is the coverage and execution time data of current suite becomes the reference data for the next build of the product. Since the new test cases are always executed, we are not ranking them among themselves. This means the test cases will be new test cases followed by prioritized test cases.Since the newly added test cases will be far less compared to valid test cases taken from the previous release the following approaches should work in practical setup. The gain of ranking the new test cases is minimal as they are executed mandatorily.2.Residual Test Coverage Algorithm Enhancements for white Box TestingWe assume the reader of this paper is aware of residual test coverage algorithm. The concept behind the algorithm is explained nicely in the reference book [1]. The problem of breaking the tie is left to readers as an exercise. This is the problem definition which we will investigate. We there-fore modify the algorithm such that the random test selection is weeded out completely at all the steps.The newly introduced parameters and steps by us are in italics. The modified algorithm looks as follows: Algorithm for prioritizing the regression test suite post modification.Input T’: Set of regression tests for the modified program P’.entitiesCov: Set of entiti es in P covered by tests in T’.cov: Coverage vector such that f or each test t Ɛ T’, cov(t) is the set of entities covered by executing P against t.executionTime: executionTime(t) is the time taken by the test case t Ɛ T’ to complete the execution.linesO fCodeTraced: linesOfCodeTraced(t) is the total lines of product code covered by the test case t Ɛ T’ during execution.Output PrT: A sequence of prioritized test cases such that (a) each test case belongs to T’, (b) each test in T’ appears exactly once in PrT, and (c) tests in PrT are arranged in the ascending order of cost.Step 1:X’ = T’. Find t Ɛ X’ such that │cov(t)│≥ │cov(u)│for all u Ɛ X’, u ≠ t.Step 2:Set PrT = <t>, X’ = X’\{t}. Update entitiesCov by removing from it all entities covered by t. Thus entitiesCov=entitiesCov\cov(t).Step 3:Repeat the following steps while X’ ≠ Φ and entityCov ≠ Φ.pute the residual coverage for each test t Ɛ T’. resCov(t) = │ent itiesCov \ (cov(t) ∩entitiesCov│.resCov(t) indicates the count of currently uncovered entities that will remain uncovered after having executed P against t.3.2.Find test t Ɛ X’ such that resCov(t) ≤ resCov(u), for all u Ɛ X’, u ≠ t. If two or more such tests exist thenfirst compare │cov(t)│, if there is tie again look for executionTime(t) and linesOfCodeTraced(t) and select the one with high │cov(t)│, linesOfCodeTraced(t) and least executionTime(t).3.3.Update the prioritized sequence, set of tests remaining to be examined, and entities yet to be covered bytests in PrT. PrT = append(PrT, t), X’=X’\{t}, and entitiesCov = entitiesCov\cov(t).Step 4:Append to PrT any remaining tests n X’. All remaining tests have the same residual coverage which equals │entitiesCov│. Hence these tests are tied. Now follow exactly what was done in step3.2. That is when two or more tests tie look for test case with higher value of │cov(t) │and linesOfCodeTraced(t) and least executionTime(t).End of AlgorithmReaders of this paper are strongly advised to trace the example 9.29 in the text book again in conjunction with the algorithm.This algorithm needs bit of explanations in plain English as the notations of Mathematics often do not go well with the computer science practitioners. In simple terms we start with the test case which covers maximum entities to begin with. Then we choose the test case which will run the maximum uncovered entities that are not already covered by previously run test case. The second step is repeated till there are no more unique entities to be covered. Of course when we encounter two or more test cases with the same cost, we go ahead with the one which has high entities coverage, high loc trace and least execution time. Once all the entities are covered, we choose to run the remaining test cases with the same criteria i.e. high entities coverage, high loc trace and least execution time. The logic behind this is, always choose the test case which covers maximum entities, traces maximum lines of code in least amount of time.In the introduction section we mentioned about same person wearing different hats of developer and tester. This is with a reason. White box testing is by or with the help of developer.3.Statistical Approach for Prioritization of Test Cases for Black Box TestersAlthough the approach used in section 2 is nice, it involves the product code dissection at class, function level. Therefore we explain a very simple approach which can be used by regression team for prioritizing the test cases when there is no sufficient time to understand and implement the algorithm. As we shall explain in section 4, this approach can be implemented with minimal probes in the test case and minimal tweaking of the tool used for gathering the coverage data.We explain this directly taking the example. Please have look at the table below.Table 1. Table for Calculating the New MetricWhere Nmi = LOCProd(1)(LOCTest X ᴛ )The logic needs bit of explanation. We are using the logic that the test case which traces maximum lines of product code with least number of lines in itself in least amount of time is efficient. We sum up the numbers Nmi short for New Metric to get the picture at the test suite level.However this logic assumes there are no redundant test cases in test suite.4.Coverage Tools: Codecover a Case StudySince we have used the terms such as product lines of code traversed and lines of the code in the test case we need a tool to measure the same. The obvious choice is code coverage tools. There are plenty of coverage tools for code coverage [3]. The choice of tool for particular project depends upon various criteria [3]. We had investigated the CodeCover earlier. Its most suited tool for Java projects since it comes with EPL license and most importantly, it is open source software. It is backed by courteous team of developers who support the tools issues. The tool can be extended and tweaked as per the needs of particular project. Although we have other coverage criteria such as combinatorial coverage at researchers disposal today [5, 6], we need to revisit the traditional coverage criteria code coverage often. Although one of our previous papers [4] attempts to prioritize the test suite, the focus in this paper is completely different. The CodeCover gives various metrics such as statement coverage, branch coverage, loop coverage, MC/DC coverage etc at test case level as well as test suite level. There are provisions to call the Application Programmers Interface (APIs) of this tool from outside. The flexibility to call the APIs from external environment can mean a lot to implement the topics explained in this paper.In further sections we explain how the APIs could be called from test setup to gather the required data and how it can be combined with other parameter of interest viz. execution time.The CodeCover already supports two languages as diverse as Java and Cobol. This is being mentioned for reason. That is tweaking of the tool is not effort intensive.5.Process Flow for Collecting Metrics of Choice.Fig.1. Process Flow for Collecting the Metrics of Choice.The figure 1 needs bit of explanation. We have been talking about gathering the product code traced and execution time of the test case while collecting the metrics of choice. The figure 1 depicts how this could be done in real life project.6.Advantages of Test Suite PrioritizationThe real advantages of spending effort in test suite prioritization can be explained very easily. Imagine a project which maintains 1000+ test cases. Further, depending upon the system, it could take few days to execute the test cases. These kinds of systems are real in wireless telecom sector. Imagine the period of field support where the developers and testers have to quickly give the fixes for field support issues. The product team cannot afford the time required. In such scenarios it is very advantageous to have the ranked test suite where the tester could decide to end the test case after 500+ test cases. The savings could be substantial amount of time.7.ConclusionIn this paper we presented two approaches mainly for the cases when the testers want to use the black box or white box testing. Each approach is with its own benefits and drawbacks. Either of the approach can be followed depending upon resources and time.We presented how the metrics being discussed in either of the approaches can be extracted in practical setups. The CodeCover synonymous to Java coverage although incorrect is discussed as case study to explain the fact that the metrics introduced in the algorithm or in the new approach are not difficult to extract.8.Future WorkWe will investigate if these concepts can be applied to ongoing commercial project. We shall investigate how the concepts could be improved upon further.Further we investigate how the concepts explained in this paper can be applied to integrated test environments which we investigated earlier [7].AcknowledgementsOur sincere thanks to the open source software’s mentioned in the papers without which the practical aspects of the tools usage would not have been possible.Our sincere thanks to head of the department computer science and information systems who in the capacity of academic council members of the research work being carried out at BITS Pilani, Goa, suggested to look at the problems related to Regression testing. The same was studied and this paper documents the findings.Our sincere thanks to the authors of the books mentioned in the reference section.References[1]Aditya P. Mathur. 2013. Foundations of software testing, 2nd edition text book. University of Purdue.[2]Paul C.Jorgensen.2013.Software testing a craftman’s ap proach, 3rd edition, text book.[3]Abhinandan H. Patil et al.2013. CodeCover: A Code Coverage Tool for Java Projects, ERCICA Elsevierpublications.[4]Abhinandan H. Patil et al.2014.CodeCover: Enhancement of CodeCover, ACM SIGSOFT SEN, March2014 issue.[5]Abhinandan H. Patil, Neena Goveas and Krishnan Rangarajan.2015. Test Suite Design Methodologyusing Combinatorial Approach for Internet of Things Operating Systems, Scientific Research Publishing, Journal of Software Engineering and Application.[6]Abhinandan H. Patil, Neena Goveas and Krishnan Rangarajan.2015. Re-architecture of Contiki andCooja Regression Test Suites using Combinatorial Testing Approach, ACM SIGSOFT SEN, June 2015 issue.[7]Abhinandan H. Patil, Preeti Satish, Neena Goveas and Krishnan Rangarajan.2015. Integrated TestEnvironment for Combinatorial Testing. IEEE conferences, IACC.[8]CodeCover Home Page=/.[9]S. Elbaum, A. G. Malishevsky and G. Rothermel. Test case prioritization: A family of empirical studies.IEEE Trans.[10]M. J. Harrold, J. A. Jones, T. Li, D. Liang, A. Orso, M. Pennings, S. Sinha, S. A. Spoon and A.Gujarathi. Regression test selection for java software. In OOPSLA ’01: Proceedings of the 16th ACM SIGPLAN conference on Object Oriented Programming, Systems, Languages, and Applications, pages 312–326, New York, NY, USA, ACM Press 2001.[11]J. A. Jones and M. J. Harrold. Test-suite reduction and prioritization for modified condition/decisioncoverage. IEEE Trans.Softw. Eng. 2003.[12]M. Lyu, J. Horgan and S. London. A coverage analysis tool for the effectiveness of software testing.IEEE Trans. on Reliability 1994.[13]G. Rothermel, M. J. Harrold, J. Ostrin and C. Hong. An empirical study of the effects of minimizationon the fault detection capabilities of test suites. In ICSM ’98: Proceedings of the International Conference on Software Maintenance, Washington, DC, USA, IEEE Computer Society, 1998.[14] A. Srivastava and J. Thiagarajan. Effectively prioritizing tests in development environment. InISSTA ’02: Proceedings of the 2002 ACM SIGSOFT International Symposium on Software Testing and Analysis, pages 97–106, New York, NY, USA, ACM Press, 2002.[15]T.W.Williams and M. R.Mercer. Code Coverage, what does it mean in terms of quality. IEEEConference Publications 2001.[16]K. Sakamoto and H.Washizaki. Open Code Coverage Framework: A Consistent and FlexibleFramework for Measuring Test Coverage Supporting Multiple Programming Languages. IEEE Conference Publications 2010.[17]Y. Adler and N. Behar. Code Coverage Analysis in Practice for Large Systems. IEEE ConferencePublications 2011.[18] F. Del Frate and P. Grag. On the correlation between code coverage and software reliability. IEEEConference Publications 1995.[19]S. Berner and R. Weber. Enhancing Software Testing by Judicious Use of Code Coverage Information.IEEE Conference Publications 2007.[20]J. Lawrence and S. Clarke. How well do professional developers test with code coverage visualizations?An empirical study. IEEE Conference Publications.[21]W. E. Wong and Yu Qi. Effective Fault Localization using Code Coverage. IEEE ConferencePublications 2007.[22]R. M. Karcich and R. Skibbe. On software reliability and code coverage. IEEE Conference Publications1996.[23]Zheng Li, Mark Harman and Robert M. Hierons.2007. Search Algorithms for Regression Test CasePrioritization, IEEE transactions on Software Engineering.[24]Siavash Mirarab, Soroush Akhlaglv and Ladan Tahvildari.2012. Size Constrained Regression Test CaseSelection using Multicriteria Optmization, IEEE transactions on Software Engineering.[25]Luay Tahat, Bogdan Korel, Mark Harman and Hasan Ural.2011.Regression Test Suite Prioritizationusing System Models. Wiley online Library.Authors’ ProfilesAbhinandan H. Patil has 10+ years of experience in wireless telecom domain. His researchinterests include Software engineering, Wireless networks, Automation tools for wirelessnetworks, Simulator tools for wireless networks, Verification and validation. His previousindustrial exposure spans across companies like Motorola, Kshema Technologies (MPhasisnow), Infosys.He is a research student at BITS Pilani, Goa.Neena Goveas is Associate Professor at CS&IS department of BITS Pilani, Goa. She holdsPh.D from IIT, Bombay.Her research interests include Wireless Sensor networks, Mean field and computationalapproaches to magnetic systems, Thermodynamic properties of magnetic systems andNetwork Science.Krishnan Rangarajan is Professor in CSE department at CMRIT, Bangalore. He holdsPh.D from University of Central Florida.His research interests include Computer Vision, Software engineering topics like Testing,Usability, Security, Software architecture.How to cite this paper: Abhinandan H. Patil, Neena Goveas, Krishnan Rangarajan,"Regression Test Suite Prioritization using Residual Test Coverage Algorithm and Statistical Techniques", International Journal of Education and Management Engineering(IJEME), Vol.6, No.5, pp.32-39, 2016.DOI: 10.5815/ijeme.2016.05.04。

Model 8500Angle Position Indicator• 0.01° Resolution• 0.03° Accuracy on each of the two independent channels • Auto-compensation of phase shift errors maximizes accuracy• Auto-ranging adjusts to any line-to-line voltage of 10-100V•Optional IEEE-488 interface for remote sensing and controlThe Model 8500, API is a Synchro/Resolver-to-digital converter that performs high quality analog-to-digital conversions of Synchro or Resolver data.The API transmits the converted digital representation of the analog data simultaneously to the following locations:• The front panel display which uses six seven-segment LED planar information displays. • The BCD outputs of the rear panel parallel I/O connector.• The optional IEEE-488 interface bus, which has full MATE compatibility.The Model 8500 is housed in a 9 1/2-inch wide rack panel and is packaged primarily for computer controlled or fixed installation applications.Front Panel Description: The front panel contains a group of controls and indicators including a power ON/OFF switch, a set of function switches and coordinated LED indicators, a set of input terminals, and a display for angular data, degree/minutes, and IEEE-488 interface status information. (See table on next page)Rear Panel Description: The rear panel provides an ac input receptacle (J2), a parallel I/O connector (J1), and an 8-position mode DIP-Switch with appropriate instruction label. An IEEE-488 ADDRESS switch and connector (J3) are optionally available. (See table on next page)Power Requirements: The API operates with either 115 V ac or 230 V ac, 47 to 440 Hz power source. Power may be applied from the line cord or parallel I/O rear connector J1. Refer to tables, J1 power connections and switch selection of voltage and power sourceInternal Power Connections: All API models are factory set for 115 V AC line cord operation (line cord is supplied), but can operate using 115 V AC or 230 V AC as selected by an internal switch. In addition, a rear power connector, which also accepts 115 V/230 V AC, can be used in place of the line cord by selecting the position of an internal switch (see pin designations).SpecificationsItem Specification Input SpecificationsInputchannels Signalinputs 2 (selectable)Automatic line-to-line tracking, Synchro orResolver.10 to 100 V L-L, 47-440 Hz (F2, option 2) or 360 to 1200 Hz (F2, option 4).Signal input impedance Reference levels 250 k ohms (minimum)1 to 115 V rms, all frequency ranges.(All Synchro or Resolver data must be derived from this reference.)Reference input impedance Power requirements 100 k ohms (minimum) 115/230 V rms_+ 10% 47 to 440 Hz, 20 VAData Freeze DF DFFreeze Track+5 V 0 V or open0 V +5 V or open(Display and output frozen; internalcircuitry continues to track signal.)Channel Remote Program 0 V or GND=CH1, +5 V or OPEN=CH2 Output SpecificationsDisplayReadoutresolution Digital output dataDigital output levelLogic1LogicConverterBusy 5 decimal digits, 0.56-inch high LED indicators for channel and remote0.01 degree or 1 minute (F2, option 2 or 4) 5 decades of BCD digits (1,2,4,8 code)+3.9 V minimum, 4 standard LS TTL loads 0.1 V maximumTTL compatible (pulses are present when converter is busy)Performance SpecificationsAngular Accuracy 0.03 degreesNorth Atlantic Industries, Inc. . 11-06-01SpecificationsItem SpecificationAngular Resolution 0.01 degreesAngular Range 0 to 359.99 degrees or 0 to 359 degrees 59minutes; or, -179.99 to +180 degrees or -179 degrees 59minutes to +180 degrees 00 minutes (F2=2 or 4) Auto phase correction Automatically corrects for signal phase shift up to_+ 80degrees.Trackingspeed Selectable:Lo speed = 180 degrees/sec with no tracking error, 47-440 Hz (F2, option 2)Hi speed = 1800 degrees/sec with no tracking error, 360-1200 Hz (F2, option 4)Settling time Dependent on tracking speed selected and frequency range:Less than 1.5 seconds for 180 degrees step change, Lotracking speed and 47-440 Hz (F2, option 2).Less than 1.0 seconds for 180 degrees step change, Hitracking speed and 360-1200 Hz (F2, option 4). Velocity output:HI Tracking rate 2.85 mV dc/degree/second (nominal)LO Tracking rate 28.5 mV dc/degree/second (nominal)Operating modeFaultindications Lamptest Track onlyNo reference present: all 8s displayedNo Synchro or Resolver connected or input line-to-line voltage is too low: display is blanked.Over velocity: "o" displayed to left of angle displayOptional IEEE-488 MATE relay closureDisconnect reference to display all 8s or apply logic "0" to J1-38.Mechanical Specifications Front Panel Color (See figure 2-1 Outline and Dimension Drawing, API Model 8500)Semi-gloss gray, 26440 per Fed-Std-595 window area black #27038 per Fed-Std-595Markings Semi-gloss black enamel 27038 per Fed-Std-595; PantoneWarm Red U (warnings and logo only); White #27875 perFed-Std-595Size 9.5" W x 1.75" H x 12" DWeight 4 lbs. (maximum)Operating Temperature 0-50o CNorth Atlantic Industries, Inc. . 11-06-01ORDERING INFORMATIONFeatures and Options:To identify the Model 8500 options, a three-digit number is assigned in accordance with table below.For example, the Standard Model 8500 with half rack mounting (1), 47 Hz to 440 Hz frequency selectable display (2), and parallel interface (1) would have an option number of F121.8500-F 1 2 1F1F2F3No. Feature OptionsF1 Configuration Options 1. Panel mount, half rack2. Bench use (includes front terminals and stand)3. Panel mount, full rackF2 Frequency and Display 2. 47-440 Hz, selectable display4. 360 Hz to 1200 Hz, selectable displayF3 Interface 1.Parallelonly2. Parallel and IEEEAccessories:The API can be ordered with mounting adapters for mounting either one or two units in a standard 19-inch equipment rack. The table below describes full rack and tandem full rack mounting accessories:Type of Mount Description NAI P/N Full Rack Mounting Mounts one unit in 19-inch rack 300697Tandem Full Rack Mounting Mounts two units side by side in 19-inchrack300698The parallel I/O 50-pin mating connector, J1 is supplied by North Atlantic Industries (NAI P/N 783718) but operator must make cable assembly. It consists of the following parts:Description AMP P/N QtyShellClamp Retainer Pins 205211-1205732-1205980-166569-311250North Atlantic Industries, Inc. . 11-06-01Front Panel Controls and IndicatorsControl/Indicator FunctionPWR push button Alternate Acting Switch. Turns power on and off (push button in: power on;push button out: power off).REM push button Alternate Acting Switch. Selects remote operation of the API (push buttonin: Remote; push button out: local).CHAN push button Alternate Acting Switch. Selects input channel (push button in: CH 1; pushbutton out: CH 2).HOLD push button Momentary Switch. Push in to freeze display and output data.REM LED When ON, indicates the API is in remote operation.CHAN LED When on, indicates Channel 1 is selected.When off, indicates Channel 2 is selected.CAUTIONTerminals S1, S2, S3, S4, and REF HI and LO are directlyconnected to the transformer inputs and must not be used ifJ1 inputs are used. Refer to table 2-1, J1 pin connections.S1,S2,S3,S4Accepts Synchro or Resolver input signals (bench units only).TerminalsAccepts reference input signal (bench units only).REF HI and LOTerminalsRear Panel DescriptionControl/Indicator FunctionInput Power Receptacle Power cable connector (J2) for 115 V ac or 230 V ac input.ADDRESS Switches ADDRESS DIP switches set unit address for IEEE bus.Parallel I/O Connector Provides API interconnection with external systems, powersources, etc. Refer to table 2-1.MODES Switch 8-position DIP switch which controls selectable modes. Referto paragraph 3-3.3.IEEE-488 Connector (optional) Connects IEEE-488 standard I/O bus to unit.North Atlantic Industries, Inc. . 11-06-01Mode Switch SW2Switch NumberSwitchSignal NameSwitch Position1 01 CH1 SYN Channel 1 in Resolver mode or forremote control of Channel 1.Channel 1 in Synchro mode.2 CH2 SYN Channel 2 in Resolver mode or forremote control of Channel 2.Channel 2 in Synchro mode.3 INT/EXTREF Selects auto phase correctedinternal reference.Selects external reference.4 Bandwidth(H/L) Selects low bandwidth (trackingspeed) or remote control of trackingspeed.Selects high bandwidth (trackingspeed).5 Deg/Min Selects 2 LSDs of display in minutesof arc. Selects 2 LSDs of display in hundredths of degrees.6 Display(U/B) Unipolar display.(0o to 359.99o) or remote control ofdisplay.Bipolar display_+ 180o.7 Sign Sign bit equals plus sign (+) in F2=2or 4 units. Sign bit equals minus sign (-) in F2=2 or 4 units.8 P/I Selects IEEE-488 interface forremote control Selects parallel interface for remote control.North Atlantic Industries, Inc. . 11-06-01J1 Pin DesignationsPin Function1 Power input Hi (internal switch enables pins 1 & 2; disables IEC power connector2 Power input loground3 Chassisground4 Digital(Channel 1)5 S16 S2 “ “7 S3 “ “8 S4 “ “9 R1 “ “10 R2 “ “Busy11 Converter12 .04° or 4’13 .01° or 1’14 .8° or not used15 .2° or 20’16 4°17 1°18 Channel 2 Synchro jumper (connect to pin 35 for channel 2 Synchro operation)19 NC20 Tracking HI/LO input21 S1 (Channel 2)22 S2 “ “23 S3 “ “24 S4 “ “25 R1 “ “26 R2 “ “27 Data freeze (DF)28 .02° or 2’29 .08° or 8’30 .1° or 10’31 .4° or 40’32 2°33 8°34 Channel 1 Synchro jumper (connect to pin 35 for channel 1 Synchro operation)35 Synchro jumper common36 Fault 1 (not used)37 Fault 2 (not used)38 Lamp Test39 Unipolar/Bipolar for F2=2 or 4(Built in Test Equipment)output40 BITE(analog)output41 VelocityFreeze(DF)42 Data(0=CH1, 1=CH2)Program43 Remotespare44 NC45 20°BCD Outputs46 40° “ “47 80° “ “48 10° “ “49 100° “ “50 200° or sign bit in bipolar “ “North Atlantic Industries, Inc. . 11-06-01。

S2-IIIProfessional Active Performance SystemUser Manual UM-Mel i n e S2-I I I-20180516Ve r B11. 2. 3. 4. 5. 6. 7. 8. 9. 10. Read the instruction first before using this product.Pay attention to all warnings.Obey all operating instructions.Do not expose this product to rain or moisture.Do not block any ventilation openings. Install according to instructions .Do not install this product near any heat source, such as , heater, burner, or any other equipment with heat radiation .Only use spare parts by manufacturer.Pay attention to the safety symbol on the of the cover.manual Please keep this manual for future reference Clean this equipment with a dry cloth.manufacturer's a supplied the outside SAFETY INSTRUCTIONSPLEASE READ THIS MANUAL FIRSTThank you for a buyin product. Read this manual first as it will help you operate the system properly. Please keep this manual for future reference.g WARNING:This product must be installed by professionals. When using hanging brackets or rigging other than those supplied withthe product, please ensure they comply with the local safety codes.The exclamation point within an equilateral triangle is intended to alert you to the presence of important operating and servicing instructions.ATTENTION: Don't refit the system or spare parts without being authorized as this will .void the warranty WARNING: Don't (such as candles) the equipment.place naked flames close to2S2-IIICONTENT4533334556667CONTENTFeatures Description Applications Frequency Response and THD Curve Curve AMPLIFIER MODULEINSTALLATIONMounting Accessories Installation Reference INTRODUCTIONTechnical Sheet2D DimensionTECHNICAL SPECIFICATIONAmplifier Module Product information is subject to change without prior notification. Please visit for the latest updates.3S2-IIIS2-IIIINTRODUCTIONApplicationsMultifunctional hallAuditorium Church Conference room Small performance FeaturesDescriptionProfessional Active Performance SystemCompact,portable and eye catching design.System is 1.8M high to deliver full,natural sound.12 2.75"full range and 2 25mm ×× Silk dome tweetervertical column speakers to ensure smooth sound coverage.Bi-amp module including DSP.Exclusive CLIK together connections,no cables required.Handle on back of subwoofer.Carry bags for system,ease of transportation.β3 Meline S2-III is a performance sound reinforcement system designed for musicians,meeting room presentation,DJ's etc for an audience up to 300.The three piece system is designed for quick and easy setup with new click together interconnecting speakers.The amplifier module is housed within the subwoofer.This bi-amp module includes DSP to enable superior performance. The active 3-way column speaker system Meline S2-III can be used for various PA applications. The individual components of the Meline S2-III(1 subwoofer module,2 column modules) can be connected so that the Meline S2-III is also ideally suited for mobile applications. Two class D amplifiers,each with a power of 400W RMS,are available for the low-frequency and the mid-high frequency ranges. Two audio units and two microphones can be connected to the 4-channel mixer unit. For sound adjustment and frequency splitting,the audio signals pass a digital signal processor(DSP)that also includes a signal limiter. ...AC INPUT 230V~50Hz,T5AL DONGGUAN 3G AUDIO TECHNOLOGY CO., LTD.S/N:Professional Active Performance SystemS2-III4S2-III12 53 4 6PROFESSIONAL ACTIVEPERFORMANCE SYSTEMS2-III789101617121314151819202122AMPLIFIER MODULEAmplifier Module1. Volume control for the input LINE IN(12)2. Volume control for the input MIC IN(11)3. Volume control for the input COMBI IN(15)4. Volume control for the input AUX IN(16)5. Control to adjust the strength of the low frequencies radiated by the subwoofer6. Control CONTOUR to define the level of the aurally compensated sound correction for the input LINE IN(12)7. Equalizer control for the signal of the input MIC IN(11), continuously adjustable between vocals(SING), neutral (FLAT)and speech8. Equalizer control for the signal of the input COMBI IN(15),continuously adjustable between neutral(FLAT),music and speech 9. Control CONTOUR to define the level of the aurally compensated sound correction for the input AUX IN(16)10. LED indicatorsON = Power indicator SIGNAL = Signal indicatorLIMIT = Limiter indicator:Lights up when the signal level is too high;the limiter will reduce the signal level to protect the speaker.11. MP3 music player module12. Input MIC IN(combined 6.3mm jack/XLR,bal.)to connect a microphone13. Stereo input LINE IN(combined 6.3mm jacks/XLR,bal.)to connect a signal source with line output level(e.g.mixer,CD/MP3 player)14. Output LINE OUT(XLR,unbal.)At this output,the signal of the input LINE IN(12)is available; either as a mono signal or only the signal of the right channel, can be selected by means of the selection switch(14).15. Switch to select the operating modeMONO = The speaker column reproduces the signal of the input LINE IN(12)monophonically;the monophonic input signal is available at the output LINE OUT(13).RIGHT = The speaker column reproduces the left channel of the input LINE IN;the input signal of the right channel is available at the output LINE OUT.16. Mono input COMBI IN(combined 6.35mm jack/XLR,bal.)to connect a microphone17. Stereo input AUX IN(RCA jacks and 3.5mm jack,unbal.)to connect a signal source with line output level18. Output MIX OUT(XLR,unbal.)to send the mixed mono signal to an additional amplifier,for example19. Output REC OUT(RCA)to connect a recorderAt this output,the mixed stereo signal is available.20. Support for the mains fuseAlways replace a blown fuse by one of the same type.21. Mains jack for connection to a socket(230V~50Hz)by means of the mains cable provided 22. Power switch115S2-IIIINSTALLATIONInstallation Accessories(Optional)Installation ReferenceReference A Reference B1.Meline S2-II BAG2.Meline S2-II EXTMeline S2-II EXT1. Place the subwoofer module on an even,horizontal surface(floor).2. Start with the column module where a 6.35mm jack is located on the upper side.Place the column module- turned by approx.20°to the left-onto the connector of the subwoofer module and then turn it to the right stop so that it is firmly engaged.3. Proceed in the same way to connect the second column module to the first one.4. If the tweeters located in the centre of the connected columns do not have the optimal height(ear's height), use the adapter piece Meline S2-II EXT(available as an option)to increase the height of the column modules.6S2-III20000100001000100502018010860708090100S e n s i t i v i t y (d B )50Frequency (Hz )36-36-108-180TECHNICAL SPECIFICATIONSpecificationFrequency response(-3dB):Max.SPL:Transducer:Input:Connector:Input impedance(line):Input level:Input overloading level: Wire connection: Heat radiation: Power cable:45Hz-20kHz 113dB/119dB(PEAK)2 8" Woofer,12 2.75" Midrange Unit ××T channel (MIC/COMBI/LINE) balanced input(XLR and 6.35mm jack)hree XLR for input, XLR for output20kohm balanced input, 10kohm unbalanced input pin 1: ground; pin2: signal +; pin3: signal -Forced air-cooled drives 090×400Dispersion(H ×V):2 25mm × Silk dome tweeterSafety voltage range: Amplifier power output:Cabinet: Handle: Painting:Cabinet dimension(W D H): ××Packing dimension :(W ×D ×H)Net weight:Gross weight:AC 220V-230V~50Hz/60Hz 800WRated impedance:4 OhmsFrequency response curve & THD curveLINE IN 775mVrms, AUX IN 200mVrms MIC IN: 20mVrms, COMBI IN: 40mVrms : : LINE IN Vrms, AUX IN 2VrmsMIC IN: 200mVrms,COMBI IN: 400mVrms : 3.5: 23.5kg(51.7 lbs)25.5kg(56.1 lbs)2504001726mm(9.815.768.0in)××××615355705mm(24.214.027.8in)××××LF:200W,M HF:30W F:180W,Power:One channel (AUX) unbalanced input(RCA and 3.5mm jack)PowerCon, three pins Plywood,column loudspeaker1× Wooden handlesCabinet coated by Polyurethane paint; grille is powder coatedFrequency Response 2nd Distortion 3rd Distortion7400mm (15.75in)586m m (23.07i n )250mm (9.84in)1726m m (67.95i n )86.5mm (3.41in)108.6mm (4.28in)570m m (22.44i n )S2-IIITop viewFront viewSide viewBack viewBottom view2D DimensionTECHNICAL SPECIFICATIONFront view Side view Back viewMeline S2-II EXT:Notes:。

6B Product and Service PortfolioT h e P r ov en A l t erna tiveAnsaldo Energia GroupTogether, PSM and Ansaldo Thomassen, as part of the Ansaldo Energia Group, now offer complete solutions for the Frame 6B, providing our customers with innovative products and services to lower emissions, extend life, and much more.PSM’s Complete 6B Service OfferingPSM’s complete single source solution brings together engineering capabilities from our OEM background with the innovative solutions of the independent service providers of PSM and Ansaldo Thomassen. With an extensive portfolio of field service, repair capabilities, spare parts supply, innovative upgrades, training and long-term service agreements, our goal is to serve the energy industry with a broad range of power generation equipment worldwide.Optimizing Maintenance & Operations for Your 6B UnitOur mission is to lead the way in developing technology solutions, delivered with a wide range of services to help GT owners and operators decrease life cycle costs and improve the overall performance of their turbines and plants. As your partner, our Service teams bring you a wealth of expertise and years of experience. We’re constantly searching for better ways to help you meet your goals, with an agile entrepreneurial spirit combined with a multifaceted engineering team. This combination has created unique equipment solutions, upgrade options and patented inventions that have improved the reliability and performance of power plants worldwide.02PSM and Ansaldo Thomassen under the Ansaldo Energia umbrella provide Frame 6B hot gas path buckets, nozzles, shrouds and compressor hardware. mproved durability and lower life cycle cost is achieved using our component and system product modeling and data evaluation tools, to identify the issues and failure modes in current OEM designs.We manufacture all buckets, nozzles and shroud blocks to be compatible with the latest 1140C (2084F) firing temperature machines and are also backwards compatible. In normal operation the entire hot gas path has a minimum service interval of 24,000 FFH, which can be increased to 32,000 FFH on a unit by unit basis, with consultation from our experts.I nstallation hardware and optional alternative coatings are available based on specific operating conditions such as a heavy corrosion environment.NEW HOT GAS PATH PARTS SOLUTIONSBuckets1st Stage: • I nterchangeable with GE P/N 314B7162G015• B ase Alloy-111-DS• M CrAlY airfoil coating plus internal aluminide coating• 16-cooling hole design to allow for increased inlet temperatures.2nd Stage: • I nterchangeable with GE P/N 314B7163G021• B ase Alloy-738-LC•6 turbulated cooling hole design with cobalt base hardface material on the z-notches.3rd Stage: • A dvanced aero design interchangeable with GE P/N 314B7164G019 or standard configuration 314B7164G014• B ase Alloy-738-LCNozzles1st Stage:• I nterchangeable with GE P/N 112E6044G001• B ase Alloy-414• C hordal hinge design to minimize cooling airleakage with optional TBC/MCrAlY coating depending on operating conditions2nd Stage: •I nterchangeable with GE P/N 119E2434G044 or 119E2434G036 (brush seal)• O ption available for brush seal design • N ozzle - Base Alloy-939-mod • D iaphragm – AISI 410• B rush seal configuration will generate an increased power output and improved heat rate. Standard configuration nozzles are coated with Al-Si diffusion coating to enhance oxidation resistance 3rd Stage: • A dvanced aero design interchangeable with GE P/N 201E1231G002 or standard configuration 112E6642G003• B ase Alloy-738-LCBefore delivery a harmonic analysis is conducted on all nozzles to verify the assembly sequence. Nozzles are fully interchangeable with other GEgroup numbers without any modification to the gas turbine.Ansaldo Energia Group03Rotor Lifetime Extension Rotor Management ProgramCustomer Rotor Inspec6onsEvalua6ons and Reworks Rotor Life6me Assessment• P E R F O R M A N C E • R E L I A B I L I T YC O M B U S T I O N T U N I N G•F U E L F L E X I B I L I T Y 04Ansaldo Energia GroupThree key design features in the LEC III™ combustion system enable thisimproved process and fundamentally differentiate the LEC III™ from theOEM design: the forward flowing venturi, effusion cooling technology, and mixture via the premixer dilution holes, resultingNOx formation.in better mixing and a leaner combustionmixture which reduces NOx generation.066B CONTROL SOLUTIONSfety-related turbine functions. This control system also offers the rdware and software flexibility your power plant needs to remain relevant, iable – and, above all – profitable.e TC-7 can be easily exchanged with a Mark I , Mark I , Mark I V or ark V and no mechanical support change is needed. Electrical and strumentation changes are minimized. The cable entrance is at the ttom so no additional marshalling boxes are needed for cable extension. strumentation can be adapted to fulfill SIL requirements. Approved flame tectors and the gas nozzle start pressure switch are common instruments be adapted.+ A ddition of AutoTune provides fuel flexibility, extended turndown, elimination of annual or seasonal tuning, fast transfer and start-up optimization to respond to fluctuating market demandsAnsaldo Energia Group •R E L I A B I L I T Y•P E R F O R M A N C E08Customized Tooling Emergency Response Team Control/Combustion Tuning Instrumentation Support Valve CalibrationCustomized Work Instructions & Quality Plan Foreign Material Exclusion Procedures Field Inspection & AssessmentsDetailed Lessons Learned & Improvement Plans+ F ull Metallurgical Laboratory with Engineering Services + Brazing + FIC Cleaning+ Qualified fixture check for all components +R obotically controlled coating+ F low testing, gas and liquid, including F-class and DLN + H eat treat+ 24 hour engineering and shop support + L atest Qualified Procedures/Process + S tate-of-the-Art Equipment+ W arehouse for Spare & Emergency Parts + L ifetime assessment of components and rotorsAnsaldo Energia Group09Monitoring & Diagnostics CenterPSM provides engineering and operational support in troubleshooting issues outside of the normal inspection periods. The support includes staff located in Florida, USA and Genoa, Italy supporting the monitoring function on a 24-hours-a-day, seven-days-per-week basis. The monitoring center personnel have the capability to perform an analysis of the cause of issues and recommendations on how to solve the issues in the short term and, if applicable, a recommendation for a longer term improvement. The data collected from the Monitoring & Diagnostics Center is essential in tracking the history of parts and providing the essential functions required for Long-Term Planning. The Monitoring Center function includes data analysis and trending for the following Gas Turbine Points:+ C ombustor Dynamics + B lade Path Spread+ E xhaust Gas Temperature Spreads + F uel Gas/Oil Temperature + B earing Temperature & Vibration+ C ompressor Discharge Temperature & Pressure + I nlet Guide Vane Position + T urbine Speed+ C ompressor Inlet Temperature + A larm Displays in the DCS + R -0 Vibration MonitoringCustomer TrainingOur courses combine theoretical knowledge with practical training toensure maximum value and relevance. The GE-type heavy-duty gas turbine program trains operators and maintenance personnel on this type of gas turbine and its associated systems. The Speedtronic™ Mark V & Mark VI control program familiarizes electrical and instrumental staff with the hardware and software of the control system and enhances their ability to find viable solutions.These programs include:– gas turbine basics – major components – auxiliary systems – turbine maintenance – turbine operations – a n introduction to turbine controls – a n introduction to Speedtronic™ controls – panel hardware– operating instructions – i ntroduction to software configurations – u ser manuals, maintenance and application manuals – control systemsWhen we conduct training at a client’s location, we combine classroom sessions and visual presentations with practical instruction close to the machinery. This gives trainees the opportunity to apply theoreticalknowledge to their own machines.10Long Term Agreements and Structured Maintenance ContractsPSM can bring in all of our services and product lines specifically engineered for the 6B, to structure specific maintenance programs to provide our customers with significant life cycle cost reduction in order to maximize ROI. In summary, the various agreement offerings are structured to optimize your maintenance budget by offering competitive parts life guarantees, minimal parts fallout, coverage during unscheduled inspections, control of inventory, and proactive contract management to ensure total coverage.Scope of Supply — based on the customer requirementsThe customer determines the level of scope for the Long Term Agreements, ranging from full service offerings to a pricing agreement. Service offered by PSM within a Long Term Agreement include, but are not limited to, the following:+ P arts Supply + R econditioning+ F ield Services — including craft labor+ M onitoring & Diagnostics (e.g. Remote Monitoring)+ C ontract Management + I nventory Management + P arts Tracking+ E ngineering Assessments + System Technical SupportAnsaldo Energia Group11Plant Assessment for Combined Cycle Power PlantsThe competitive power generation market drives power plant operators to increase output, improve heat rate and lower operational costs. Enhancements and upgrades of the original design equipment are typically implemented to accomplish these goals. Consideration of the power plant as a system is critical when making decisions to invest in performance upgrades.BenefitsA PSM Plant Assessment provides the knowledge to:+E nsure equipment and systems are compatible with proposed upgrades +M aximize asset potential+A ssess real-time condition & performance +I ncrease operational flexibility +F orecast life expectancy +M anage emissions profileComponent EvaluationGas Turbine+ P SM upgrade applications + O utput and efficiency gains + E xhaust flow and temperature Heat Recovery Steam Generator + P ressure part design limits + F low accelerated corrosion areas + C apacity of attemperators Steam Turbine + S team path analysis+ T hermal and mechanical stress limits + O utput and efficiency gainsGenerator+ O peration during maximum output + C apability curves and cooling limitations + M agnetic saturation limits Balance of Plant+ P erformance of environmental controls+C apacity of control valves, pumps, heat exchangers & safety valvesModeling & AnalysisPSM can perform a detailed analysis of the power plant for multiple operational and ambient conditions. The following considerations are taken into account:+ O riginal design and upgraded heat balances + M odel calibration to as-is equipment condition+ O EM and model-based upgrade potential formajor equipment+ B alance of plant systems and components capabilityPlant Assessment ReportThe plant assessment report provides thefollowing evaluations:+ C urrent vs. upgraded plant thermal performance+ E missions summary and environmental impact+ E quipment and operational limitations/recommendations+ Business case development supportAnsaldo Energia GroupRevision 9/2019Contact your PSM Sales Representative for more information.Call: 561.354.1100 or email: ************************.com© 2019 Power Systems Mfg., LLC (PSM). PSM is not an authorized distributor or representative of GE, Siemens, Mitsubishi, or Westinghouse. The data contained herein is provided for information purposes only. PSM makes no representation, warranty or guarantee (whether expressed or implied) as to the accuracy or completeness of such data or any projected performance criteria.Ansaldo Energia GroupLEC III ™ and T-DLN offerings are available and can be specifically tailored to customers’ needs by incorporating our FlexSuite products, whether there are ultra low emissions, single or dual fuel needs.Hot Gas Path1st, 2nd, 3rd stage buckets, nozzles, and shrouds with the latest design improvementsRotorRotor components from bolting to new compressor and turbine discsCombustion System Engine Tuning including Monitoring & DiagnosticsSupport for all rotating equipment (e.g. remote monitoring) of gas turbines worldwide.Rotor Lifetime Extension (LTE)PSM’s Rotor LTE program can extend the useful lifetime of your rotor. With the advancements in computing power, material properties, fracture mechanic methodologies, and inspection techniques, it is now possible to assess the potential to run rotors beyond their original published limits.Field Services and Outage ManagementDeveloped globally and executed regionally, PSM offers complete field service solutions including on-staff bladers and supply of labor for gas turbines, steam turbines and generators worldwidePSM’s robust repair facility located in Florida, USA has partnered with Ansaldo Thomassen and their network of facilities in The Netherlands and Abu Dhabi, UAE in order to provide a true global network of component repair facilities.Conversions, Modifications and UpgradesAs needs change, PSM brings the ability to upgrade aging equipment back to life to compete against a changing power grid allowing customers to reduce emissions, extend life, and much moreFlexible Long-Term Parts and Service AgreementsCombining all of our services into one robust package tailored to fit the needs of your 6B units from full LTAs to rotor or component management programs.Company Headquarters and Sales for Gas Turbines 1440 West Indiantown Road Jupiter, Florida 33458 USA Phone: +1 561 354 1100Sales for Gas Turbines Phone : +41 585 058 593Sales for Gas Turbines Phone : +31 26 497 5941+ Americas+ Europe/Africa+ Middle East。

HP ELITEBOOK 845 G9WORK WHERE YOU’RE NEEDEDHP Wolf Security for Businesscreates a hardware-enforced,always-on, resilient defenseto protect your PC frommodern threats. 2Take some friction out of working remotely with the HP EliteBook 845. Built to seamlessly fit into enterprise IT, it also comes with features that delight its users.RECOMMENDED ACCESSORIES COLLABORATION FOR HYBRID WORKA good collaboration experience is imperative in our new hybrid working world.The HP EliteBook 845, powered by HP Presence5, with its optional auto-tracking5MP camera6, Audio by Bang & Olufsen, and optional 4G LTE8 connectivity, letsusers connect from almost any location with a more personal experience.PRODUCTIVITY WHEREVER YOU AREPerformance continues to improve with new technology that powers the HPEliteBook 845. The new 16:10 ratio screen reduces the need to scroll by showingmore vertical content than a 16:9 display. DDR5 memory and PCI Gen4 SSDsprovide fast access to your work.A PERSONALIZED EXPERIENCEOptimize audio and video to your surroundings, powered by HP Presence5, withsettings in the myHP application.9HELP PROTECT OUR SHARED FUTUREThis PC contains at least 30% post-consumer recycled plastic in the bezel, atleast 50% post-consumer recycled plastic in the keycaps,41 and the outer boxpackaging is 100% sustainably sourced.40Be on the cutting edge ofcomputing with the latestAMD Ryzen® multi-coreProcessors1HP USB-C EssentialPower BankHP 635 Multi-DeviceWireless MouseE34m Conferencing MonitorHP Renew BusinessHP USB-C Dock G5FOOTNOTES1. Multi-core is designed to improve performance of certain software products. Not all customers or software applications will necessarily benefit from use of this technology. Performance and clock frequency will vary dependingon application workload and your hardware and software configurations. AMD’s numbering is not a measurement of clock speed.2. HP Wolf Security for Business requires Windows 10 and higher, includes various HP security features and is available on HP Pro, Elite, Workstation, and RPOS products. See product details for included security features and OSrequirements.3. For full Intel® vPro® functionality, Windows 10 Pro or higher 64 bit, a vPro supported processor, vPro enabled chipset, vPro enabled wired LAN and/or WLAN card and TPM 2.0 are required. Some functionality requiresadditional 3rd party software in order to run. See /vpro4. Sold separately or as an optional feature.5. Requires the myHP application and Windows OS.6. Optional feature that must be configured at the time of purchase.7. N/A8. 4G LTE module is optional and must be configured at the factory. Module requires activation and separately purchased service contract. Backwards compatible to HSPA 3G technologies. Check with service provider for coverageand availability in your area. Connection, upload, and download speeds will vary due to network, location, environment, network conditions, and other factors. 4G LTE not available on all products, in all regions.9. Available on select HP PCs with Windows 10 and higher, and with Intel processors.10. A vailable on select HP PCs with Windows 10 and higher and Intel processors.11. H P Sure View Reflect integrated privacy screen is an optional feature that must be configured at purchase and is designed to function in landscape orientation.12. S ure View privacy panel and touchscreen will lower actual brightness.13. L ow blue light panel is only available on non-touch models.14. D ue to the non-industry standard nature of some third-party memory modules, we recommend HP branded memory to ensure compatibility. If you mix memory speeds, the system will perform at the lower memory speed.15. R echarges your battery up to 90% within 90 minutes when the system is off or in standby mode. Power adapter with a minimum capacity of 65 watts is required. After charging has reached 50% capacity, charging will return tonormal. Charging time may vary +/-10% due to System tolerance.16. A ctual battery Watt-hours (Wh) will vary from design capacity. Battery capacity will naturally decrease with shelf life, time, usage, environment, temperature, system configuration, loaded apps, features, power managementsettings and other factors.17. H P TamperLock must be enabled by the customer or your administrator.18. W i-Fi 6E requires a Wi-Fi 6E router, sold separately, to function in the 6GHz band. Availability of public wireless access points limited. Wi-Fi 6E is backwards compatible with prior 802.11 specs. And available in countries whereWi-Fi 6E is supported.19. N/A20. H P Sound Calibration is delivered automatically through Windows update or can be downloaded from https:///us-en/drivers when available. Requires Windows 10 or 11, analog headset, and setup.21. W WAN is an optional feature, requires factory configuration and separately purchased service contract. Check with service provider for coverage and availability in your area. 4G LTE not available on all products, in all regions.22. H P Touch Fingerprint sensor is an optional feature that must be configured at purchase.23. H P Privacy Camera only available PCs equipped with HD or IR camera and must be installed at the factory.24. H P Sure Start Gen7 is available on select HP PCs and requires Windows 10 or 11.25. H P Sure Run Gen5 is available on select HP PCs and requires Windows 10 or higher.26. H P Sure Recover Gen5 with Embedded Reimaging is an optional feature which requires Windows 10 and higher must be configured at purchase. You must back up important files, data, photos, videos, etc. before use to avoidloss of data. Network based recovery using Wi-Fi is only available on PCs with Intel Wi-Fi Module.27. H P Sure Admin requires Windows 10, HP BIOS, HP Manageability Integration Kit from /go/clientmanagement and HP Sure Admin Local Access Authenticator smartphone app from the Android or Apple store.28. H P Sure Click requires Windows 10 and higher. See https://bit.ly/2PrLT6A_SureClick for complete details.29. H P Sure Sense is available on select HP PCs and is not available with Windows10 Home.30. H P Manageability Integration Kit can be downloaded from /go/clientmanagement and requires Microsoft Endpoint Manager.31. H P Connect for Microsoft Endpoint Manager is available at for HP Pro, Elite, Z and Point-of-Sale PCs managed with Microsoft Endpoint Manager. Subscription to Microsoft Endpoint Manager required and soldseparately. Network connection required.32. H P Easy Clean requires Windows 10 RS3 and higher and will disable the keyboard, touchscreen, and clickpad only. Ports are not disabled. See user guide for cleaning instructions.33. H P Support Assistant requires Windows and Internet Access.34. R equires Internet access and Windows 10 and higher PC preinstalled with HP QuickDrop app and either an Android device (phone or tablet) running Android 7 or higher with the Android HP QuickDrop app, and /or an iOS device(phone or tablet) running iOS 12 or higher with the iOS HP QuickDrop app.35. M IL STD 810 testing is not intended to demonstrate fitness for U.S. Department of Defense contract requirements or for military use. Test results are not a guarantee of future performance under these test conditions.Accidental damage requires an optional HP Accidental Damage Protection Care Pack.36. H P Total Test Process testing is not a guarantee of future performance under these test conditions. Any accidental damage requires an optional HP Accidental Damage Protection Care Pack.37. S elect household wipes can be safely used to clean HP Elite and Workstation, and HP ProBook 635 Aero PCs up to 1,000 wipes: See wipe manufacturer’s instructions for disinfecting and the HP cleaning guide for HP tested wipesolutions at How to Sanitize Your HP Device Whitepaper (/v2/GetDocument.aspx?docname=4AA7-7610ENW) not applicable to HP Elite c1030 Chromebook.38. B ased on US EPEAT® registration according to IEEE 1680.1-2018 EPEAT®. EPEAT® status varies by country. Visit for more information.39. L aptop speaker enclosure contains 5% ocean bound plastic by weight.40. 100% outer box packaging made from sustainably sourced certified and recycled fibers. Fiber cushions made from 100% recycled wood fiber and organic material. Any plastic cushions are made from >90% recycled plastic.41. R ecycled plastic content percentage is based on the definition set in the IEEE 1680.1-2018 standard.© Copyright 2022 HP Development Company, L.P. The information contained herein is subject to change without notice. The only warranties for HP products and services are setforth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not beliable for technical or editorial errors or omissions contained herein.AMD and Ryzen are trademarks of Advanced Micro Devices, Inc. Bluetooth is a trademark owned by its proprietor and used by HP Inc. under license. USB Type-C® and USB-C®areregistered trademarks of USB Implementers Forum. DisplayPort™ and the DisplayPort™ logo are trademarks owned by the Video Electronics Standards Association (VESA®) in the United States and other countries. Members of Wi-Fi Alliance® are bound to follow the requirements of the Brand Styleguide pursuant to the Certification Mark License Agreement.*********************************************************************************.requirements.AMDandRadeonaretrademarksofAdvancedMicroDevices,Inc.January 2022。

Levante Sistemas deAutomatización y Control S.L.CatálogosLSA Control S.L. - Bosch Rexroth Sales PartnerRonda Narciso Monturiol y Estarriol, 7-9Edificio TecnoParQ Planta 1ª Derecha, Oficina 14(Parque Tecnológico de Paterna)46980 Paterna (Valencia)Telf. (+34) 960 62 43 01*************************VisualMotion GPS 6.0DOK-VISMOT-VM*-06VRS**-FKB1-AE-P • 07/98Reference Manual 280585VisualMotion GPS 6.0Reference Manual DOK-VISMOT-VM*-06VRS**-FKB1-AE-P • 07/98IAE 74792, Rev. G This document is intended to be a reference manual for the CLC Multi-AxesCoordinated Motion Control Card. This manual contains the informationneeded to program the card using VisualMotion32 and covers the followingitems.• I/O Systems• Parameters• Icon/Text Programming• Direct ASCII Communication• DDE Client Interfaces RevisionDate Remarks IAE 74792, Rev A10/91Initial Release IAE 74792, Rev B06/94Updates IAE 74792, Rev C10/94Updates - Not released IAE 74792, Rev D12/94GPS 1.2IAE 74792, Rev E9/95GPS 02IAE 74792, Rev F10/96GPS 05IAE 74792, Rev G 07/98VisualMotion32 - GPS 06© INDRAMAT, 1998Copying this document, and giving it to others and the use or communicationof the contents thereof without express authority, are forbidden. Offenders areliable for the payment of damages. All rights are reserved in the event of thegrant of a patent or the registration of a utility model or design (DIN 34-1).All rights are reserved with respect to the content of this documentation andthe availability of the product.INDRAMAT • 5150 Prairie Stone Parkway • Hoffman Estates, IL 60616Telephone 847-645-3600 • Fax 847-645-6201TechDoc Dept. (LS/HK)TitleKind of documentationDocu-typeInternal file referencePurpose of this document Revision history Copyright Validity Published byVisualMotion GPS 6.0DOK-VISMOT-VM*-06VRS**-FKB1-AE-P Contents IContents1Introduction 1-11.1Purpose of Manual...........................................................................................................................1-11.2Manual Overview..............................................................................................................................1-61.3Overview of CLC..............................................................................................................................1-7CLC System Architecture.................................................................................................................1-7Indramat’s VisualMotion ® Programming Interface..........................................................................1-8CLC BTC06......................................................................................................................................1-8CLC Operating System ....................................................................................................................1-91.4CLC Motion Capabilities.................................................................................................................1-10Non-Coordinated Motion................................................................................................................1-10Coordinated Motion........................................................................................................................1-10Electronic Line Shaft (ELS)............................................................................................................1-112CLC Input/Output Systems 2-12.1I/O Overview.....................................................................................................................................2-12.2Remote I/O Systems........................................................................................................................2-22.3I/O Mapper .......................................................................................................................................2-3I/O Mapper Ladder Logic Format.....................................................................................................2-4I/O Mapper Boolean Format.............................................................................................................2-4I/O Mapper Operators ......................................................................................................................2-5I/O Mapper Considerations ..............................................................................................................2-52.4I/O Bit Forcing ..................................................................................................................................2-62.5Reading and Writing Physical I/O.....................................................................................................2-62.6CLC Registers..................................................................................................................................2-7Register 1: System Control ..............................................................................................................2-8Registers 2-5: Task Control ...........................................................................................................2-10CLC Cycle Control Considerations.................................................................................................2-13Register 6: System Diagnostic Code..............................................................................................2-14Registers 7-10: Task Jog Control...................................................................................................2-14Registers 11-18, 209-240: Axis Control.........................................................................................2-17Register 21: System Status............................................................................................................2-18Registers 22-25: Task Status.........................................................................................................2-19Registers 27 and 28: Eagle Module Inputs/Outputs (CLC-V Only)................................................2-20Register 29: ELS Master Control Register.....................................................................................2-21Register 30: ELS Master Status Register.......................................................................................2-22Registers 31-38, 309-340: Axis Status...........................................................................................2-23VisualMotion GPS 6.0Registers 40-87: DEA (4/5/6) I/O...................................................................................................2-26Registers 88,89: Task A Extend Event Control..............................................................................2-26Registers 90 and 91: Latch and Unlatch........................................................................................2-27Registers 92-94: Mask Pendant Key Functionality.........................................................................2-27Registers 95-97: BTC06 Teach Pendant Status Registers............................................................2-28Registers 98, 99: Teach Pendant Control - Task A-B, C-D............................................................2-29Register 400-405, 410-415: DEA (28/29/30) I/O Registers............................................................2-30CLC Reserved Register Tables......................................................................................................2-313Parameters3-13.1Overview...........................................................................................................................................3-13.2Parameter Transfer Commands......................................................................................................3-23.3List of Parameters............................................................................................................................3-33.4System Parameters........................................................................................................................3-14System Setup (0001-0031)............................................................................................................3-14Jogging and Display (0042-0056)...................................................................................................3-24Program Management (0090-0099)...............................................................................................3-26System Status (0100-0126)............................................................................................................3-29Electronic Line Shaft Parameters 1 of 2 (0150-0170)....................................................................3-33VME Bus (0200-0287)....................................................................................................................3-37BTC06 Teach Pendant (0801-0991)..............................................................................................3-44Electronic Line Shaft Parameters 2 of 2 (1000-1568)....................................................................3-53System Parameter Lists (2000-3108).............................................................................................3-593.5Task Parameters............................................................................................................................3-74Task Setup (0001-0002).................................................................................................................3-74Coordinated Motion (0005-0026)...................................................................................................3-76Robotics (0035-0059).....................................................................................................................3-80Coordinated Motion Status (0100-0113)........................................................................................3-81Task Status (0120-0200)................................................................................................................3-83Task Parameter Lists (2000-2001).................................................................................................3-873.6Axis Parameters.............................................................................................................................3-88Axis Setup (0001-0038)..................................................................................................................3-88Axis Status (0100-0145)...............................................................................................................3-103Electronic Line Shaft (0150-0164)................................................................................................3-106Axis Feedback Capture (Registration 0170-0174).......................................................................3-110Optional SERCOS Data (0180-0196)...........................................................................................3-111Axis Parameter Lists (2000-2001)................................................................................................3-1133.7Drive Parameters.........................................................................................................................3-113Drive Status..................................................................................................................................3-115Required DDS Setup....................................................................................................................3-115 II Contents DOK-VISMOT-VM*-06VRS**-FKB1-AE-PVisualMotion GPS 6.0DOK-VISMOT-VM*-06VRS**-FKB1-AE-P Contents III4VisualMotion Menu Commands 4-14.1Introduction.......................................................................................................................................4-14.2The File Menu ..................................................................................................................................4-2Program Management......................................................................................................................4-2Archive..............................................................................................................................................4-4Transfer Cams .................................................................................................................................4-5Transfer Events................................................................................................................................4-6Transfer I/O Mapper.........................................................................................................................4-6Transfer Parameters........................................................................................................................4-6Transfer Points.................................................................................................................................4-7Transfer Variables............................................................................................................................4-8Transfer Zones.................................................................................................................................4-8Print..................................................................................................................................................4-84.3The Edit Menu................................................................................................................................4-10Clear Current Task.........................................................................................................................4-10Find, Find Next...............................................................................................................................4-10Add Subroutine...............................................................................................................................4-11Add Event Function........................................................................................................................4-11Labels - User Labels ......................................................................................................................4-11Labels - Register Labels.................................................................................................................4-13Labels - Bit Labels..........................................................................................................................4-13Import User Label File....................................................................................................................4-14Export User Label File....................................................................................................................4-144.4The View Menu...............................................................................................................................4-15Subroutines....................................................................................................................................4-15Event Functions..............................................................................................................................4-15Zoom Out .......................................................................................................................................4-154.5The Setup Menu.............................................................................................................................4-16Card Selection................................................................................................................................4-16Configuration..................................................................................................................................4-16Drives.............................................................................................................................................4-17Drives Help Directories...................................................................................................................4-17Coordinated Motion........................................................................................................................4-18I/O Setup........................................................................................................................................4-19Overview.........................................................................................................................................4-21Pendant Security............................................................................................................................4-22CLC Serial Ports.............................................................................................................................4-23VME Configure...............................................................................................................................4-234.6The Tools Menu.............................................................................................................................4-25Breakpoint Control..........................................................................................................................4-25CAM Builder...................................................................................................................................4-25Jogging...........................................................................................................................................4-30VisualMotion GPS 6.0Oscilloscope...................................................................................................................................4-33VisualMotion32, CLC_DDE Release6............................................................................................4-33Show Program Flow.......................................................................................................................4-334.7The Data Menu...............................................................................................................................4-35CAM Indexer..................................................................................................................................4-35Events.............................................................................................................................................4-35Field Bus Mapper (CLC-D Only).....................................................................................................4-37I/O Mapper.....................................................................................................................................4-40PID Control Loops..........................................................................................................................4-44PLS.................................................................................................................................................4-49Points..............................................................................................................................................4-57Registers........................................................................................................................................4-59Registration (Not Functional for GPS 6.0)......................................................................................4-62Sequencer......................................................................................................................................4-63Variables.........................................................................................................................................4-66Zones.............................................................................................................................................4-674.8The Status Menu............................................................................................................................4-68Diagnostic Log................................................................................................................................4-68Drives.............................................................................................................................................4-68Drives on Ring................................................................................................................................4-68System............................................................................................................................................4-69Tasks..............................................................................................................................................4-694.9The Options Menu..........................................................................................................................4-714.10Help................................................................................................................................................4-725Programming Concepts5-15.1Overview...........................................................................................................................................5-15.2Program Tasks.................................................................................................................................5-1Command Execution........................................................................................................................5-15.3Events...............................................................................................................................................5-2Time-based Events..........................................................................................................................5-2Distance-based Events....................................................................................................................5-3Repeating Axis Position (Rotary) Events..........................................................................................5-5Interrupt Input Events.......................................................................................................................5-6Extended External I/O Events..........................................................................................................5-7VME Events......................................................................................................................................5-7Feedback Capture (Probe)...............................................................................................................5-9Event Tables..................................................................................................................................5-105.4Subroutines....................................................................................................................................5-10Function Arguments and Local Variables.......................................................................................5-105.5Sequencer......................................................................................................................................5-11Single Stepping a Sequencer Step.................................................................................................5-12 IV Contents DOK-VISMOT-VM*-06VRS**-FKB1-AE-PVisualMotion GPS 6.0DOK-VISMOT-VM*-06VRS**-FKB1-AE-P Contents VSingle Stepping a Step Function....................................................................................................5-125.6Data and Expressions....................................................................................................................5-13Integers and Floats.........................................................................................................................5-13Constants and Variables................................................................................................................5-13Expressions....................................................................................................................................5-15Mathematical and Logical Operators..............................................................................................5-165.7Tables.............................................................................................................................................5-17Event Table....................................................................................................................................5-19CLC Path Planner...........................................................................................................................5-20Absolute Point Table......................................................................................................................5-22Relative Point Table.......................................................................................................................5-23Zone Protection Table....................................................................................................................5-246Icon Programming 6-16.1Introduction.......................................................................................................................................6-1Working with VisualMotion’s Icon Palettes and Buttons ..................................................................6-1Connecting Icons..............................................................................................................................6-3Icon Labels and Comments .............................................................................................................6-5User Defined Labels.........................................................................................................................6-56.2CLC Icons.........................................................................................................................................6-6Single Axis Icon Palette....................................................................................................................6-6Coordinated Motion Icon Palette......................................................................................................6-7ELS Icon Palette...............................................................................................................................6-8Utility Icon Palette.............................................................................................................................6-9Accel...............................................................................................................................................6-10Axis.................................................................................................................................................6-11AxisEvt............................................................................................................................................6-16Branch............................................................................................................................................6-17Calc................................................................................................................................................6-19Cam................................................................................................................................................6-22CamAdj...........................................................................................................................................6-23CamBuild........................................................................................................................................6-24Cam Indexer...................................................................................................................................6-26Circle..............................................................................................................................................6-30Decel..............................................................................................................................................6-32ELS.................................................................................................................................................6-33ELSAdj............................................................................................................................................6-36ELSMode........................................................................................................................................6-37Event..............................................................................................................................................6-38Finish..............................................................................................................................................6-39Go...................................................................................................................................................6-40Home..............................................................................................................................................6-41I/O...................................................................................................................................................6-42。