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2000门课程名称翻译大全(十五)

2000门课程名称翻译大全(十五)

2000门课程名称翻译大全(十五)色彩 Color色谱 Color Spectrum摄影技巧 Techniques for Photography涉外企业管理 Enterprise Administration Concerning Foreign Natio社会调查的理论与方法 Theories & Methods for Social Investigation社会调查方法 Methods for Social Investigation社会工作 Social Work社会统计分析与SYSTAT应用 Social Statistics Analysis & SYSTAT Application社会统计学 Social Statistics社会问题研究 Research on Social Problems社会心理学 Social Psychology社会学概论 Introduction to Sociololgy社会学简论 Brief Introduction to Sociology社会学理论专题 Current Issues in Theories of Socilolgy 社会学问题研究 Research on Problems of Sociology社会学研究方法 Research Methods of Sociology社会主义财政学 Finance of Socialism社会主义各国政，经体制讨论 Discussion on Political & Economic Systems in Socialism审计学 Science of Auditing生产管理 Administration of Manufacturing生产过程计算机控制 Computer Control in Manufacturing Process生产过程自动化 Water-Turbine Engine生理学 Physiology生命科学与无机化学 Life Science and Inorganic Chemistry 生物工程产品 Bio-engineering Products生物工程导论 Introduction to Bio-engineering生物化学 Biochemistry生物化学工程 Biochemical Engineering生物化学及实验 Biochemistry Experiment生物检测技术 Measurement for Biotechnique生物控制论 Biocybernetics生物流变学 Biorheology生物物理 Biophysics生物学专题 Currents Issues in Biology生物医学超声学 Biomedical Supersonics失效分析 Invalidation Analysis诗歌美学 Aesthetics of Poetry时间序列 Time Sequence实变函数 Functions of Real Variable实验分析 Experimental Analysis实验力学 Experimental Mechanics实验力学基础 Basis of Experimental Mechanics实验流体 Experimental Flowing Object实验应力分析 Analysis of Experimental Stress世界近现代经济史 Modern History of World Economy世界近现代史 Modern History of the World世界文化史 History of World Culture世界政治经济与国际关系 World Politic Ecomony&International Relationship适应控制系统 Adaption Control System市场学 Science of Market市场研究 Research on Market市场预测 Market Predicting输入输出设计原理 Principle of Input and Output Designing 书法 Handwriting数据结构 Data Structure数据库概论 Introduction to Database数据库基础 Basis of Database数据库技术 Technique of Database数据库设计与分析 Design & Analysis of Database数据库系统原理 Principles of Database System数据库应用 Application of Database数据库原理及应用 Principle & Application of Database数控机床 Digit Control Machine Tool数控技术 Digit Control Technique数理方程 Mathematical Equations数理方程积分变换 Integral Transmission of Mathematical Equation数理方程与特殊函数 Equations of Mathmatical Physics & Special Functions数理逻辑 Mathematical Logic数理统计 Mathematical statistics数量经济 Quantity Economics数学分析 Mathematical Analysis数学规划 Mathematical Planning数学模型 Mathematical Modening数学物理方法 Method of Mathematical Physics数值电路 Digital Circuit数值分析 Numerical Analysis数值计算 Digital Computation数字测量技术 Digital Measuring Technique数字测量实验技术 Experimental Technique of Digital Measuring数字测试实验技术 Experimental Technique of Digital Testing数字电路 Digital Circuit数字电路及微机原理 Digital Circuit & Computer Principles 数字电视 Digital Television数字电子基础 Fundamental Digital Electionics数字电子技术 Digital Electronic Technique数字电子技术基础 Fundamental Digital Electronic Technique数字电子技术设计与实验 Experiment & Design of Digital Electron Technique数字电子线路 Digital Electrical Circuitry数字电子与微机原理 Digital Electronics & Principle of Microcomputer数字仿真 Digital Simulation数字化测量技术 Digital Measuring Technique数字控制及微机控制技术 Digital Control & Microcomputer Control Technique数字逻辑 Digital Logic数字图象处理 Digital Image Processing数字系统逻辑设计 Logical Design of Digital System数字系统设计 Design of Digital System数字信号处理 Digital Signal Processing双曲线方程 Hyperbolic Equation水电能源学 Science of HydrOelectric Enelgy水电站过渡过程的特殊问题 Special Problems in the Transition of a Hydropower Station水电站计算机控制 Computer Control in Hydropower Station 水电站经济运行 Economic Operation in Hydropower Station 水电站控制系统分析 Analysis of Control System in Hydropower Station水电站自动化 Automation of Hydropower Station水动力学 Water Dynamics水机工艺结构分析 Technics Structure Analysis of Hydraulic Machinery水力机械测试技术 Test Technique of Hydraulic Machinery 水力机械的汽蚀 Gas Etching of Hydraulic Machinery水力机械调节 Adjustment of Hydraulic Machinery水力机械强度计算 Intensity Calculation of Hydraulic Machinery水力机械原理 Principles of Hydraulic Machinery水力机械制造工艺及结构分析 Manufacturing Technique &Structure Analysis of Hydraulic Machinery水力机械制造工艺学 Manufacturing Technique for Hydraulic Machinery水力学 Hydraulics水轮机 Water-Turbine Engine水轮机调节 Water-Turbine Engine Adaption水轮机调节系统 Adaptive System of Water-Turbine Engine 水轮机水力设计 Hydraulic Design of Water Engine水轮机原理及水力设计 Principles of Water-Turbine Engine & Design of Water Engine水轮机原理与CAD Principle of Water-Turbine Engine & CAD 水轮水力设计 Hydraulic Design of Water Engine水现代控制理论 Modern Theory of Water Controling水质稳定技术 Stability Technique of Water Quality思想教育 Virtue Education素描 Pencil Sketch速冻技术 Technique of Speed Freezing塑性力学 Plastic Machanics算法语言 Algorithmic Language随机过程 Stochastic Process & Time Series Analysis随机运筹学 Randomized Operational Research锁相技术 Phase Lock Technique---来源网络整理，仅供参考。

锁相技术课件

锁相技术课件

一、概述
§6.3 频率合成
1. 概念
频率合成器是将一个高精确度和高稳定度的标准
参考频率，经过混频、倍频与分频等对它进行加、
减、乘、除的四则运算，最终产生大量的具有同样
精确度和稳定度的频率源。
2. 应用 频率合成器在雷达、通信、遥控遥测、电视广
播和电子测量仪器等方面得到了广泛的应用。
《锁相技术》
第6章 锁相环路的应用
于He (s)具有高通特性，只要在He (s) 的通带之内，
输出信号频偏正比于调制信号的幅度。----调频波
调相波：
2
(s)
He (s)
Ko s
sU F
(s)
对调制信号先 微分再调频
2 (s) He (s)KoUF (s)
输出信号相位正比于调制信号的幅度。----调相波
《锁相技术》
第6章 锁相环路的应用
音频信号调频，则输入瞬时频率为：
载频
i (t) c sin t
Δω为峰 值频偏
当 0 时，i c ，所以 实际是叠加到c 上的。
做出 H ( ji ) i 的关系图，就是环路对输入信号 瞬时频率i 的振幅频率响应：
《锁相技术》
第6章 锁相环路的应用
-3dB点
2c
① 具有带通滤波特性。带宽为 2c 。 ② 由于锁相环的跟踪性能，其中心频率可以跟踪输
fd
fo N V
fo N Vfr
①增加前置分频器，解决了输出频率高于程序分频
器的工作频率的问题，提高了输出频率范围。
《锁相技术》
第6章 锁相环路的应用
②输出频率增量为Vfr ，频率分辨率降低了。
③如果保持原有的频率分辨率 fr ，需要使参考频率

锁相技术学习心得体会doc

锁相技术学习心得体会doc

锁相技术学习心得体会篇一：锁相技术锁相技术论文题目：专业班级：学生姓名：学号：任课老师：陈燕锁相技术的核心 XX级通信工程1班 XX 年 6 月13日摘要本文介绍了锁相技术的核心锁相环路：一个实现相位自动锁定的控制系统。

锁相环路有两个突出的特性：1是窄带滤波特性；2是宽带跟踪特性。

这两个特性使得锁相技术在电子技术领域得到了广泛的应用，特别是随着集成电路技术、数字技术以及通讯和计算机技术的发展，极大地推动了锁相技术的发展和应用。

现在锁相技术已经形成一门比较系统的理论科学，锁相技术的应用主要包含以下几个方面：跟踪滤波、频率合成与频率变换、模拟和数字信号的相干解调、数字通讯、调制与解调、检波、稳频和位频等。

下面来主要介绍一下锁相技术的核心，掌握核心就能运用得当。

关键字：核心，锁相环路，运用锁相环路的工作原理：锁相环路是一种反馈电路，锁相环的英文全称是Phase-Locked Loop,简称PLL。

其作用是使得电路上的时钟和某一外部时钟的相位同步。

因锁相环可以实现输出信号频率对输入信号频率的自动跟踪，所以锁相环通常用于闭环跟踪电路。

锁相环在工作的过程中，当输出信号的频率与输入信号的频率相等时，输出电压与输入电压保持固定的相位差值，即输出电压与输入电压的相位被锁住，这就是锁相环名称的由来。

在数据采集系统中，锁相环是一种非常有用的同步技术，因为通过锁相环，可以使得不同的数据采集板卡共享同一个采样时钟。

因此，所有板卡上各自的本地 80MHz和20MHz 时基的相位都是同步的，从而采样时钟也是同步的。

因为每块板卡的采样时钟都是同步的，所以都能严格地在同一时刻进行数据采集。

锁相环路是一个相位反馈自动控制系统。

它由以下三个基本部件组成：鉴相器（PD）、环路滤波器（LPF）和压控振荡器（VCO）。

锁相环的工作原理：1. 压控振荡器的输出经过采集并分频；2. 和基准信号同时输入鉴相器；3. 鉴相器通过比较上述两个信号的频率差，然后输出一个直流脉冲电压；4. 控制VCO，使它的频率改变；5. 这样经过一个很短的时间，VCO 的输出就会稳定于某一期望值。

锁相技术 第1章

锁相技术 第1章
应用上述描述方法, 矢量图可以画成图1-2(b)所示形式。系 统的瞬时相位差θe(t)=θ1(t)－θ2(t)，瞬时频差
(1-11)
二、捕获过程 从输入信号加到锁相环路的输入端开始, 一直到环路达到
锁定的全过程, 称为捕获过程。一般情况, 输入信号频率wi与被 控振荡器自由振荡频率wo不同, 即两者之差Dwo≠0。若没有相
qe(t)=［wit+qi(t)］－［wot+qo(t)］ =(wi－wo)t+qi(t)－qo(t)
(1-3)
图 1-2 输入信号和输出信号的相位关系 (a) 绝对相位表示；(b) 相对相位表示
前面已经说到, 被控振荡器的自由振荡角频率wo是系统的 一个重要参数, 它的载波相位wot可以作为一个参考相位。这样
(1-15)
第二节 环 路 组 成
锁相环路为什么能够进入相位跟踪, 实现输出与输入信号 的同步呢？因为它是一个相位的负反馈控制系统。这个负反馈 控制系统是由鉴相器(PD)、环路滤波器(LF)和电压控制振荡器 (VCO)三个基本部件组成的, 基本构成如图 1-4所示。
图 1-4 锁相环路的基本构成
一、鉴相器
鉴相器是一个相位比较装置, 用来检测输入信号相位q1(t) 与反馈信号相位q2(t)之间的相位差qe(t)。输出的误差信号ud(t) 是相差qe(t)的函数, 即
ud(t)=f［qe(t)］
图 1-5 正弦鉴相器及其模型 (a) 电压模型；(b) 相位模型
设相乘器的相乘系数为Km［单位为1／V］, 输入信号ui(t) 与反馈信号uo(t)经相乘作用
图 1-1 相位跟踪系统框图 (a) 电压信号图；(b) 相位表示图
若输入信号是未调载波, θi(t)即为常数, 是ui(t)的初始相位； 若输入信号是角调制信号(包括调频调相), θi(t)即为时间的函数。

锁相技术译文翻译

锁相技术译文翻译

锁相技术译文翻译英文原文：An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOI译文：45纳米SOI全数字片上测量电路表征锁相环响应特性年级专业：姓名：学号：2013 年 6 月 2 日英文中文An On-Chip All-Digital Measurement Circuit to Characterize Phase-Locked Loop Response in 45-nm SOIAbstract—An all-digital measurement Circuit , built in 45-nm SOI-CMOS enabl es on-chip characterization of phase-loc ked loop (PLL) response to a self-induce d phase step.This technique allows estimationof PLL closed-loop bandwidth and jitterpeaking. The circuit canbe used to plot step-response vs.time, measure static phase error,and observe phase-lock status. INTRODUCTIONMany applications such as PCI Express ? require a PLL to produce alow-jitter cl ock at a given frequency while meeting stringent bandwidth and jitter peaking r 45纳米SOI全数字片上测量电路表征锁相环响应特性摘要---建立在45纳米的SOI-CMOS上一个全数字测量电路，它能够表征PLL对自诱导相步进的响应这项技术允许对PLL闭环带宽和抖动峰值的估计。

锁相环英文文献翻译

锁相环英文文献翻译

锁相技术译文翻译英文原名：High Speed Digital Hybrid PLL Frequency Synthesizer译文：高速数字混合锁相环频率合成器年纪专业：08级通信工程班姓名：学号：2011年 5月2日To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design.In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequency synthesizer)-driven PLL for the high switching speed [2].However, there is a problem that the speed of the whole system is limited by PLL.Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage converter (FVC) [3].It has a fast switching speed by the PD (phase detector), FVC using output signal of VCO and the proposed coarse tuning controller.However, H/W complexity is increased for the high switching speed.Also, it shows the fast switching characteristic only when the FVC works well.Another method is pre-tuning one which is called DH-PLL in this study [4].It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic ofVCO(voltage controlled oscillator).For this reason, this paper proposes a timing synchronization circuit for the rapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption. Also, the requisite condition is solved in the proposed method. The fast switching operation at every the frequency synthesis process is verified by the computer circuit simulation.II.DH-PLL synthesizerAs shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO 要得到高运行速度,事先做好复杂设计的精确同步是必要的。

锁相技术


设输出信号为：uo (t) Uo cos[ot o (t)]
PLL内部VCO的 自由振荡角频率
是在输入信号控制下，
相对于 ot的瞬时相位，
是时间 t 的函数。
锁相环路中，输入信号 ui (t) 对环路的作用是 在它的瞬时相位 i (t) i (t) 的作用下，改变输出 信号 uo (t) 的瞬时相位 o (t) o (t) ，所以对于锁相 环路来说，更关心的是它的输入和输出信号的相
不为零
数值很小 的量，但
不为零
这一过程所用的时间为捕获时间 TP
《 锁相技术》
第1章 锁相环路的基本工作原理
捕获过程中瞬时相差与瞬时频差的典型时间图分析
．
《 锁相技术》
第1章 锁相环路的基本工作原理
三、锁定状态
环路锁定状态（同步状态）的条件：
e((tt))
(t) 2n e

K0 p
整理得到：pe (t) p1(t) KoUd F ( p)sine(t)
uc (t)
环路的动态方程：
K KoUd
pe (t) p1(t) KF ( p)sine(t)
K K0Ud 为环路增益
《 锁相技术》
第1章 锁相环路的基本工作原理
锁相环路动态方程的物理概念解释：
第1章 锁相环路的基本工作原理
环路的瞬时相位差：（矢量表示方法如图所示）
e (t) 1(t) 2(t)
输入信号的 瞬时角频率
输出信号的 瞬时角频率
环路瞬时频差：
de (t)
dt



1(t)2 (t)
(t)



e (t)

信息科学与电子工程专业英语课程翻译1

Unit 1 电子学：模拟和数字Unit 1-1第一部分：理想运算放大器和实际限制为了讨论运算放大器的理想参数，我们必须首先定义一些指标项，然后对这些指标项讲述我们所认为的理想值。

第一眼看运算放大器的性能指标表，感觉好像列出了大量的数值，有些是陌生的单位，有些是相关的，经常使那些对运放不熟悉的人感到迷惑。

对于这种情况我们的方法是花上必要的时间有系统的按照列出的次序阅读并理解每一个定义。

如果没有对每一项性能指标有一个真正的评价，设计人员必将失败。

目标是能够依据公布的数据设计电路，并确认构建的样机将具有预计的功能。

对于线性电路而言，它们与现在的复杂逻辑电路结构相比看起来较为简单，（因而在设计中）太容易忽视具体的性能参数了，而这些参数可极大地削弱预期性能。

现在让我们来看一个简单但很引人注意的例子。

考虑对于一个在50kHz频率上电压增益为10的放大器驱动10kΩ负载时的要求。

选择一个普通的带有内部频率补偿的低价运放，它在闭环增益为10时具有所要求的带宽，并且看起来满足了价格要求。

器件连接后，发现有正确地增益。

但是它只能产生几伏的电压变化范围，然而数据却清楚地显示输出应该能驱动达到电源电压范围以内2到3伏。

设计人员忽视了最大输出电压变化范围是受频率严格限制的，而且最大低频输出变化范围大约在10 kHz受到限制。

当然，事实上这个信息也在数据表上，但是它的实用性并没有受到重视。

这种问题经常发生在那些缺乏经验的设计人员身上。

所以这个例子的寓意十分明显：在开始设计之前总要花上必要的时间来描写全部的工作要求。

关注性能指标的详情总是有益的。

建议下面列出的具体的性能指标应该考虑：1. 在温度，时间和供给电压下的闭环增益的精确性和稳定性2. 电源要求，电源和负载阻抗，功率消耗3. 输入误差电压和偏置电流，输入输出电阻，随着时间和温度的漂移4. 频率响应，相位偏移，输出变化范围，瞬态响应，电压转换速率，频率稳定性，电容性负载驱动，过载恢复5. 线性，失真和噪声6. 输入，输出或电源保护要求，输入电压范围，共模抑制7. 外部补偿调整要求不是所有的指标项都是有关的，但要记住最初就考虑它们会更好，而不要被迫返工。

锁相技术译文翻译

single-phase signal. The primary signal of the two-phase signalis the injected single-phase signal itself, or a new filtered signalin phase with the fundamental component of the injected singlephase
signal, and the secondary signal is a signal with phase lagofπ/2rad to the fundamental component. The PLL methodsamong them have the potential to correctly estimate the phaseand frequency of frequency-varying single-phase signals.
Index Terms—Frequency estimation, phase estimation, phaselockedloop (PLL), single phase.
I. INTRODUCTION
PHASE, frequency, and amplitude of single-phase voltages
Paper IPCSD-07-073, presented at the 2007 Power Conversion Conference,Nagoya,Japan, April 2–5, and approved for publication in the IEEE TRANSACTIONS ONINDUSTRYAPPLICATIONSby the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review April 27, 2007 and released for publication September 6, 2007.

专业术语翻译

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英文
中文
An On-Chip All-Digital Measurement Circuit to Characterize Phase-LockedLoopResponse in 45-nm SOI
Abstract—An all-digital measurement
Circuit, built in 45-nm SOI-CMOS enables on-chip characterization of phase-locked loop (PLL) responseto a self-induced phase step.This technique allows estimationof PLL closed-loop bandwidth and jitter peaking. The circuit canbeused to plot step-response vs.time, measure static phase error,and observe phase-lock status.
锁相技术译文翻译
英文原文：
An On-Chip All-Digital Measurement Circuit to Characterize
Phase-LockedLoopResponse in 45-nm SOI
译文：45纳米SOI全数字片上测量电路表征锁相环响应特性
年级专业：
姓名： 学号：
2013年6月ቤተ መጻሕፍቲ ባይዱ日
INTRODUCTION
Many applications such as PCI Express™ require a PLL to produce alow-jitter clock at a given frequency while meeting stringent bandwidth and jitter peaking requirements. Process, voltage, and temperature (PVT) variations as well as random device mismatch make it difficult to guarantee a narrow rangefor PLL response. For example,loop parameters such as VCO gaincould vary bymore than 2X overPVT corners. In Fig. 1, we see the closed-loop jitter transfer functions of two PLLs with identical reference clock and output frequencies. One PLL exhibits large peaking and low bandwidth while the other shows little peaking but high bandwidth. Although differences in this example are more extreme than usual, similar but smaller differences often result from PVT variations.
CIRCUIT DESIGN
The PLL under test (Fig. 5) isa standard integer-N charge-pump PLL. The only modification is theaddition of loop measurement circuitry. The feedback divisor (N) isprogrammable from 5 to 63，although N>=8 during loop measurement tests. The charge-pump current, loop-filter resistance, and VCO gain are programmable to allow for bandwidth and peaking adjustments aswell as jitter optimization. The PLL bandwidth may be configured from 3 to 25 MHz while the peaking may be varied from <1 to >4 dB. The VCO operates from 1.6 to 5 GHz. The expected reference clock frequencyrangeis 100 to 200 MHz.
A simple way to induce therequired input phase step is to flip the polarity of the reference clock so its phase is advancedby half a clock cycle. A disadvantage to this approach is thatthe magnitude of the phase step is dependent on the reference clock duty cycle. This is undesirable because overshoot tests requirea large and predictable input phase step. Instead, the circuit implementation presented here manipulates the feedback divisor to induce a known phase step. The circuit then automatically measures theresulting crossover and MaxOvershoot. Fig.6 shows a block diagramof the loop measurement test circuit. It includes three main units: control, crossover detector, and MaxOvershoot detector. The control unitcontains two synchronizers (to VCO clock), three edge detectors (rising and falling), andlogictoenable the induced phase step. The crossover detector includes a bang-bang phase detector, a phase-error change-of-sign detector, and a 10-bit counter. The MaxOvershoot detector contains a feedback count sampler, a comparator, and a maximum overshoot register.
PLL response is often measured on a test bench using signal generators, oscilloscopes, and/or spectrum analyzers. For example, the transfer functions in Fig. 1 were automatically generated by modulating the 100-MHz reference clock with various frequencies while observing the amplitudes of the resulting output spurs. Such methods, which may require many seconds to complete, motivate the need for faster, less expensive, and preferably on-chip techniques to characterize PLL response [1]-[3]. Fig. 2 shows the PLL output phase transient response to an induced phase step. Similar to other second-order feedback systems, the PLL tends to overcorrect (or overshoot) as it works to eliminate the induced phase error. If the PLL is underdamped, as in this example, the PLL may ring several times before settlingto its final lock state. A key metric in the PLL step-response iscrossover, defined here as theelapsed time from input step toonset of phase overshoot. Anotherkey metric is MaxOvershoot. Itmeasures the maximum overcorrectionin the step response.
Transient simulations and closed-form loop equations [4] show that crossover is inversely proportional tothe PLL’s 3dB closed-loop bandwidth; the smaller crossoveris, the higher the bandwidth (Fig. 3). Notice that crossover is largely independentof the size ofthe phase step.Both simulations and loop equations also predict that MaxOvershoot is proportional to the maximum peaking in the closed-loop transfer function; the larger MaxOvershoot is, the greaterthe peaking (Fig. 4). Notice thatthe magnitude of the overshoot isalso proportional to theinput stepsize.These relationships between time- and frequency-domain behaviors allow us to make fast time-domain measurements and then relate the results back to frequency-domain performance specifications.Thecircuitimplementation presented in thispaper shows that the PLL stepresponse may be captured byanall-digital, on-chip finite statemachine, allowing for fast PLL characterization. Silicon results indicate that this circuit could allow for Power-on calibration of the PLL bandwidth and peaking for compensation of process variations.