MDVP definition

mdp文件详解title = BPTI in water, 300K ；名字cpp = /lib/cpp ；预处理程序，gcc的路径define = -DPOSRES_LIPID ；对top文件的控制选项-DFLEXBLE:这个选项告诉grompp水分子是柔性的，非刚体-DPOSRES：限制自由度;constraints = all-bondsintegrator = md ；算法，md这里表示蛙跳算法dt = 0.001 ; ps ! ；时间步长nsteps = 1000 ; total 10 ps. ；步数comm_mode = None ；linear对质心平动，anglar 平动+转动，none对质心无限制nstxout = 0 ；将坐标写入输出轨迹文件的频率nstvout = 0 ；将速度写入输出轨迹文件的频率nstfout = 0 ；将力写入输出轨迹文件的频率nstxtcout = 500 ；将坐标写日xtc坐标文件的频率nstlog = 1000 ；将能量写入log文件的频率nstenergy = 1000 ；将能量写入energy文件的频率nstlist = 10 ；neighbor list 的更新频率ns_type = grid ；neighbor search 的种类，分两种grid：格子和simple coulombtype = PME ；库伦作用种类，cut-off，ewald，PME,PPPM.... rlist = 1.0 ；短程neighbor-list截断半径rcoulomb = 1.0 ；库伦截断半径rvdw = 1.0 ；范德华力截断半径; Berendsen temperature coupling is on in two groupsTcoupl = berendsen ；热浴？berendsen和nose-hoovertc-grps = CNT SOL ；分别进行热浴的类tau_t = 0.1 0.1 ；热浴时间常数（ps）ref_t = 300 300 ；热浴的参考温度（对不同的类分别指定）; Energy monitoringenergygrps = CNT SOL; non-equilibrium MDfreezegrps = CNT ；指出受约束的系统freezedim = Y Y Y ；Y=yes，N=no，三个字母分别代表xyz轴; Isotropic pressure coupling is now on;Pcoupl = berendsen ；NO：无压力耦合，盒子尺寸大小固定，berendsen:每个时间步长都会重新度量盒子大小，Parrinello-Rahman;Pcoupltype = semiisotropic;tau_p = 1.0 1.0 ；耦合时间常数;compressibility = 0 4.5e-5 ；压缩系数;ref_p = 1.0 1.0 ；参考压强; Generate velocites is off at 300 K.gen_vel = no ；no：初始速度为零yes：按照麦克斯韦分布设定初始速度gen_temp = 300.0 ；麦克斯韦分布的温度gen_seed = 173529 ；使用随机发生器来产生随机速度(time() + getpid()) % 1000000。

MSDP（组播源发现协议）当网络跨越了公网，或者网络需要各自独立时，如果每个独立的网络，或者是每个AS之间都需要组播通信的情况下，我们需要在不影响网络独立的前提下连通网络间的组播。

不各个独立的网络中，又希望自己的组播路由器可以由自己完全控制，那么就需要将各个网络配置成独立的PIM-SM域。

要将不同的PIM-SM域之间连通组播，就必须先有正常的组播树，而PIM-SM组播树的建立，必须了解到网络中的RP 信息，以及组播源的位置。

要连通不同的PIM-SM域，就必须在域之间建立MSDP 连接，MSDP在PIM-SM域间传递组播源的信息，以及保持域间RP的信息。

在使用MSDP将多个PIM-SM域连接时，每一个PIM-SM都可以在域中配置各自的RP，以实现自治。

在不同的PIM-SM域之间建立MSDP连接时，是使用TCP 639，IP地址高的初始化TCP连接，60秒一次keepalive,75秒后没数据或keepalive则重建TCP。

建立连接的双方均是各自区域的RP，组播源向RP注册之后，那么RP将这些源信息通过在MSDP 连接上发送Source-Active (SA)到远程RP，以提供组播源的信息。

因为RP收到Source-Active (SA)后，也是要做RPF检测的，检测是根据BGP来做的，在这里，需要使用MP-BGP之组播MP-BGP，组成员的网络信息和建立MSDP连接的peer地址理论上都需要在MP-BGP中进行通告，一是防止RPF检测失败，二是由此来决定组播数据的传递，所以十分重要。

但是如果不需要在PIM-SM域之间开启MP-BGP，就会有RPF检测失败的危险，失败后，Source-Active (SA)将被丢弃，所以要想在不开启MP-BGP的情况下，又要接收所有的Source-Active (SA)，则将接收端配置成default MSDP,那么该域将接收任何SA 信息。

在配置default MSDP时，需要指定从何处接收SA，就需要指定对端MSDP peer，使用ip msdp default-peer指定，之后从对端过来的SA将不做RPF检测而完全被接收。

TSL UMD ProtocolIntroductionThe TSL protocols are widely implemented throughout the industry, especially for Multiviewer use.There is no charge for the use of these protocols.•UMD V3.1 is the TSL basic industry standard serial protocol.•UMD V4.0 extends the basic V3.1 protocol to add full control of text and tally lamp colours.These two protocols can also be implemented over UDP/IP where each UDP packet contains one serial data packet.•UMD V5.0 is a new protocol, specifically aimed at multiviewer display devices, over Ethernet.The following document describes these protocols.Note these protocols are published without technical support; however In case of difficulty please email tim.whittaker@.Protocol V3.11.0 ScopeThis protocol sets out to define the method of communication between a TSL controller and peripheral devices on a multi-drop device bus.The protocol described is for one way communication only. It details physical layer, link layer and message structure.2.0 ElectricalRS 422/ RS 4858 bit data1 stopeven parity38k4 baud3.0 Dynamic UMD Protocol----------------------------------------------------------------| HEADER | CONTROL BYTE | DISPLAY DATA |----------------------------------------------------------------Header = Display address (0-126) + 80 hex(1 byte) ( control byte and display datawill be sent )Control bit 0 = tally 1 ( 1=on, 0=off )(1 byte) bit 1 = tally 2 ( 1=on, 0=off )bit 2 = tally 3 ( 1=on, 0=off )bit 3 = tally 4 ( 1=on, 0=off )bits 4-5 = brightness databit 4 = 0, bit 5 = 0 (0 brightness)bit 4 = 0, bit 5 = 1 (1/7 brightness)bit 4 = 1, bit 5 = 0 (1/2 brightness)bit 4 = 1, bit 5 = 1 (full brightness)bit 6 = reserved (clear to 0)bit 7 = cleared to 0Display Data = 16 displayable ASCII characters(16 bytes) in the range 20 hex to 7E hex.All 16 characters must be sent.4.0 Single Dynamic DisplaysFor 8 character displays only the first 8 characters of thedisplay data are used, the remaining 8 are needed just forpadding.Only tallies 1&2 are use for single displays.5.0Dual Dynamic DisplaysDual 8 character displays are treated as a single display of16 characters, the first 8 characters for the left-hand sideand the second 8 characters for the right-hand side.Tallies 1&2 are for the left display and tallies 3&4 for theright display.6.0 Triple/Quad Dynamic DisplaysThese units take two addresses.Address 1, for display 1, tally 1 & 2Address 1 for display 2, tally 3 & 4Address 2 for display 3, tally 5 & 6Address 2 for display 4, tally 7 & 8Protocol V4.0Summary of EnhancementsTo support multiple tally channels, more tally control bits are added. Full compatibility withV3.1 (1994) is maintained. Future revisions provided for with version/byte count information. V3.1 HeaderThe current format is retained up to and including the final character of the data field;<0x80+addr><CTRL><DATA>where CTRL is :bit 7: 0bit 6: 0 for display data, 1 for command databit 5: brightness MSBbit 4: brightness LSBbit 3: tally 3bit 2: tally 2bit 1: tally 1bit 0: tally 0and DATA is:16 ASCI characters for messages with CTRL.6 = 0 (i.e. display data messages)For CTRL.6=1, DATA is defined by the control code formed by CTRL5:0.NB Version 4.0 enhancements only apply to display data messages; command messages are V4.0 EnhancementsV4.0 and above messages are recognised as having further data following the last byte of<DATA>, as follows:<0x80+addr><CTRL><DATA><CHKSUM><VBC><XDATA>CHKSUM = (2’s complement of (sum of all V3.1 bytes)) modulo 128(i.e. hdr+CTRL+DATA)VBC is:Bit 7: 0Bit 6-4: minor Version (V4.0 = 0)Bit 3-0 Byte count of XDATA<XDATA> is defined by minor Version number.Currently the following is defined:-Minor Version = 0 (i.e. V4.0)XDATA consists of 2 bytes:Xbyte 1 has 6 tally bits for Display L, Xbyte 2 has 6 tally bits for display R.The 6 bits consist of 2 bits each for the LH tally, text, and RH tally as follows:Bit 7 0Bit 6 Reserved (ignore (RX) or set to 0 (TX))Bit 5: LH MSBBit 4: LH LSBBit 3: Txt MSBBit 2: Txt LSBBit 1: RH MSBBit 0: RH LSB2 Bit values are:0 = OFF; 1 = RED, 2 = GREEN, 3 = AMBER.The four original V3.1 tally bits (in the CTRL packet) are now separately mapped to the four parallel tally outputs from the display.Protocol V5.0OverviewThis protocol is a new 16 bit UMD protocol, with no reverse compatibility to previous TSL UMD protocols.The primary points for this protocol to provide over previous versions are as follows:1. Display addressing up to 65,535 per screen2. ASCII or Unicode character sets3. Variable length mnemonics4. IP based packet communication, with optional wrapper for stream based comms5. Multiple display updates per packetPhysical LayerPackets are sent via UDP. Maximum packet length is 2048 bytes.Optionally, the protocol can operate over TCP/IP, or any other byte stream interface, with the following wrapper scheme:DLE is defined as 0xFESTX is defined as 0x02Packet start is delimited by the sequence DLE/STX.Any occurrence of the DLE character in the packet is byte stuffed to DLE/DLE.Any byte count fields in the packet are not affected by the byte stuffing.Message Format16 bit values are sent as little-endian, i.e. LSB/MSB.The packet is defined as follows:PBC / VER / FLAGS / SCREEN / (<DMSG> ( / <DMSG>)…) or (SCONTROL)PBC (16 bit):Total byte count of following packetVER (8 bit):Minor version number (e.g. V5.00, VER = 0). Note this byte can be used as versioning control for the following definitions. Whilst any future changes to this protocol will aim to be backward compatible, this is not guaranteed.FLAGS (8 bit):Defined as follows:Bit 0: Clear for ASCII based strings in packet, set for Unicode UTF-16LEBit 1: If set, data after SCREEN is screen control data (SCONTROL) – otherwise it’s display message data (DMSG)Bit 2-7: Reserved (clear to 0)SCREEN (16 bit):Primary index for use where each screen entity would have display indices (defined below) starting from 0.Index 0xFFFF is reserved as a “Broadcast” to all screens.If not used, set to 0.Display Message (<DMSG>) DefinitionThis message definition is sent per display, and there can be several in a packet (up to max packet length). Constructed as follows:INDEX / CONTROL / (LENGTH / TEXT) or (CONTROL DATA)INDEX (16 bit):The 0 based address of the display, up to 65534 (0xFFFE). Address 0xFFFF is reserved as a “Broadcast” address to all displays.CONTROL (16 bit):Display control and tally data as follows:Bit 0-1: RH Tally Lamp stateBit 2-3: Text Tally stateBit 4-5: LH Tally Lamp stateBit 6-7: Brightness value (range 0-3)Bit 8-14: Reserved (clear to 0)Bit 15: Control Data: following data to be interpreted as Control data ratherthan Display data when set to 1.2 Bit Tally values are:0 = OFF, 1 = RED, 2 = GREEN, 3 = AMBER.Display Data: (CONTROL bit 15 is cleared to 0)LENGTH (16 bit):Byte count of following text.TEXT:UMD text, format defined by FLAGS byte.Control Data: (CONTROL bit 15 is set to 1)Not defined in this version of protocol.Screen control (SCONTROL) Definition (FLAGS bit 1 is set to 1)Not defined in this version of protocol.。

KSZ8851-16MLL/MLLI/MLLUSingle-Port Ethernet MAC Controllerwith 8-Bit or 16-Bit Non-PCI InterfaceRevision 2.2General DescriptionThe KSZ8851M-series is a single-port controller chip witha non-PCI CPU interface and is available in 8-bit and 16-bit bus designs. This datasheet describes the 48-pin LQFPKSZ8851-16MLL for applications requiring high-performance from single-port Ethernet Controller with 8-bitor 16-bit generic processor interface. The KSZ8851-16MLL offers the most cost-effective solution for addinghigh-throughput Ethernet connectivity to traditionalembedded systems.The KSZ8851-16MLL is a single chip, mixed analog/digitaldevice offering Wake-on-LAN technology for effectivelyaddressing Fast Ethernet applications. It consists of a fastEthernet MAC controller, an 8-bit or 16-bit generic hostprocessor interface and incorporates a unique dynamicmemory pointer with 4-byte buffer boundary and a fullyutilizable 18KB for both TX (allocated 6KB) and RX(allocated 12KB) directions in host buffer interface.The KSZ8851-16MLL is designed to be fully compliant withthe appropriate IEEE 802.3 standards. An industrialtemperature-grade version of the KSZ8851-16MLLI and aqualified AEC-Q100 Automotive version of the KSZ8851-16MLLU are also available (see “Ordering Information”section).LinkMD®Physical signal transmission and reception are enhancedthrough the use of analog circuitry. This makes the designmore efficient and allows lower-power consumption. TheKSZ8851-16MLL is designed using a low-power CMOSprocess that features a single 3.3V power supply withoptions for 1.8V, 2.5V or 3.3V VDD I/O. The deviceincludes an extensive feature set that offers managementinformation base (MIB) counters and CPU control/datainterfaces with single shared data bus timing.The KSZ8851-16MLL includes a unique cable diagnosticsfeature called LinkMD®. This feature determines the lengthof the cabling plant and also ascertains if there is an openor short condition in the cable. Accompanying softwareenables the cable length and cable conditions to beconveniently displayed. In addition, the KSZ8851-16MLLsupports Hewlett Packard (HP) Auto-MDIX therebyeliminating the need to differentiate between straight orcrossover cables in applications.Functional DiagramFigure 1. KSZ8851-16MLL/MLLI Functional DiagramFeatures•Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3µ standards •Designed for high performance and high throughput applications•Supports 10BASE-T/100BASE-TX•Supports IEEE 802.3x full-duplex flow control and half-duplex backpressure collision flow control •Supports DMA-slave burst data read and write transfers•Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking•Supports IPv6 TCP/UDP/ICMP checksum generation and checking•Automatic 32-bit CRC generation and checking •Simple SRAM-like host interface easily connects to most common embedded MCUs.•Supports multiple data frames for receive without address bus and byte-enable signals•Supports both Big- and Little-Endian processors •Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable low, highand overrun watermark for flow control in RX FIFO •Shared data bus for Data, Address and Byte Enable •Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization•Powerful and flexible address filtering scheme •Optional to use external serial EEPROM configuration for MAC address•Single 25MHz reference clock for both PHY and MAC •HBM ESD Rating 6kVPower Modes, Power Supplies, and Packaging •Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD I/O•Built-in integrated 3.3V or 2.5V to 1.8V low noise regulator (LDO) for core and analog blocks •Enhanced power management feature with energy detect mode and soft power-down mode to ensurelow-power dissipation during device idle periodsComprehensive LED indicator support for link, activity and 10/100 speed (2 LEDs) - User programmable •Low-power CMOS design•Commercial Temperature Range: 0°C to +70°C •Industrial Temperature Range: –40°C to +85°C •Flexible package options available in 48-pin (7mm × 7mm) LQFP KSZ8851-16MLL or 128-pinPQFP KSZ8851-16/32MQLAdditional FeaturesIn addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLL offers:•Flexible 8-bit and 16-bit generic host processor interfaces with same access time and single bustiming to any I/O registers and RX/TX FIFO buffers •Supports to add two-byte before frame header in order for IP frame content with double word boundary •Micrel LinkMD® cable diagnostic capabilities to determine cable length, diagnose faulty cables, anddetermine distance to fault•Wake-on-LAN functionality– Incorporates Magic Packet™, wake-up frame, network link state, and detection of energy signaltechnology•HP Auto MDI-X™ crossover with disable/enable option •Ability to transmit and receive frames up to 2000 bytes Network Features•10BASE-T and 100BASE-TX physical layer support •Auto-negotiation: 10/100 Mbps full and half duplex •Adaptive equalizer•Baseline wander correctionApplications•Video/Audio Distribution Systems•High-end Cable, Satellite, and IP set-top boxes •Video over IP and IPTV•Voice over IP (VoIP) and Analog Telephone Adapters (ATA)•Industrial Control in Latency Critical Applications •Home Base Station with Ethernet Connection •Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves)•Security, Motion Control and Surveillance Cameras •In-vehicle Diagnostics (OBD) & software download Markets•Fast Ethernet•Embedded Ethernet•Industrial Ethernet•Embedded Systems•Automotive EthernetOrdering InformationPart Number Temperature Range Package Lead Finish KSZ8851-16MLL 0°C to 70°C 48-Pin LQFP Pb-Free KSZ8851-16MLLI –40°C to +85°C 48-Pin LQFP Pb-Free KSZ8851-16MLLU(Automotive AEC-Q100 qualified)–40°C to +85°C 48-Pin LQFP Pb-Free KSZ8851-16MLL-Eval Evaluation Board for the KSZ8851-16MLLRevision HistoryRevision Date Summary of Changes1.0 06/30/2008 First released Information.1.1 2/13/2009 Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table content and description.2.0 8/31/2009 Change revision ID from “0” to “1” in CIDER (0xc0) register. Update pins 8, 14 and 29 description for 1.8V VDD_IO supply. To add the command write (CMD=1) address index register in order for software to read back the CMD register value. To enable software read or write external EEPROM.2.104/30/2012 In 16-bit bus mode, the SD1 bit must set to “1” when CMD = 1 during DMA access. Remove auto-enqueue function, add the reset circuit. Update the description for the register PMECR Bits [1,0]. Add KSZ8851MLLU Automotive part. Add the description for the register TXCR bit 7. Update read/write timing diagram for Asynchronous Cycle. Add power sequence descriptions in the reset timing section.2.203/04/2014 Remove auto-enqueue function for transmit, Update the description for section of Asynchronous Interface. Update read/write timing diagram and table, add notes for timing table ,CIDER and RXFCTR registers. Update the defination for Register P1CR bit [9],P1MBCR bit [4] and RX/TX pair. Update the description in Half-Duplex Backpressure section. Change TTL to CMOS and updates min/max I/O voltage in different VDDIO.ContentsList of Figures (7)List of Tables (8)Pin Configuration (9)Pin Description (10)Pin for Strap-In Options (13)Functional Description (14)Functional Overview (14)Rx unused block disabled (14)Wake-up Packet (16)Physical Layer Transceiver (PHY) (17)Straight Cable (18)Crossover Cable (19)Access (21)Usage (21)Frame Queue (RXQ) Frame Format (29)EEPROM Interface (31)CPU Interface I/O Registers (33)I/O Registers (33)Internal I/O Registers Space Mapping (33)CIDER (37)0x887x (37)Reserved (38)Do Not Care (38)None (38)Register Map: MAC, PHY and QMU (39)Bit Type Definition (39)0x00 – 0x07: Reserved (39)Chip Configuration Register (0x08 – 0x09): CCR (39)0x0A – 0x0F: Reserved (39)Host MAC Address Registers: MARL, MARM and MARH (40)Host MAC Address Register Low (0x10 – 0x11): MARL (40)Host MAC Address Register Middle (0x12 – 0x13): MARM (40)Host MAC Address Register High (0x14 – 0x15): MARH (40)0x16 – 0x1F: Reserved (40)On-Chip Bus Control Register (0x20 – 0x21): OBCR (41)EEPROM Control Register (0x22 – 0x23): EEPCR (41)Memory BIST Info Register (0x24 – 0x25): MBIR (42)Global Reset Register (0x26 – 0x27): GRR (42)0x28 – 0x29: Reserved (42)Wakeup Frame Control Register (0x2A – 0x2B): WFCR (43)0x2C – 0x2F: Reserved (43)Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 (43)Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 (43)Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 (44)Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 (44)Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 (44)Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 (44)0x3C – 0x3F: Reserved (44)Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 (45)Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 (45)Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 (45)Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 (45)0x4C – 0x4F: Reserved (45)Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 (45)Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 (46)Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 (46)Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 (46)Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 (46)Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 (46)0x5C – 0x5F: Reserved (46)Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 (46)Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 (47)Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 (47)Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 (47)Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 (47)Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 (47)0x6C – 0x6F: Reserved (47)Transmit Control Register (0x70 – 0x71): TXCR (48)Transmit Status Register (0x72 – 0x73): TXSR (49)Receive Control Register 1 (0x74 – 0x75): RXCR1 (49)Receive Control Register 2 (0x76 – 0x77): RXCR2 (50)TXQ Memory Information Register (0x78 – 0x79): TXMIR (51)0x7A – 0x7B: Reserved (51)Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (51)Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR (52)TXQ Command Register (0x80 – 0x81): TXQCR (52)RXQ Command Register (0x82 – 0x83): RXQCR (53)TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR (54)RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR (54)0x88 – 0x8B: Reserved (55)RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR (55)RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR (55)Interrupt Enable Register (0x90 – 0x91): IER (55)Interrupt Status Register (0x92 – 0x93): ISR (56)0x94 – 0x9B: Reserved (57)RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR (57)TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR (57)MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0 (58)MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1 (58)MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2 (58)MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3 (58)0xA8 – 0xAF: Reserved (58)Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR (58)Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR (59)Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR (59)0xB6 – 0xBF: Reserved (59)Chip ID and Enable Register (0xC0 – 0xC1): CIDER (59)0xC2 – 0xC5: Reserved (59)0xCA – 0xCF: Reserved (60)Indirect Access Data Low Register (0xD0 – 0xD1): IADLR (60)Indirect Access Data High Register (0xD2 – 0xD3): IADHR (60)Power Management Event Control Register (0xD4 – 0xD5): PMECR (61)Go-Sleep and Wake-Up Time Register (0xD6 – 0xD7): GSWUTR (62)PHY Reset Register (0xD8 – 0xD9): PHYRR (62)0xDA – 0xDF: Reserved (62)0xE0 – 0xE3: Reserved (62)PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR (63)PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR (64)PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR (64)PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR (64)PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR (65)PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR (66)0xF0 – 0xF3: Reserved (66)Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD (66)Port 1 Control Register (0xF6 – 0xF7): P1CR (67)Port 1 Status Register (0xF8 – 0xF9): P1SR (68)0xFA – 0xFF: Reserved (69)MIB (Management Information Base) Counters (70)Absolute Maximum Ratings (73)Operating Ratings (73)Electrical Characteristics (73)Timing Specifications (75)Asynchronous Read and Write Timing (Processor read and write) (75)Selection of Isolation Transformers (80)Selection of Reference Crystal (80)Package Information (81)Acronyms and Glossary (82)Figure 2. 48-Pin LQFP (9)Figure 3. Typical Straight Cable Connection (18)Figure 4. Typical Crossover Cable Connection (19)Figure 5. Auto Negotiation And Parallel Operation (20)Figure 6. Ksz8851-16mll 8-Bit And 16-Bit Data Bus Connections (25)Figure 8. Host Rx Single Or Multiple Frames In Auto-Dequeue Flow Diagram (30)Figure 9. Phy Port 1 Near-End (Remote) And Host Far-End (Local) Loopback Paths (32)Figure 10. Asynchronous Cycle (75)Figure 11. Auto Negotiation Timing (76)Figure 12. Reset Timing (77)Figure 13. Eeprom Read Cycle Timing Diagram (78)Figure 14. Recommended Reset Circuit (79)Figure 15. Recommended Circuit For Interfacing with Cpu/Fpga Reset (79)Table 1. Internal Function Blocks Status (14)Table 2. Mdi/Mdi-X Pin Definitions (18)Table 3. Address Filtering Scheme (23)Table 4. Bus Interface Unit Signal Grouping (24)Table 5. Frame Format For Transmit Queue (26)Table 6. Transmit Control Word Bit Fields (26)Table 7. Transmit Byte Count Format (27)Table 8. Registers Setting For Transmit Function Block (27)Table 9. Frame Format For Receive Queue (29)Table 10. Registers Setting For Receive Function Block (29)Table 11. Ksz8851-16mll Eeprom Format (31)Table 12. Format Of Mib Counters (70)Table 13. Port 1 Mib Counters Indirect Memory Offsets (71)Table 14. Asynchronous Cycle Timing Parameters (75)Table 15. Auto Negotiation Timing Parameters (76)Table 16. Reset Timing Parameters (77)Table 17. Eeprom Timing Parameters (78)Table 18. Transformer Selection Criteria (80)Table 19. Qualified Single Port Magnetics (80)Table 20. Typical Reference Crystal Characteristics (80)Figure 2. 48-Pin LQFPPin Number Pin Name Type Pin Function1 P1LED1 IPU/O Programmable LED output to indicate port activity/status.LED is ON when output is LOW; LED is OFF when output is HIGH.Port 1 LED indicators1 defined as follows:Chip Global Control Register: CGCR bit [9]0 (Default) 1P1LED1 100BT ACTP1LED0 LINK/ACT LINK1. Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;Speed = LED On (100BASE-T); LED Off (10BASE-T)Config Mode: The P1LED1 pull-up/pull-down value is latched as 16/8-bit mode during power-up / reset. See “Strapping Options” section for details2 P1LED0 OPU3 PME OPU Power Management Event (default active low): It is asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low power mode.4 INTRN OPU Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7K pull-up resistor.5 RDN IPU Read Strobe NotAsynchronous read strobe, active low to indicate read cycle.6 WRN IPU Write Strobe NotAsynchronous write strobe, active low to indicate write cycle.7 DGND GND Digital ground8 VDD_CO1.8 P 1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29 (VDD_D1.8) for core VDD supply.If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29 (VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46 (VDD_IO) with appropriate filtering.9 EED_IO IPD/O In/Out Data from/to external EEPROM.Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during power-up / reset. See “Strapping Options” section for details10 EESK IPD/O EEPROM Serial ClockA 4µs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip bus speed @ 125MHz) serial output clock cycle to load configuration data from the serial EEPROM.Config Mode: The pull-up/pull-down value is latched as big/little endian mode during power-up / reset. See “Strapping Options” section for details11 CMD IPD Command TypeThis command input decides the SD[15:0] shared data bus access information.When command input is low, the access of shared data bus is for data access in 16-bit mode shared data bus SD[15:0] or in 8-bit mode shared data bus SD[7:0].When command input is high, the access of shared data bus is for address A[7:2] access at shared data bus SD[7:2], byte enable BE[3:0] at SD[15:12] and the SD[11:8] is “Do Not Care” in 16-bit mode. It is for address A[7:0] access at SD[7:0] in 8-bit mode.Pin Number Pin Name Type Pin Function12 CSN IPU Chip Select NotChip select for the shared data bus access enable, active Low.13 AGND GND Analog ground14 VDD_A1.8 P 1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.15 EECS OPD EEPROM Chip SelectThis signal is used to select an external EEPROM device.16 RXP1 I/O Port 1 physical receive signal (+ differential).17 RXM1 I/O Port 1 physical receive signal (– differential).18 AGND GND Analog ground.19 TXP1 I/O Port 1 physical transmit signal (+ differential).20 TXM1 I/O Port 1 physical transmit signal (– differential).21 VDD_A3.3 P 3.3V analog VDD input power supply with well decoupling capacitors.22 ISET O Set physical transmits output current.Pull-down this pin with a 3.01K 1% resistor to ground.23 RSTN IPU Reset NotHardware reset pin (active Low). This reset input is required minimum of 10ms low after stable supply voltage 3.3V.24 X1 I 25MHz crystal or oscillator clock connection.Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.Note: Clock requirement is ±50ppm for either crystal or oscillator.25 X2 O26 DGND GND Digital ground27 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.28 DGND GND Digital ground29 VDD_D1.8 P 1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.30 SD15 I/O (PD) Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3 at double-word boundary access (BE3, 4th byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.31 SD14 I/O (PD) Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2 at double-word boundary access (BE2, 3rd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.32 SD13 I/O (PD) Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1 at double-word boundary access (BE1, 2nd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.33 SD12 I/O (PD) Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0 at double-word boundary access (BE0, 1st byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.34 SD11 I/O (PD) Shared Data Bus bit 11. Data D11 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.35 SD10 I/O (PD) Shared Data Bus bit 10. Data D10 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.Pin Number Pin Name Type Pin Function36 SD9 I/O (PD) Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.37 DGND GND Digital ground38 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.39 SD8 I/O (PD) Shared Data Bus bit 8. Data D8 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.40 SD7 I/O (PD) Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7 access when CMD=1.41 SD6 I/O (PD) Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6 access when CMD=1.42 SD5 I/O (PD) Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5 access when CMD=1.43 SD4 I/O (PD) Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4 access when CMD=1.44 SD3 I/O (PD) Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3 access when CMD=1.45 SD2 I/O (PD) Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2 access when CMD=1.46 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.47 SD1 I/O (PD) Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.48 SD0 I/O (PD) Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.Legend:P = Power supplyGND = GroundI/O = Bi-directionalI = InputO = Output.IPD = Input with internal pull-down (58K ±30%).IPU = Input with internal pull-up (58K ±30%).OPD = Output with internal pull-down (58K ±30%).OPU = Output with internal pull-up (58K ±30%).IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise. IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise. I/O (PD) = Input/Output with internal pull-down (58K ±30%).Pin for Strap-In OptionsPin Number Pin Name Type Pin Function1 P1LED1 IPU/O 8 or 16-bit bus mode select during power-up / reset: NC or Pull-up (default ) = 16-bit busPull-down = 8-bit busThis pin value is also latched into register CCR, bit 6/7.9 EED_IO IPD/O EEPROM select during power-up / reset:Pull-up = EEPROM presentNC or Pull-down (default ) = EEPROM not present This pin value is latched into register CCR, bit 9.10 EESK IPD/O Endian mode select during power-up / reset:Pull-up = Big EndianNC or Pull-down (default) = Little EndianThis pin value is latched into register CCR, bit 10.When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode.Note: IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.Pin strap-ins are latched during power-up or reset.Functional DescriptionThe KSZ8851-16MLL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8851-16MLL via an 8-bit or 16-bit host bus interface. The KSZ8851-16MLL is fully compliant to IEEE802.3u standards.Functional OverviewPower ManagementThe KSZ8851-16MLL supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are four operation modes under the power management function which is controlled by two bits in PMECR (0xD4) register as shown below:PMECR[1:0] = 00 Normal Operation ModePMECR[1:0] = 01 Energy Detect ModePMECR[1:0] = 10 Soft Power-down modePMECR[1:0] = 11 Power-saving modeTable 1 indicates all internal function blocks status under four different power management operation modes.KSZ8851-16MLL Function BlocksPower Management Operation ModesNormal Mode Power-saving mode Energy Detect Mode Soft Power-Down ModeInternal PLL Clock Enabled Enabled Disabled DisabledTx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx DisabledMAC Enabled Enabled Disabled DisabledHost Interface Enabled Enabled Disabled DisabledTable 1. Internal Function Blocks StatusNormal Operation ModeThis is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When KSZ8851-16MLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write.During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal operation mode to any one of the other three power management operation modes.Energy Detect ModeThe energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present or it is connected to a powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can automatically power up to normal power state in energy detect mode.Energy detect mode consists of two states, normal power state and low power state. While in low power state, the KSZ8851-16MLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851-16MLL is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-Sleep time in GSWUTR register, KSZ8851-16MLL will go into a low power state. When KSZ8851-16MLL is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for a time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851-16MLL will enter either the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if both auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.The KSZ8851-16MLL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register or generate interrupt to signal an energy detect event occurred if the corresponding enable bit[2] is set in IER (0x90) register. Once the power management unit detects the PME output asserted or interrupt active, it will power up the host CPU and issue a wakeup command which is a read cycle to read the Globe Reset Register (GRR at 0x26) to wake up the KSZ8851-16MLL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled. When KSZ8851-16MLL is at normal power state, it is able to transmit or receive packet from the cable.Soft Power-Down ModeThe soft power-down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851-16MLL is in this mode, all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host interface is only used to wake-up this device from current soft power-down mode to normal operation mode.In order to go back the normal operation mode from this soft power-down mode, the only way to leave this mode is through a host wake-up command which the CPU issues to read the Globe Reset Register (GRR at 0x26).Power-Saving ModeThe power-saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851M is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from power-saving mode.During this power-saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in P1SCLMD register to transit the current power-saving mode to any one of the other three power management operation modes. Wake-on-LANWake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. The KSZ8851-16MLL controller can be programmed to notify the host of the wake-up frame detection with the assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working).A wake-up signal is caused by:1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)2. Detection of a linkup in the network link state (bit 3 in ISR register)3. Receipt of a Magic Packet (bit 4 in ISR register)4. Receipt of a network wake-up frame (bit 5 in ISR register)There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own way.Detection of EnergyThe energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. Detection of LinkupLink status wake events are useful to indicate a linkup in the network’s connectivity status.。

DMVPN原理什么是DMVPNDMVPN（Dynamic Multipoint Virtual Private Network）是一种网络技术，可以实现在广域网（WAN）中建立安全的虚拟专用网络（VPN）。

DMVPN具有动态路由、灵活性和可扩展性等特点，适用于大规模网络中的分支机构和远程办公场景。

DMVPN的工作原理DMVPN的工作原理涉及到几个关键组件和协议，包括NHRP（Next Hop Resolution Protocol）、GRE（Generic Routing Encapsulation）、IPsec（Internet Protocol Security）和动态路由协议。

1. NHRPNHRP是DMVPN的核心协议之一，负责建立和维护动态多点隧道。

它允许DMVPN网络中的路由器动态地解析其他路由器的IP地址和公共密钥，从而实现路由器之间的直接通信。

2. GREGRE是一种隧道协议，用于在公共网络上封装和传输数据包。

在DMVPN中，GRE用于在不可信的WAN上建立安全的虚拟专用网络。

3. IPsecIPsec是一种网络安全协议，用于对数据进行加密和身份验证。

在DMVPN中，IPsec用于保护GRE隧道中传输的数据，确保数据的机密性和完整性。

4. 动态路由协议DMVPN支持各种动态路由协议，如OSPF、EIGRP和BGP等。

这些协议负责在DMVPN 网络中交换路由信息，实现动态路由的功能。

DMVPN的优势DMVPN相比传统的VPN技术具有以下优势：1.灵活性：DMVPN可以适应不同规模和拓扑的网络，可以轻松地添加、删除或修改分支机构，而无需对整个网络进行重新配置。

2.可扩展性：DMVPN支持动态多点隧道，可以在网络中添加新的分支机构，而无需手动配置每个分支机构的隧道。

3.简化管理：DMVPN使用动态路由协议，可以自动学习和传播路由信息，减少了管理员的配置工作。

4.减少网络延迟：DMVPN使用GRE隧道和IPsec加密，可以在公共网络上建立安全的虚拟专用网络，减少了数据传输的延迟。

CISCO VPN技术DMvpn详解（一）利用IPSec隧道在Internet上进行安全的数据传输，是目前公司总部与分支通讯的主要解决方案。

它的商业价值，这里就不提了，随便找个文档也会侃半天的。

IPSec网络的拓扑可以是星形结构（hub−and−spoke）也可以是网状结构（full mesh）。

实际应用中，数据流量主要分布在分支与中心之间，分支与分支之间的流量分布较少，所以星形结构（hub−and−spoke）通常是最常用的，并且它更经济。

因为星形结构（hub−and−spoke）比网状结构（full mesh）使用更少的点到点链路，可以减少线路费用。

在星形拓扑中，分支机构到分支机构（spoke −to−spoke）的连通不需要额外的通讯费用。

但在星形结构中，分支到分支的通信必须跨越中心，这会耗费中心的资源并引入延时。

尤其在用IPSec加密时，中心需要在发送数据分支的隧道上解密，而在接收数据的分支隧道上重新加密。

还有一种情况是：通讯的两个分支在同一个城市，而中心在另一个城市，这便引入了不必要的延时。

当星形IPSec网络（hub−and−spoke）规模不断扩展时，传统VPN的配置则愈加繁琐，且不便于维护和排错。

因此IP数据包的动态路由将非常有意义。

但IPSec隧道和动态路由协议之间存在一个基础问题，动态路由协议依赖于多播或广播包进行路由更新，而IPSec隧道不支持多播或广播包的加密。

这里便引入了动态多点VPN （DMVPN）的概念。

这里将引入两个协议：GRE 和NHRPGRE：通用路由封装。

由IETF在RFC 2784中定义。

它是一个可在任意一种网络层协议上封装任意一个其它网络层协议的协议。

GRE将有效载荷封装在一个GRE包中，然后再将此GRE包封装基于实际应用的传输协议上进行转发。

（我觉得：GRE类似木马的壳。

^_^）IPSec不支持广播和组播传输，可是GRE能很好的支持运载广播和组播包到对端，并且GRE 隧道的数据包是单播的。

MSDP简介 MSDP是Multicast Source Discovery Protocol（组播源发现协议）的简称，是为了解决多个PIM-SM（Protocol Independent Multicast Sparse Mode，协议无关组播—稀疏模式）域之间的互连而开发的一种域间组播解决方案，用来发现其他PIM-SM域内的组播源信息。

MSDP目前只支持在IPv4网络部署，域内组播路由协议必须是PIM-SM。

MSDP仅对ASM（Any-Source Multicast）模型有意义。

目的： PIM-SM模式下，源端DR（Designated Router）向RP注册，成员端DR也会向RP发起加入报文，因此RP可以获取到所有组播源和组播组成员的信息。

随着网络规模的增大以及便于控制组播资源，管理员可能会将一个PIM网络划分为多个PIM-SM域，此时各个域中的RP无法了解其他域中的组播源信息。

MSDP可以解决这一问题。

MSDP通过在不同PIM-SM域的路由器（通常在RP上）之间建立MSDP对等体，MSDP对等体之间交互SA（Source-Active）消息，共享组播源信息，最终可以使一个域内的组播用户接收到其他域的组播源发送的组播数据。

MSDP用于在ISP（Internet Service Provider）之间建立对等体。

通常，ISP并不希望借助其他ISP的RP来向自己的用户提供服务。

这一方面是出于安全性考虑，另一方面如果其他ISP的RP发生故障导致业务中断，用户投诉的却是自己的服务。

借助MSDP，每个ISP可以实现依靠自己的RP来向Internet转发和接收组播数据。

尽管MSDP是为域间组播产生的，但它在PIM-SM域内还有着一项特殊的应用——Anycast RP（任播RP）。

Anycast RP是指在同一PIM-SM域内通过设置两个或多个具有相同地址的RP，并在这些RP之间建立MSDP对等体关系，以实现域内各RP之间的负载分担和冗余备份。

dm-verity是一种用于Android系统的完整性验证机制。

它通过在设备的分区上创建一个只读的校验区域，来验证系统分区的完整性。

具体原理如下：
1. 在系统分区上创建一个只读的校验区域，该区域包含了一个校验表和一组校验块。

2. 校验表中记录了系统分区中每个数据块的哈希值。

3. 当设备启动时，系统会加载校验表到内存中。

4. 在系统分区上的每个数据块被读取时，dm-verity 会计算该数据块的哈希值，并与校验表中对应的哈希值进行比较。

5. 如果哈希值匹配，则数据块被认为是完整的，可以继续使用。

6. 如果哈希值不匹配，则数据块被认为是被篡改的，系统会拒绝使用该数据块，并可能触发相应的安全机制。

通过使用dm-verity，Android系统可以在启动时验证系统分区的完整性，以防止恶意软件或未经授权的修改对系统的破坏。

这有助于提高系统的安全性和稳定性。

DMVPN技术原理DMVPN（Dynamic Multipoint Virtual Private Network）是一种使用IPsec（Internet Protocol Security）协议和动态路由协议的远程访问技术，它允许在广域网上建立高度可扩展和高效的虚拟专用网络。

DMVPN通过动态GRE（Generic Routing Encapsulation）隧道和NHRP （Next-Hop Resolution Protocol）协议实现了多点之间的直接通信。

本文将详细介绍DMVPN的技术原理。

DMVPN使用IPsec协议来提供虚拟专用网络的安全和加密。

在IPsec 中，使用了不同的安全协议和算法，如ESP（Encapsulating Security Payload）和AH（Authentication Header）来加密和验证数据包的完整性。

DMVPN使用IPsec提供分支节点之间的安全连接。

DMVPN通过动态GRE隧道来在中心节点和分支节点之间建立直接的点对点通信。

GRE隧道用于将IP数据包封装在IP头中，以在不同网络之间进行传输。

DMVPN中的GRE隧道可以在需要时动态地建立和拆除，这使得DMVPN具有高度可扩展性和灵活性。

动态GRE隧道由网络设备自动创建和管理，无需手动配置。

NHRP协议用于管理DMVPN网络中的寻址和路由信息。

NHRP允许分支节点发现其他分支节点的存在，并建立动态的直接访问路径。

当一个分支节点需要与另一个分支节点通信时，它将通过NHRP协议查询中心节点以获取目标分支节点的IP地址和路由信息。

中心节点将收到的查询信息转发给目标分支节点，建立一条直接的虚拟专用网络连接。

这些直接连接可以通过动态GRE隧道实现，从而实现相同网络中分支节点之间的直接通信。

1.分支节点启动并获取公共IP地址。

2.分支节点通过动态路由协议（如EIGRP、OSPF或BGP）与中心节点建立动态邻居关系。

厚膜电阻网络，双排，模压SIPThick Film Resistor Networks, Dual-In-Line, Molded DIP特性•可提供单个的、总体的以及双终端线路图•0.160"(4.06mm)最大座高，采用坚固的模塑壳体结构•厚膜电阻元件•低温系数 (-55°C 至+125°C) ±100ppm/°C •降低了整体的安装成本•与自动插入设备相兼容•电阻范围宽（10欧至2.2兆欧）•始终如一的性能特性•可提供管式包装•符材料类别：了解合规性定义，敬请访问 /doc?99912* 本数据手册将提供产品是否符合RoHS 指令的信息。

例如采用含铅（Pb ）端子的产品不符合RoHS 指令。

请参见数据手册中的信息/表格，了 解详情。

Notes(1)了解在+25°C 下的电阻功定功率，请参见降额曲线。

(2)可采用更严格的TCR 跟踪。

(3)±2%为标准公差，也可采用±1%和±5%Note •了解有关封装的更多信息，请参考“通孔网络封装”文档 (/doc?31542).AvailableAvailable全球编号/引脚数量原理图额定功耗元件(1)P 70 °CW 电阻范围Ω公差(3)± %温度系数(-55 °C 至 +125 °C)± ppm/°CTCR 跟踪(2)(-55 °C 至 +125 °C)± ppm/°C重量g MDP 14010.12510 至 2.2M 1, 2, 510050 1.3030.25010 至 2.2M 50050.125咨询工厂100MDP 16010.12510 至 2.2M 1, 2, 510050 1.5030.25010 至 2.2M 50050.125咨询工厂100新的全球部件编号: MDP1403100RGD04 (首选的部件编号格式)全球编号引脚数量电阻范围电阻值公差代码封装专用位MDP14 = 14 引脚16 = 16 引脚01 = 总线03 = 绝缘00 = 特定R = ΩK = k ΩM = M Ω10R0 = 10 Ω680K = 680 k Ω1M00 = 1.0 M Ω0000 = 0 Ω 跨接线F = ± 1 %G = ± 2 %J = ± 5 %S = 特定Z = 0 Ω 跨接线E04 = 无铅(Pb)，管装空格=标准型（零件编号）从1至999适用D04 = 锡、铅，管装以往的部件编号实例：MDP1403101G （将被继续采用）MDP 1403101G D04以往的编号引脚数量原理图电阻值公差代码封装新的全球部件编号: MDP1405121CGD04（首选的部件编号格式）全球编号引脚数量电阻范围电阻值公差代码封装专用位MDP14 = 14 引脚16 = 16 引脚05 = 双端子3位数字电阻代码后面是一个阿尔法修改器（参见阻抗代码表)F = ± 1 %G = ± 2 %J = ± 5 %E04 = 无铅(Pb)，管装空格=标准型（零件编号）从1至999适用D04 = 锡、铅，管装以往的部件编号：MDP1405221271G （将被继续采用）MDP 1405221271G D04以往的编号引脚数量原理图电阻值1电阻值2公差代码封装40D G R0013041PD M40D G C 1215041PD M注标准电气规格注全球部件编号信息注尺寸单位：英寸（mm ）Note•了解更多阻抗代码，请参见“双端子阻抗代码表”文档(/doc?31530)。

mdd工程术语MDD（Model-Driven Development）是模型驱动开发的缩写，是一种软件开发方法。

在MDD中，软件系统的开发过程主要依赖于从一个或多个模型中自动生成代码和其他开发资源。

以下是一些与MDD相关的术语：1. 模型（Model）：在MDD中，模型是软件系统的抽象表示，可以是用于描述系统行为、结构和属性的图形化、文本化或数学化的表示。

2. 模型驱动工程（Model-driven Engineering）：模型驱动工程是一种软件工程方法，基于模型，用于系统的设计、分析、实现和维护。

3. 可执行模型（Executable Model）：可执行模型是指能够直接运行的模型，通常可以生成代码或其他可执行形式。

4. 模型转换（Model Transformation）：模型转换是指将一个模型转换为另一个模型的过程，常用于生成代码、验证模型以及其他模型间的转换。

5. 模型驱动架构（Model-driven Architecture，MDA）：MDA是一种MDD的软件开发方法，提供了一种用于描述和转换模型的标准化框架。

6. MDA转换（MDA Transformation）：MDA转换是指基于MDA方法的模型转换过程，通常包括从平台无关的模型转换到平台特定的模型。

7. 模型驱动测试（Model-driven Testing）：模型驱动测试是一种使用模型驱动方法进行软件测试的技术，通过生成测试用例来验证系统模型的正确性和完整性。

8. 模型驱动工具（Model-driven Tool）：模型驱动工具是用于支持MDD开发过程的软件工具，包括模型编辑器、模型转换器、代码生成器等。

9. MDD开发环境（MDD Development Environment）：MDD开发环境是指支持MDD方法的集成开发环境（IDE），提供了一系列与模型驱动开发相关的功能。

10. 模型驱动改进（Model-driven Improvement）：模型驱动改进是指通过引入MDD方法来提高软件系统开发效率和质量的过程。

MDVS 技术手册1. 引言MDVS（Model-Driven Video Streaming）技术是一种基于模型驱动的视频流处理技术，它通过抽象的模型来描述视频流的处理流程，从而实现高效的视频流处理。

本手册旨在为开发者提供详细的MDVS技术指南，帮助开发者快速掌握和应用MDVS技术。

2. MDVS 技术概述MDVS技术是一种新型的视频流处理框架，它允许开发者通过定义模型来描述视频流的处理流程。

这种模型通常包括视频源、处理节点和输出目标三个部分。

通过这种方式，MDVS技术能够实现高度的灵活性和可扩展性，同时也能够提高视频流处理的效率。

3. MDVS 系统架构MDVS系统的架构主要包括以下几个部分：- 视频源：负责提供原始视频流。

- 处理节点：负责对视频流进行处理，如编码、解码、滤波等。

- 输出目标：负责接收处理后的视频流，并进行展示或其他操作。

- 控制器：负责协调各个部分的工作，以及处理用户输入。

4. MDVS 核心组件MDVS的核心组件主要包括以下几个部分：- 模型定义器：负责定义视频流处理的模型。

- 模型解析器：负责解析模型定义器定义的模型。

- 视频处理器：负责根据解析后的模型对视频流进行处理。

- 控制器：负责协调各个组件的工作，以及处理用户输入。

5. MDVS 开发环境搭建要使用MDVS技术进行开发，首先需要搭建开发环境。

这通常包括安装MDVS 的开发工具包、配置开发环境等步骤。

具体的步骤可能会因具体的开发环境和工具而有所不同。

6. MDVS 开发流程MDVS的开发流程通常包括以下几个步骤：1. 定义模型：使用模型定义器定义视频流处理的模型。

2. 解析模型：使用模型解析器解析定义的模型。

3. 编写处理代码：根据解析后的模型编写视频处理的代码。

4. 测试：使用控制器进行测试，确保代码的正确性。

5. 部署：将编写的代码部署到目标环境中。

7. MDVS 调试与测试在MDVS的开发过程中，调试和测试是非常重要的环节。