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逐步减压缩聚法制备高分子量聚乳酸的研究
马海艳;滕翠青;余木火
【期刊名称】《材料科学与工程学报》
【年(卷),期】2007(025)004
【摘要】以L-乳酸单体为原料,用逐步减压缩聚法合成了相对高分子量的聚乳酸.探讨了反应条件如:温度、反应时间、催化剂用量、酯化时间、逐步减压时间等对聚乳酸分子量的影响,并采用FTIR、1H NMR测试手段对聚合物进行了结构表征.结果表明,催化剂用量为0.5wt%,反应温度180℃,先酯化7小时,再逐步减压7小时,然后在高真空度70Pa下反应45小时,可得到重均分子量约为12万的聚乳酸.【总页数】4页(P554-557)
【作者】马海艳;滕翠青;余木火
【作者单位】东华大学材料科学与工程学院,纤维材料改性国家重点实验室,上海,200051;东华大学材料科学与工程学院,纤维材料改性国家重点实验室,上
海,200051;东华大学材料科学与工程学院,纤维材料改性国家重点实验室,上
海,200051
【正文语种】中文
【中图分类】TQ316.4
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DS90LV048A3V LVDS Quad CMOS Differential Line ReceiverGeneral DescriptionThe DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and high data rates.The device is de-signed to support data rates in excess of 400Mbps (200MHz)utilizing Low Voltage Differential Signaling (LVDS)technology.The DS90LV048A accepts low voltage (350mV typical)dif-ferential input signals and translates them to 3V CMOS out-put levels.The receiver supports a TRI-STATE ®function that may be used to multiplex outputs.The receiver also supports open,shorted and terminated (100Ω)input fail-safe.The re-ceiver output will be HIGH for all fail-safe conditions.The DS90LV048A has a flow-through pinout for easy PCB layout.The EN and EN *inputs are ANDed together and control the TRI-STATE outputs.The enables are common to all four re-ceivers.The DS90LV048A and companion LVDS line driver (eg.DS90LV047A)provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.Featuresn >400Mbps (200MHz)switching ratesn Flow-through pinout simplifies PCB layout n 150ps channel-to-channel skew (typical)n 100ps differential skew (typical)n 2.7ns maximum propagation delay n 3.3V power supply designn High impedance LVDS inputs on power down n Low Power design (40mW 3.3V static)n Interoperable with existing 5V LVDS driversn Accepts small swing (350mV typical)differential signal levelsn Supports open,short and terminated input fail-safe n Conforms to ANSI/TIA/EIA-644Standardn Industrial temperature operating range (-40˚C to +85˚C)nAvailable in SOIC and TSSOP packageConnection DiagramFunctional DiagramENABLESINPUTS OUTPUT EN EN*R IN+−R IN−R OUT HL or OpenV ID ≥0.1V H V ID ≤−0.1V L Full Fail-safe OPEN/SHORT or TerminatedHAll other combinations of ENABLE inputs X ZTRI-STATE ®is a registered trademark of National Semiconductor Corporation.Dual-in-LineDS100888-1Order Number DS90LV048ATM,DS90LV048ATMTCSee NS Package Number M16A,MTC16July 1999DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver©1999National Semiconductor Corporation Absolute Maximum Ratings(Note1)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)−0.3V to+4V Input Voltage(R IN+,R IN−)−0.3V to3.9V Enable Input Voltage(EN,EN*)−0.3V to(V CC+0.3V) Output Voltage(R OUT)−0.3V to(V CC+0.3V) Maximum Package Power Dissipation+25˚CM Package1025mW MTC Package866mW Derate M Package8.2mW/˚C above+25˚C Derate MTC Package 6.9mW/˚C above+25˚C Storage Temperature Range−65˚C to+150˚C Lead Temperature Range Soldering(4sec.)+260˚C Maximum Junction Temperature+150˚C ESD Rating(Note10)(HBM,1.5kΩ,100pF)≥10kV (EIAJ,0Ω,200pF)≥1200VRecommended Operating ConditionsMin Typ Max Units Supply Voltage(V CC)+3.0+3.3+3.6V Receiver Input Voltage GND+3.0V Operating Free AirTemperature(T A)−4025+85˚CElectrical CharacteristicsOver Supply Voltage and Operating Temperature ranges,unless otherwise specified.(Notes2,3)Symbol Parameter Conditions Pin Min Typ Max Units V TH Differential Input High Threshold V CM=+1.2V,0.05V,2.95V(Note13)R IN+,+100mV V TL Differential Input Low Threshold R IN−−100mV VCMR Common-Mode Voltage Range VID=200mV pk to pk(Note5)0.1 2.3V I IN Input Current V IN=+2.8V V CC=3.6V or0V−10±5+10µAV IN=0V−10±1+10µAV IN=+3.6V V CC=0V-20±1+20µA V OH Output High Voltage I OH=−0.4mA,V ID=+200mV R OUT 2.7 3.3VI OH=−0.4mA,Input terminated 2.7 3.3VI OH=−0.4mA,Input shorted 2.7 3.3V V OL Output Low Voltage I OL=2mA,V ID=−200mV0.050.25V I OS Output Short Circuit Current Enabled,V OUT=0V(Note11)−15−47−100mA I OZ Output TRI-STATE Current Disabled,V OUT=0V or V CC−10±1+10µAV IH Input High Voltage EN,EN*2.0V CC VV IL Input Low Voltage GND0.8V I I Input Current V IN=0V or V CC,Other Input=V CC orGND−10±5+10µA V CL Input Clamp Voltage I CL=−18mA−1.5−0.8V I CC No Load Supply CurrentReceivers EnabledEN=V CC,Inputs Open V CC915mA I CCZ No Load Supply Current EN=GND,Inputs Open15mAReceivers DisabledSwitching CharacteristicsOver Supply Voltage and Operating Temperature ranges,unless otherwise specified.(Notes3,4,7,8)Symbol Parameter Conditions Min Typ Max Units t PHLD Differential Propagation Delay High to Low C L=15pF 1.2 2.0 2.7ns t PLHD Differential Propagation Delay Low to High V ID=200mV 1.2 1.9 2.7ns t SKD1Differential Pulse Skew|t PHLD−t PLHD|(Note6)(Figure1and Figure2)00.10.4ns t SKD2Differential Channel-to-Channel Skew;same device(Note7)00.150.5ns t SKD3Differential Part to Part Skew(Note8) 1.0ns t SKD4Differential Part to Part Skew(Note9) 1.5ns t TLH Rise Time0.5 1.0ns t THL Fall Time0.35 1.0ns 2Switching Characteristics(Continued)Over Supply Voltage and Operating Temperature ranges,unless otherwise specified.(Notes3,4,7,8)Symbol Parameter Conditions Min Typ Max Units t PHZ Disable Time High to Z R L=2kΩ814nst PLZ Disable Time Low to Z C L=15pF814nst PZH Enable Time Z to High(Figure3and Figure4)914nst PZL Enable Time Z to Low914nsf MAX Maximum Operating Frequency(Note14)All Channels Switching200250MHzNote1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the devices should be operated at these limits.The table of“Electrical Characteristics”specifies conditions of device operation.Note2:Current into device pins is defined as positive.Current out of device pins is defined as negative.All voltages are referenced to ground unless otherwise speci-fied.Note3:All typicals are given for:V CC=+3.3V,T A=+25˚C.Note4:Generator waveform for all tests unless otherwise specified:f=1MHz,Z O=50Ω,t r and t f(0%to100%)≤3ns for R IN.Note5:The VCMR range is reduced for larger VID.Example:if VID=400mV,the VCMR is0.2V to2.2V.The fail-safe condition with inputs shorted is not supported over the common-mode range of0V to2.4V,but is supported only with inputs shorted and no external common-mode voltage applied.A VID up to V CC−0V may be applied to the R IN+/R IN−inputs with the Common-Mode voltage set to V CC/2.Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to400mV.Skew specifications apply for200mV≤VID≤800mV over the common-mode range.Note6:t SKD1is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel Note7:t SKD2,Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs.Note8:t SKD3,part to part skew,is the differential channel-to-channel skew of any event between devices.This specification applies to devices at the same V CC, and within5˚C of each other within the operating temperature range.Note9:t SKD4,part to part skew,is the differential channel-to-channel skew of any event between devices.This specification applies to devices over recommended operating temperature and voltage ranges,and across process distribution.t SKD4is defined as|Max−Min|differential propagation delay.Note10:ESD Rating:HBM(1.5kΩ,100pF)≥10kVEIAJ(0Ω,200pF)≥1200VNote11:Output short circuit current(I OS)is specified as magnitude only,minus sign indicates direction only.Only one output should be shorted at a time,do not exceed maximum junction temperature specification.Note12:C L includes probe and jig capacitance.Note13:V CC is always higher than R IN+and R IN−voltage.R IN−and R IN+are allowed to have a voltage range−0.2V to V CC−VID/2.However,to be compliant with AC specifications,the common voltage range is0.1V to2.3VNote14:f MAX generator input conditions:t r=t f<1ns(0%to100%),50%duty cycle,differential(1.05V to1.35V peak to peak).Output criteria:60/40%duty cycle, V OL(max0.4V),V OH(min2.7V),Load=15pF(stray plus probes).Parameter Measurement InformationDS100888-3FIGURE1.Receiver Propagation Delay and Transition Time Test CircuitDS100888-4FIGURE2.Receiver Propagation Delay and Transition Time Waveforms3Parameter Measurement Information(Continued)Typical ApplicationApplications InformationGeneral application guidelines and hints for LVDS drivers and receivers may be found in the following application notes:LVDS Owner’s Manual (lit #550062-001),AN808,AN977,AN971,AN916,AN805,AN903.LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5.This configuration provides a clean signaling en-vironment for the fast edge rates of the drivers.The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable,a parallel pair cable,or simply PCB traces.Typically,the characteristic impedance ofthe media is in the range of 100Ω.A termination resistor of 100Ω(selected to match the media),and is located as close to the receiver input pins as possible.The termination resis-tor converts the driver output (current mode)into a voltage that is detected by the receiver.Other configurations are possible such as a multi-receiver configuration,but the ef-fects of a mid-stream connector(s),cable stub(s),and other impedance discontinuities as well as ground shifting,noise margin limits,and total termination loading must be taken into account.DS100888-5C L includes load and test jig capacitance.S 1=V CC for t PZL and t PLZ measurements.S 1=GND for t PZH and t PHZ measurements.FIGURE 3.Receiver TRI-STATE Delay Test CircuitDS100888-6FIGURE 4.Receiver TRI-STATE Delay WaveformsBalanced SystemDS100888-7FIGURE 5.Point-to-Point Application4Applications Information(Continued)The DS90LV048A differential line receiver is capable of de-tecting signals as low as100mV,over a±1V common-mode range centered around+1.2V.This is related to the driver off-set voltage which is typically+1.2V.The driven signal is cen-tered around this voltage and may shift±1V around this cen-ter point.The±1V shifting may be the result of a ground potential difference between the driver’s ground referenceand the receiver’s ground reference,the common-mode ef-fects of coupled noise,or a combination of the two.The ACparameters of both receiver input pins are optimized for arecommended operating input voltage range of0V to+2.4V(measured from each pin to ground).The device will operatefor receiver input voltages up to V CC,but exceeding V CC willturn on the ESD protection circuitry which will clamp the busvoltages.The DS90LV048A has a flow-through pinout that allows foreasy PCB layout.The LVDS signals on one side of the de-vice easily allows for matching electrical lengths of the differ-ential pair trace lines between the driver and the receiver aswell as allowing the trace lines to be close together to couplenoise as common-mode.Noise isolation is achieved with theLVDS signals on one side of the device and the TTL signalson the other side.Power Decoupling Recommendations:Bypass capacitors must be used on power e highfrequency ceramic(surface mount is recommended)0.1µFand0.001µF capacitors in parallel at the power supply pinwith the smallest value capacitor closest to the device supplypin.Additional scattered capacitors over the printed circuitboard will improve decoupling.Multiple vias should be usedto connect the decoupling capacitors to the power planes.A10µF(35V)or greater solid tantalum capacitor should beconnected at the power entry point on the printed circuitboard between the supply and ground.PC Board considerations:Use at least4PCB layers(top to bottom);LVDS signals,ground,power,TTL signals.Isolate TTL signals from LVDS signals,otherwise the TTLmay couple onto the LVDS lines.It is best to put TTL andLVDS signals on different layers which are isolated by apower/ground plane(s)Keep drivers and receivers as close to the(LVDS port side)connectors as possible.Differential Traces:Use controlled impedance traces which match the differen-tial impedance of your transmission medium(ie.cable)andtermination resistor.Run the differential pair trace lines asclose together as possible as soon as they leave the IC(stubs should be<10mm long).This will help eliminate re-flections and ensure noise is coupled as common-mode.Infact,we have seen that differential signals which are1mmapart radiate far less noise than traces3mm apart sincemagnetic field cancellation is much better with the closertraces.In addition,noise induced on the differential lines ismuch more likely to appear as common-mode which is re-jected by the receiver.Match electrical lengths between traces to reduce skew.Skew between the signals of a pair means a phase differ-ence between signals which destroys the magnetic field can-cellation benefits of differential signals and EMI will result.(Note the velocity of propagation,v=c/Er where c(thespeed of light)=0.2997mm/ps or0.0118in/ps).Do not relysolely on the autoroute function for differential traces.Care-fully review dimensions to match differential impedance andprovide isolation for the differential lines.Minimize the num-ber or vias and other discontinuities on the line.Avoid90˚turns(these cause impedance discontinuities).Use arcs or45˚bevels.Within a pair of traces,the distance between the two tracesshould be minimized to maintain common-mode rejection ofthe receivers.On the printed circuit board,this distanceshould remain constant to avoid discontinuities in differentialimpedance.Minor violations at connection points are allow-able.Termination:Use a termination resistor which best matches the differen-tial impedance or your transmission line.The resistor shouldbe between90Ωand130Ω.Remember that the currentmode outputs need the termination resistor to generate thedifferential voltage.LVDS will not work without resistor termi-nation.Typically,connecting a single resistor across the pairat the receiver end will suffice.Surface mount1%to2%resistors are best.PCB stubs,component lead,and the distance from the termination to thereceiver inputs should be minimized.The distance betweenthe termination resistor and the receiver should be<10mm(12mm MAX)Probing LVDS Transmission Lines:Always use high impedance(>100kΩ),lowcapacitance(<2pF)scope probes with a wide bandwidth(1GHz)scope.Improper probing will give deceiving results.Cables and Connectors,General Comments:When choosing cable and connectors for LVDS it is impor-tant to remember:Use controlled impedance media.The cables and connec-tors you use should have a matched differential impedanceof about100Ω.They should not introduce major impedancediscontinuities.Balanced cables(e.g.twisted pair)are usually better thanunbalanced cables(ribbon cable,simple coax.)for noise re-duction and signal quality.Balanced cables tend to generateless EMI due to field canceling effects and also tend to pickup electromagnetic radiation a common-mode(not differen-tial mode)noise which is rejected by the receiver.For cable distances<0.5M,most cables can be made towork effectively.For distances0.5M≤d≤10M,CAT3(cat-egory3)twisted pair cable works well,is readily availableand relatively inexpensive.Fail-Safe Feature:The LVDS receiver is a high gain,high speed device thatamplifies a small differential signal(20mV)to CMOS logiclevels.Due to the high gain and tight threshold of the re-ceiver,care should be taken to prevent noise from appearingas a valid signal.The receiver’s internal fail-safe circuitry is designed tosource/sink a small amount of current,providing fail-safeprotection(a stable known state of HIGH output voltage)forfloating,terminated or shorted receiver inputs.1.Open Input Pins.The DS90LV048A is a quad receiverdevice,and if an application requires only1,2or3re-ceivers,the unused channel(s)inputs should be leftOPEN.Do not tie unused receiver inputs to ground orany other voltages.The input is biased by internal highvalue pull up and pull down resistors to set the output toa HIGH state.This internal circuitry will guarantee aHIGH,stable output state for open inputs. 5Applications Information(Continued)2.Terminated Input.If the driver is disconnected (cable unplugged),or if the driver is in a TRI-STATE or power-off condition,the receiver output will again be in a HIGH state,even with the end of cable 100Ωtermination resis-tor across the input pins.The unplugged cable can be-come a floating antenna which can pick up noise.If the cable picks up more than 10mV of differential noise,the receiver may see the noise as a valid signal and switch.To insure that any noise is seen as common-mode and not differential,a balanced interconnect should be used.Twisted pair cable will offer better balance than flat rib-bon cable.3.Shorted Inputs.If a fault condition occurs that shortsthe receiver inputs together,thus resulting in a 0V differ-ential input voltage,the receiver output will remain in a HIGH state.Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V).It is only supported with inputs shorted and no ex-ternal common-mode voltage applied.External lower value pull up and pull down resistors (for a stronger bias)may be used to boost fail-safe in the presence of higher noise levels.The pull up and pull down resistors should be in the 5k Ωto 15k Ωrange to minimize loading and waveform distortion to the driver.The common-mode bias point should be set to approximately 1.2V (less than 1.75V)to be compatible with the internal circuitry.Pin DescriptionsPin Description2,3,6,7R IN+Non-inverting receiver input pin 1,4,5,8R IN−Inverting receiver input pin 10,11,14,R OUTReceiver output pin1516ENReceiver enable pin:When EN is low,the receiver is disabled.When EN is high and EN*is low or open,the receiver is enabled.If both EN and EN*are open circuit,then the receiver is disabled.9EN*Receiver enable pin:When EN*is high,the receiver is disabled.When EN*is low or open and EN is high,the receiver isenabled.If both EN and EN*are open circuit,then the receiver is disabled.13V CC Power supply pin,+3.3V ±0.3V 12GNDGround pinOrdering InformationOperating Package Type/Order NumberTemperature Number −40˚C to +85˚C SOP/M16A DS90LV048ATM −40˚C to +85˚CTSSOP/MTC16DS90LV048ATMTC Typical Performance CurvesOutput High Voltage vs Power Supply VoltageDS100888-12Output Low Voltage vs Power Supply VoltageDS100888-13 6Typical Performance Curves(Continued)Output Short Circuit Current vsPower Supply VoltageDS100888-14Output TRI-STATE Current vsPower Supply VoltageDS100888-15Differential Transition Voltage vsPower Supply VoltageDS100888-16Power Supply Currentvs FrequencyDS100888-17Power Supply Current vsAmbient TemperatureDS100888-18Differential Propagation Delay vsPower Supply VoltageDS100888-19 7Typical Performance Curves(Continued)Differential Propagation Delay vs Ambient TemperatureDS100888-20Differential Propagation Delay vs Differential Input VoltageDS100888-21Differential Propagation Delay vs Common-Mode Voltage DS100888-22Differential Skew vs Power Supply VoltageDS100888-23Differential Skew vs Ambient Temperature DS100888-24Transition Time vs Power Supply VoltageDS100888-25 8Typical Performance Curves(Continued)Transition Time vsAmbient TemperatureDS100888-269Physical Dimensions inches(millimeters)unless otherwise noted16-Lead(0.150"Wide)Molded Small Outline Package,JEDECOrder Number DS90LV048ATMNS Package Number M16A10Physical Dimensions inches(millimeters)unless otherwise noted(Continued)LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices orsystems which,(a)are intended for surgical implantinto the body,or(b)support or sustain life,andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling,can be reasonably expected to result in asignificant injury to the user.2.A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system,or to affect itssafety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507 16-Lead(0.100"Wide)Molded Thin Shrink Small Outline Package,JEDECOrder Number DS90LV048ATMTCNS Package Number MTC16DS90LV048A3VLVDSQuadCMOSDifferentialLineReceiver National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。
2015 中国纺织0931.实验部分1.1原料：通用级PPTA 树脂（比浓对数粘度度6.8dl/g），超高分子量PPTA 树脂（比浓对数粘度9.2dl/g）河北硅谷化工有限公司提供；96~98 wt％硫酸。
1.2芳纶纤维的制备：分别用烘干的PPTA 树脂和浓硫酸加入双螺杆挤出机先快速低温溶解再进行高温溶解得到均匀的液晶溶液，纺丝液浓度为18wt%，经过过滤脱泡进行纺丝，凝固浴为5%~10%硫酸溶液，温度为2~5℃，制备得到芳纶纤维（AFS920为用通用级PPTA 树脂制得的纤维，AFS921为用超高分子量PPTA树脂与通用级PPTA树脂按照1:9混合纺丝制得的纤维）；将AFS921纤维采用热辊（五辊，转速200m/min，温度为250℃，拉伸比为3%）与热箱（温度为500-525-550-525-500℃几段分布，转速为200m/min，拉伸比为2%）热定型和热拉伸处理，得到高强度高模量芳纶纤维（AFS940）。
1.3测试表征：比浓对数黏度测定、烷基化PPTA 分子量（GPC）测试、热性能分析、结晶度测试、纤维的力学性能2.结果与讨论2.1 PPTA 树脂的表征：对两种PPTA 树脂进行了红外表征对其结超越杜邦的中国芳纶超高分子量PPTA树脂及其高模量芳纶完成作者孔海娟，叶盛，刘静，秦明林，李双江，沈伟波，刘新东，杨鹏，滕翠青，韩克清，余木火完成单位东华大学纤维材料改性国家重点实验室，材料科学与工程学院东华大学民用航空复合材料协同创新中心河北硅谷化工有限公司选登理由本论文获得2014“中国化学纤维工业协会·恒逸基金”学术论文一等奖。
获蒋士成、姚穆、孙晋良、俞建勇四位院士共同推荐。
论文的选题来自生产实践第一线，也是学科前沿，PPTA 纤维是国家重点支持的战略性新材料，是我国与美国杜邦和日本帝人相距最大的高性能纤维，尤其是在高模量纤维领域。
本文通过采用高分子量PPTA 与超高分子量PPTA 共混研究，有效解决了纤维纺丝过程中的可纺性和纺丝稳定性，而且制得的PPTA 纤维的分子量降解少，纤维的强度和模量都高于杜邦的Kevlar29和49。
东华大学 2018 年博士研究生招生目录学院：(001)纺织学院专业代码：082101专业名称：纺织工程学位类型：学术型本学科拟招生人数:16 (说明：招生人数以教育部最终下达招生人数为准，此处仅作参考，可能会有调整)学科简介：本学科点 1986 年获得博士学位授予权，1987 年被国家教委评为国家重点学科，1996 年确定为上海市重点学科，2002 年再次确认为国家重点学科，是我校“纺织科学与工程”博士 后流动站和“211 工程”建设的重点组成学科之一。
学科点现有教授 18 名、博士生导师 17 人，副教授 20 余名，目前在读的博士生和博士后共 30 余名。
本学科点在致力于工程技术研究，直接面向国民经济主战场的同时，更注重工程科学 研究，即将应用基础研究和不同学科间的交叉、渗透，从而在纺织流体加工、纺织复合材料、 生物医用材料、高性能合成浆料及浆纱工艺的智能检测与评定、智能化关键部件与装备等方面 形成了自己的特色。
目前的主要研究方向有纤维制品加工、工程与技术纤维材料与制品、纤维 加工的化学与生物技术、和纺织产业经济与管理。
本学科点有较强的研究与开发能力，近年来承担国家、部委、省市级重大科研项目 50 余项，获国家及省、部级的教学、科研成果奖 30 余项。
目前正在进行的有国家 863 计划项目、 国家自然科学基金项目、省部级重大科研项目等 20 余项。
近年毕业的博士生学位论文中，有两 篇被评为全国优秀博士论文，另有六篇被评为上海市优秀博士论文。
本学科点除培养来自全国各地的博士研究生外，还培养来自国外的博士研究生及高级 访问学者，并接受博士后进站工作。
至今本学科点已培养和正在培养的国内外博士生近百名。
本学科点在与美国、日本、英国、德国、法国、澳大利亚、韩国、香港和台湾等国家和地 区的学术交流方面较活跃，并与上述国家和地区的部分高校联合培养博士生。
不少著名大型企 业的技术骨干也在本学科点攻读在职博士学位。
